From nobody Sat Nov 30 05:30:09 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F53518BBBD; Thu, 12 Sep 2024 06:16:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726121794; cv=none; b=tgc1aHdpoC6f8IvSn1GJUYvBNV9wBIpFYYgjK4aZPzhpj8s413zc+odDFhdoILAfzbCjtw5XLtlF/7t6OisUEFxBmiBLlDmPSgjdzQZyt5qSFWy0V7AEWL43SmiWX41jo5PbPiXugOejqxBQ5c4agkdNvX+btBlt5hutMWHWokI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726121794; c=relaxed/simple; bh=1qsKQ18lRJCj0t3VY6y/f+9bi9nLWLMMKn62KN7AjyU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RngNNlD6hu9HspApR9blcbmfG8kDXhJV+CnmCzBIyRXbsFnOGD4qf5LEcx3vqaGJGozDCQVY21ucQdg4lCxovI5V+sJqUR6POCTWl75RjdtZIvxOEtA5W4Ja84PJOq74PXqrGJGR5S/avtApStJTPXJ8qoX1BTKSIgDo/xOXnWk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=MLQ9BA8E; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="MLQ9BA8E" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48C2LDha006693; Thu, 12 Sep 2024 06:16:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 2SqrfzuY58oS8x2Y2XOpO1qEDu8sn6n/1vpUMZVUcf4=; b=MLQ9BA8EcFOFfO0X YwOjUT0fo+905iE1ocegxfRL1yeVPxeqaRmWmFmr7B5/fAVswr6vcJJYjP+d4ggs xD0R/rM79hSOhiihuQFfpq7BOcGD0FCcHEvFqkmsCYiV2wpXcouelQfKdomRgbhl gS4JQSGWmFaJybJG7fNqjW4kqzvNdnPaCAzK+lnKyXDzMHsZr83huwn0mq/sTkkq HoaUOLNYvbI0MKrsfmb5XJvKulIHVgKaLvaToFdK1ObKrbGRXqQaqRniz+Cmiud/ nRo5s1ogQff4xw3QBIuoAc0DudyjRtrwDZneMdQKMe2s9c3pIFsU1SPTcISJ0dQz oorbIA== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41gy6pc1nr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Sep 2024 06:16:04 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48C6G3or024238 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Sep 2024 06:16:03 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Sep 2024 23:15:58 -0700 From: Md Sadre Alam To: , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v9 7/8] arm64: dts: qcom: ipq9574: Add SPI nand support Date: Thu, 12 Sep 2024 11:45:02 +0530 Message-ID: <20240912061503.3468147-8-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240912061503.3468147-1-quic_mdalam@quicinc.com> References: <20240912061503.3468147-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 6ypX8UBGZtAMXK2VxXlIEfzYWuDgnA6Q X-Proofpoint-GUID: 6ypX8UBGZtAMXK2VxXlIEfzYWuDgnA6Q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 spamscore=0 phishscore=0 impostorscore=0 suspectscore=0 mlxscore=0 malwarescore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409120043 Content-Type: text/plain; charset="utf-8" Add SPI NAND support for ipq9574 SoC. Signed-off-by: Md Sadre Alam --- Change in [v9] * No change Change in [v8] * No change Change in [v7] * No change Change in [v6] * No change Change in [v5] * No change Change in [v4] * No change Change in [v3] * Updated gpio number as per pin control driver * Fixed alignment issue Change in [v2] * Added initial enablement for spi-nand=20 Change in [v1] * Posted as RFC patch for design review .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 43 +++++++++++++++++++ arch/arm64/boot/dts/qcom/ipq9574.dtsi | 27 ++++++++++++ 2 files changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/= boot/dts/qcom/ipq9574-rdp-common.dtsi index 91e104b0f865..6429a6b3b903 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi @@ -139,6 +139,49 @@ gpio_leds_default: gpio-leds-default-state { drive-strength =3D <8>; bias-pull-up; }; + + qpic_snand_default_state: qpic-snand-default-state { + clock-pins { + pins =3D "gpio5"; + function =3D "qspi_clk"; + drive-strength =3D <8>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio4"; + function =3D "qspi_cs"; + drive-strength =3D <8>; + bias-disable; + }; + + data-pins { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "qspi_data"; + drive-strength =3D <8>; + bias-disable; + }; + }; +}; + +&qpic_bam { + status =3D "okay"; +}; + +&qpic_nand { + pinctrl-0 =3D <&qpic_snand_default_state>; + pinctrl-names =3D "default"; + status =3D "okay"; + + flash@0 { + compatible =3D "spi-nand"; + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + nand-ecc-engine =3D <&qpic_nand>; + nand-ecc-strength =3D <4>; + nand-ecc-step-size =3D <512>; + }; }; =20 &usb_0_dwc3 { diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qc= om/ipq9574.dtsi index 08a82a5cf667..65e70b33c587 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -330,6 +330,33 @@ tcsr: syscon@1937000 { reg =3D <0x01937000 0x21000>; }; =20 + qpic_bam: dma-controller@7984000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x7984000 0x1c000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QPIC_AHB_CLK>; + clock-names =3D "bam_clk"; + #dma-cells =3D <1>; + qcom,ee =3D <0>; + status =3D "disabled"; + }; + + qpic_nand: spi@79b0000 { + compatible =3D "qcom,spi-qpic-snand"; + reg =3D <0x79b0000 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>, + <&gcc GCC_QPIC_IO_MACRO_CLK>; + clock-names =3D "core", "aon", "iom"; + dmas =3D <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names =3D "tx", "rx", "cmd"; + status =3D "disabled"; + }; + sdhc_1: mmc@7804000 { compatible =3D "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x07804000 0x1000>, --=20 2.34.1