From nobody Sat Nov 30 03:41:48 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E01BB126BE5; Thu, 12 Sep 2024 06:15:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726121760; cv=none; b=CBys6RanWlktTySFnowpgi3QEg7ayXnHrbNWB81T0mevtJlpuac2UGcrxqPj7ee2Ke9dZL+rXdSUAJrSfJyhtjP3xFpkgcwGjR3rHMPOkFyB9ub0gdiF+MF18aHBMCpdSTRMDamBE4K9pG8JHmSEQG/Ifjn7nqQ+gJ5SKJa/f3U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726121760; c=relaxed/simple; bh=tZOZBuewPMHa7GYQc1weh9CXlvbfzgZNJezEbLiFqeg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=EVaSgWsibFqNjxRZQVFZHAv9wNwFHj1e/YFb+rFsEzXnxyI4EIKqYhRTuAuxlCTcJwxKAMWE/sukSXYvpmTrlVsM1u5CWTGIVn5H4vFVK3vIUWyvh3OJvJ2vOTHLx4I2PtH/YwDdc2VJOwyEniKMPtZLNcSitr9jE1P6m6P502U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Ccfj5cr3; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Ccfj5cr3" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48C2KqwT007652; Thu, 12 Sep 2024 06:15:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 1u6hAK53BFy2xr2q5A3du731E6lIVLbDFAFvDE2hXeQ=; b=Ccfj5cr3nGGv9tn/ nfuOEcXYDmB93c4wygWoupwLk2KLVZ8rNHJ5dbRBp896EQMOe21u3BpqV+fblr5K sD4kVSxVw/tRivBAJKidAfRZiU29VUkMkuscrrRnILDdP9ci7r1hnEWWxSdmEcLD GJEcHYDvPXaO6zyvpw/wfTARVTwh24IbfBr9U12sf5ye5gaM9vN5vdlGwCUK1bA2 NitcZtz3NomZnO5N7Jgwq1vLE56AhMcEE2bhqDK8aRlfmliPZ0956bo4BZE4ZkDr co06D2zk0gZiwjjCv71R68h10KxKX+Wwx2JtFWDXbl80E125Hwtv/jL4Kxyxc2Hn ITyGAw== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41j6gn0a75-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Sep 2024 06:15:30 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48C6FTuK007627 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Sep 2024 06:15:29 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Sep 2024 23:15:23 -0700 From: Md Sadre Alam To: , , , , , , , , , , , , , , , CC: , , , Krzysztof Kozlowski Subject: [PATCH v9 1/8] spi: dt-bindings: Introduce qcom,spi-qpic-snand Date: Thu, 12 Sep 2024 11:44:56 +0530 Message-ID: <20240912061503.3468147-2-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240912061503.3468147-1-quic_mdalam@quicinc.com> References: <20240912061503.3468147-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 8znoFeMDr4zTAGWawYjdkzmaSKIbuITw X-Proofpoint-GUID: 8znoFeMDr4zTAGWawYjdkzmaSKIbuITw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 clxscore=1015 phishscore=0 mlxlogscore=999 lowpriorityscore=0 suspectscore=0 mlxscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409120042 Content-Type: text/plain; charset="utf-8" Document the QPIC-SPI-NAND flash controller present in the IPQ SoCs. It can work both in serial and parallel mode and supports typical SPI-NAND page cache operations. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Md Sadre Alam --- Change in [v9] * No change Change in [v8] * No change Change in [v7] * No change Change in [v6] * No change Change in [v5] * No change Change in [v4] * Fix spelling mistake in HW description * Added commit message * Removed '|' from description * Removed minItems in clock * Added blank line * Removed co-developed by Change in [v3] * Updated commit message, removed "dt-bindings" from commit message * Updated compatible name as file name * Added hardware description * Documented clock-name * Moved dma-names property to top * Droped unused label "qpic_nand" * Fixed indentation in example dt node Change in [v2] * Added initial support for dt-bindings Change in [v1] * This patch was not included in [v1] .../bindings/spi/qcom,spi-qpic-snand.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qpic-sna= nd.yaml diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml= b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml new file mode 100644 index 000000000000..f0d9f7643849 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QPIC NAND controller + +maintainers: + - Md sadre Alam + +description: + The QCOM QPIC-SPI-NAND flash controller is an extended version of + the QCOM QPIC NAND flash controller. It can work both in serial + and parallel mode. It supports typical SPI-NAND page cache + operations in single, dual or quad IO mode with pipelined ECC + encoding/decoding using the QPIC ECC HW engine. + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + enum: + - qcom,spi-qpic-snand + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: core + - const: aon + - const: iom + + dmas: + items: + - description: tx DMA channel + - description: rx DMA channel + - description: cmd DMA channel + + dma-names: + items: + - const: tx + - const: rx + - const: cmd + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + spi@79b0000 { + compatible =3D "qcom,spi-qpic-snand"; + reg =3D <0x1ac00000 0x800>; + + clocks =3D <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>, + <&gcc GCC_QPIC_IO_MACRO_CLK>; + clock-names =3D "core", "aon", "iom"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + flash@0 { + compatible =3D "spi-nand"; + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + nand-ecc-engine =3D <&qpic_nand>; + nand-ecc-strength =3D <4>; + nand-ecc-step-size =3D <512>; + }; + }; --=20 2.34.1 From nobody Sat Nov 30 03:41:48 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB66A188937; Thu, 12 Sep 2024 06:16:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726121773; cv=none; b=qG+JfEpLKNIzM8hXBrrCnU61hnzVE/sHI3Hrbk7Ox+mcNQ3s5qvddFVmqQ2QCYkmTrehO/6UxzvY3snH+JOZFFICwRGxzpl+UeYXnDcXihHIEQ0OJtaexFz3q8XCapkiP7o/quPN4vgbryAMfgPC+JnsrI91m7rbtMP++NV3gk8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726121773; c=relaxed/simple; bh=82kFPpZPd0dksCBu82SxM/vWOXKWshG3TSIsJ62q6+k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qREKlE4MYFd3OnpRCjFjlUT4KUUJY+wOD1YeyWrgz6DbZzyzl91absFL/N1B0CF0H95AwxVoN3PVr6msdrvuiQ0HtPXLEzQfdfcxvqOs1PHpcieSxRtMORmKVztJAmYIgfhTBHYNP8R49tu3trPzsgmX9Dvlzrxds3+b1OFF3t8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=bvwJM+dr; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="bvwJM+dr" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48C2LIBA007214; Thu, 12 Sep 2024 06:15:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Zxm6VRvBmNG/UK0dSeKagu+8T2hVmsXIjsYNDALbfLs=; b=bvwJM+drIcfGVMB7 ak0tZcJgEFBhHU37/b5XHOMGS54/xkFGg34+GKPf9pRn7XGzEBSdoA5mrQlw1xRp q/N2Vc8JPMDPsnN99/n4G6nQ1zCqaAvIKRjO4WdkZb0k5wa6V/jkvkFW4q+KAjtE OTVVmDSPxPPlnnGnDjnv2zOOTkpHCnh6VVrICeADIMpCs22DpRNbkJN799ioKaaU 4GM7zHL5AlccX+b6VGjOQ4DfDvpFTy/3ZX1A4VGTKhOSr1yir53p3MHO2POI58kR S6TCMhZAnJmh3EMqHIm5zT2FBKy2DWhZsJRckig461yV14qD9TwP1sfu9w68mAse FMhPyQ== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41gy5rm14w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Sep 2024 06:15:36 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48C6FZx6023485 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Sep 2024 06:15:35 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Sep 2024 23:15:29 -0700 From: Md Sadre Alam To: , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v9 2/8] mtd: rawnand: qcom: cleanup qcom_nandc driver Date: Thu, 12 Sep 2024 11:44:57 +0530 Message-ID: <20240912061503.3468147-3-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240912061503.3468147-1-quic_mdalam@quicinc.com> References: <20240912061503.3468147-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: JXLTL41IH3lLy_NuWMLZSpafFxO7Nr2U X-Proofpoint-ORIG-GUID: JXLTL41IH3lLy_NuWMLZSpafFxO7Nr2U X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 clxscore=1015 malwarescore=0 bulkscore=0 lowpriorityscore=0 adultscore=0 mlxscore=0 impostorscore=0 priorityscore=1501 mlxlogscore=999 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409120043 Content-Type: text/plain; charset="utf-8" cleanup qcom_nandc driver as below - Remove register value indirection api - Remove set_reg() api - Convert read_loc_first & read_loc_last macro to function - Renamed multiple variables Signed-off-by: Md Sadre Alam --- Change in [v9] * Changed type of cmd1, vld to u32 from __le32 in qcom_nand_controller structure * Changed type of cfg0, cfg1, cfg0_raw, cfg1_raw, clrflashstatus, ecc_buf_cfg, ecc_bch_cfg, clrreadstatus to u32 in qcom_nand_host structure * In nandc_set_read_loc_first() api added cpu_to_le32() macro to fix compilation warning reported by kernel test bot * In nandc_set_read_loc_last() api added cpu_to_le32() macro to fix compilation warning reported by kernel test bot * Changed data type of cw_offset, read_size, is_last_read_loc to u32 in nandc_set_read_loc() api to fix compilation warning reported by kernel test bot * In set_address() api added cpu_to_le32() macro to fix compilation warning reported by kernel test bot * In update_rw_regs() api added cpu_to_le32() macro to fix compilation warning reported by kernel test bot * In qcom_op_cmd_mapping() api added cpu_to_le32() macro to fix compilation warning reported by kernel test bot * In qcom_read_status_exec() api added cpu_to_le32() macro to fix compilati= on warning reported by kernel test bot * In qcom_read_id_type_exec() api added cpu_to_le32() macro to fix compilat= ion warning reported by kernel test bot * In qcom_misc_cmd_type_exec() api added cpu_to_le32() macro to fix compila= tion warning reported by kernel test bot * In qcom_param_page_type_exec() api added cpu_to_le32() macro to fix compilation warning reported by kernel test bot=20 Change in [v8] * Fixed compilation warning reported by kernel test robot * Added "chip" description in nandc_set_read_loc_first() * Added "chip" description in nandc_set_read_loc_last() * Changed data type of read_location0, read_location1,=20 read_location2, read_location3, read_location_last0, read_location_last1, read_location_last2, read_location_last3, addr0, addr1, cmd, cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg, clrflashstatus, clrreadstatus, orig_cmd1, orig_vld to=20 __le32 to fix compilation warning reported by kernel test robot =20 Change in [v7] * No change Change in [v6] * No change Change in [v5] * Cleand up raw nand driver. * Removed register value indirection * Removed set_reg() api. Change in [v4] * This patch was not included in [v4] Change in [v3] * This patch was not included in [v3] Change in [v2] * This patch was not included in [v2] Change in [v1] * This patch was not included in [v1] drivers/mtd/nand/raw/qcom_nandc.c | 506 ++++++++++++++---------------- 1 file changed, 229 insertions(+), 277 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_= nandc.c index b8cff9240b28..d134329330fe 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -189,17 +189,6 @@ #define ECC_BCH_4BIT BIT(2) #define ECC_BCH_8BIT BIT(3) =20 -#define nandc_set_read_loc_first(chip, reg, cw_offset, read_size, is_last_= read_loc) \ -nandc_set_reg(chip, reg, \ - ((cw_offset) << READ_LOCATION_OFFSET) | \ - ((read_size) << READ_LOCATION_SIZE) | \ - ((is_last_read_loc) << READ_LOCATION_LAST)) - -#define nandc_set_read_loc_last(chip, reg, cw_offset, read_size, is_last_r= ead_loc) \ -nandc_set_reg(chip, reg, \ - ((cw_offset) << READ_LOCATION_OFFSET) | \ - ((read_size) << READ_LOCATION_SIZE) | \ - ((is_last_read_loc) << READ_LOCATION_LAST)) /* * Returns the actual register address for all NAND_DEV_ registers * (i.e. NAND_DEV_CMD0, NAND_DEV_CMD1, NAND_DEV_CMD2 and NAND_DEV_CMD_VLD) @@ -257,8 +246,6 @@ nandc_set_reg(chip, reg, \ * @tx_sgl_start - start index in data sgl for tx. * @rx_sgl_pos - current index in data sgl for rx. * @rx_sgl_start - start index in data sgl for rx. - * @wait_second_completion - wait for second DMA desc completion before ma= king - * the NAND transfer completion. */ struct bam_transaction { struct bam_cmd_element *bam_ce; @@ -275,7 +262,6 @@ struct bam_transaction { u32 tx_sgl_start; u32 rx_sgl_pos; u32 rx_sgl_start; - bool wait_second_completion; }; =20 /* @@ -471,9 +457,9 @@ struct qcom_op { unsigned int data_instr_idx; unsigned int rdy_timeout_ms; unsigned int rdy_delay_ns; - u32 addr1_reg; - u32 addr2_reg; - u32 cmd_reg; + __le32 addr1_reg; + __le32 addr2_reg; + __le32 cmd_reg; u8 flag; }; =20 @@ -549,17 +535,17 @@ struct qcom_nand_host { * among different NAND controllers. * @ecc_modes - ecc mode for NAND * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset - * @is_bam - whether NAND controller is using BAM - * @is_qpic - whether NAND CTRL is part of qpic IP - * @qpic_v2 - flag to indicate QPIC IP version 2 + * @supports_bam - whether NAND controller is using BAM + * @nandc_part_of_qpic - whether NAND controller is part of qpic IP + * @qpic_version2 - flag to indicate QPIC IP version 2 * @use_codeword_fixup - whether NAND has different layout for boot partit= ions */ struct qcom_nandc_props { u32 ecc_modes; u32 dev_cmd_reg_start; - bool is_bam; - bool is_qpic; - bool qpic_v2; + bool supports_bam; + bool nandc_part_of_qpic; + bool qpic_version2; bool use_codeword_fixup; }; =20 @@ -613,19 +599,11 @@ static void clear_bam_transaction(struct qcom_nand_co= ntroller *nandc) { struct bam_transaction *bam_txn =3D nandc->bam_txn; =20 - if (!nandc->props->is_bam) + if (!nandc->props->supports_bam) return; =20 - bam_txn->bam_ce_pos =3D 0; - bam_txn->bam_ce_start =3D 0; - bam_txn->cmd_sgl_pos =3D 0; - bam_txn->cmd_sgl_start =3D 0; - bam_txn->tx_sgl_pos =3D 0; - bam_txn->tx_sgl_start =3D 0; - bam_txn->rx_sgl_pos =3D 0; - bam_txn->rx_sgl_start =3D 0; + memset(&bam_txn->bam_ce_pos, 0, sizeof(u32) * 8); bam_txn->last_data_desc =3D NULL; - bam_txn->wait_second_completion =3D false; =20 sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage * QPIC_PER_CW_CMD_SGL); @@ -640,17 +618,7 @@ static void qpic_bam_dma_done(void *data) { struct bam_transaction *bam_txn =3D data; =20 - /* - * In case of data transfer with NAND, 2 callbacks will be generated. - * One for command channel and another one for data channel. - * If current transaction has data descriptors - * (i.e. wait_second_completion is true), then set this to false - * and wait for second DMA descriptor completion. - */ - if (bam_txn->wait_second_completion) - bam_txn->wait_second_completion =3D false; - else - complete(&bam_txn->txn_done); + complete(&bam_txn->txn_done); } =20 static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *c= hip) @@ -676,10 +644,9 @@ static inline void nandc_write(struct qcom_nand_contro= ller *nandc, int offset, iowrite32(val, nandc->base + offset); } =20 -static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nan= dc, - bool is_cpu) +static inline void nandc_dev_to_mem(struct qcom_nand_controller *nandc, bo= ol is_cpu) { - if (!nandc->props->is_bam) + if (!nandc->props->supports_bam) return; =20 if (is_cpu) @@ -694,93 +661,90 @@ static inline void nandc_read_buffer_sync(struct qcom= _nand_controller *nandc, DMA_FROM_DEVICE); } =20 -static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset) -{ - switch (offset) { - case NAND_FLASH_CMD: - return ®s->cmd; - case NAND_ADDR0: - return ®s->addr0; - case NAND_ADDR1: - return ®s->addr1; - case NAND_FLASH_CHIP_SELECT: - return ®s->chip_sel; - case NAND_EXEC_CMD: - return ®s->exec; - case NAND_FLASH_STATUS: - return ®s->clrflashstatus; - case NAND_DEV0_CFG0: - return ®s->cfg0; - case NAND_DEV0_CFG1: - return ®s->cfg1; - case NAND_DEV0_ECC_CFG: - return ®s->ecc_bch_cfg; - case NAND_READ_STATUS: - return ®s->clrreadstatus; - case NAND_DEV_CMD1: - return ®s->cmd1; - case NAND_DEV_CMD1_RESTORE: - return ®s->orig_cmd1; - case NAND_DEV_CMD_VLD: - return ®s->vld; - case NAND_DEV_CMD_VLD_RESTORE: - return ®s->orig_vld; - case NAND_EBI2_ECC_BUF_CFG: - return ®s->ecc_buf_cfg; - case NAND_READ_LOCATION_0: - return ®s->read_location0; - case NAND_READ_LOCATION_1: - return ®s->read_location1; - case NAND_READ_LOCATION_2: - return ®s->read_location2; - case NAND_READ_LOCATION_3: - return ®s->read_location3; - case NAND_READ_LOCATION_LAST_CW_0: - return ®s->read_location_last0; - case NAND_READ_LOCATION_LAST_CW_1: - return ®s->read_location_last1; - case NAND_READ_LOCATION_LAST_CW_2: - return ®s->read_location_last2; - case NAND_READ_LOCATION_LAST_CW_3: - return ®s->read_location_last3; - default: - return NULL; - } +/* Helper to check the code word, whether it is last cw or not */ +static bool qcom_nandc_is_last_cw(struct nand_ecc_ctrl *ecc, int cw) +{ + return cw =3D=3D (ecc->steps - 1); } =20 -static void nandc_set_reg(struct nand_chip *chip, int offset, - u32 val) +/** + * nandc_set_read_loc_first() - to set read location first register + * @chip: NAND Private Flash Chip Data + * @reg_base: location register base + * @cw_offset: code word offset + * @read_size: code word read length + * @is_last_read_loc: is this the last read location + * + * This function will set location register value + */ +static void nandc_set_read_loc_first(struct nand_chip *chip, + int reg_base, u32 cw_offset, + u32 read_size, u32 is_last_read_loc) { struct qcom_nand_controller *nandc =3D get_qcom_nand_controller(chip); - struct nandc_regs *regs =3D nandc->regs; - __le32 *reg; - - reg =3D offset_to_nandc_reg(regs, offset); + __le32 locreg_val; + u32 val =3D (((cw_offset) << READ_LOCATION_OFFSET) | + ((read_size) << READ_LOCATION_SIZE) | + ((is_last_read_loc) << READ_LOCATION_LAST)); + + locreg_val =3D cpu_to_le32(val); + + if (reg_base =3D=3D NAND_READ_LOCATION_0) + nandc->regs->read_location0 =3D locreg_val; + else if (reg_base =3D=3D NAND_READ_LOCATION_1) + nandc->regs->read_location1 =3D locreg_val; + else if (reg_base =3D=3D NAND_READ_LOCATION_2) + nandc->regs->read_location2 =3D locreg_val; + else if (reg_base =3D=3D NAND_READ_LOCATION_3) + nandc->regs->read_location3 =3D locreg_val; +} + +/** + * nandc_set_read_loc_last - to set read location last register + * @chip: NAND Private Flash Chip Data + * @reg_base: location register base + * @cw_offset: code word offset + * @read_size: code word read length + * @is_last_read_loc: is this the last read location + * + * This function will set location last register value + */ +static void nandc_set_read_loc_last(struct nand_chip *chip, + int reg_base, u32 cw_offset, + u32 read_size, u32 is_last_read_loc) +{ + struct qcom_nand_controller *nandc =3D get_qcom_nand_controller(chip); + __le32 locreg_val; + u32 val =3D (((cw_offset) << READ_LOCATION_OFFSET) | + ((read_size) << READ_LOCATION_SIZE) | + ((is_last_read_loc) << READ_LOCATION_LAST)); =20 - if (reg) - *reg =3D cpu_to_le32(val); -} + locreg_val =3D cpu_to_le32(val); =20 -/* Helper to check the code word, whether it is last cw or not */ -static bool qcom_nandc_is_last_cw(struct nand_ecc_ctrl *ecc, int cw) -{ - return cw =3D=3D (ecc->steps - 1); + if (reg_base =3D=3D NAND_READ_LOCATION_LAST_CW_0) + nandc->regs->read_location_last0 =3D locreg_val; + else if (reg_base =3D=3D NAND_READ_LOCATION_LAST_CW_1) + nandc->regs->read_location_last1 =3D locreg_val; + else if (reg_base =3D=3D NAND_READ_LOCATION_LAST_CW_2) + nandc->regs->read_location_last2 =3D locreg_val; + else if (reg_base =3D=3D NAND_READ_LOCATION_LAST_CW_3) + nandc->regs->read_location_last3 =3D locreg_val; } =20 /* helper to configure location register values */ static void nandc_set_read_loc(struct nand_chip *chip, int cw, int reg, - int cw_offset, int read_size, int is_last_read_loc) + u32 cw_offset, u32 read_size, u32 is_last_read_loc) { struct qcom_nand_controller *nandc =3D get_qcom_nand_controller(chip); struct nand_ecc_ctrl *ecc =3D &chip->ecc; int reg_base =3D NAND_READ_LOCATION_0; =20 - if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw)) + if (nandc->props->qpic_version2 && qcom_nandc_is_last_cw(ecc, cw)) reg_base =3D NAND_READ_LOCATION_LAST_CW_0; =20 reg_base +=3D reg * 4; =20 - if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw)) + if (nandc->props->qpic_version2 && qcom_nandc_is_last_cw(ecc, cw)) return nandc_set_read_loc_last(chip, reg_base, cw_offset, read_size, is_last_read_loc); else @@ -792,12 +756,13 @@ static void nandc_set_read_loc(struct nand_chip *chip= , int cw, int reg, static void set_address(struct qcom_nand_host *host, u16 column, int page) { struct nand_chip *chip =3D &host->chip; + struct qcom_nand_controller *nandc =3D get_qcom_nand_controller(chip); =20 if (chip->options & NAND_BUSWIDTH_16) column >>=3D 1; =20 - nandc_set_reg(chip, NAND_ADDR0, page << 16 | column); - nandc_set_reg(chip, NAND_ADDR1, page >> 16 & 0xff); + nandc->regs->addr0 =3D cpu_to_le32(page << 16 | column); + nandc->regs->addr1 =3D cpu_to_le32(page >> 16 & 0xff); } =20 /* @@ -811,41 +776,43 @@ static void set_address(struct qcom_nand_host *host, = u16 column, int page) static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool r= ead, int cw) { struct nand_chip *chip =3D &host->chip; - u32 cmd, cfg0, cfg1, ecc_bch_cfg; + __le32 cmd, cfg0, cfg1, ecc_bch_cfg; struct qcom_nand_controller *nandc =3D get_qcom_nand_controller(chip); =20 if (read) { if (host->use_ecc) - cmd =3D OP_PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE; + cmd =3D cpu_to_le32(OP_PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE); else - cmd =3D OP_PAGE_READ | PAGE_ACC | LAST_PAGE; + cmd =3D cpu_to_le32(OP_PAGE_READ | PAGE_ACC | LAST_PAGE); } else { - cmd =3D OP_PROGRAM_PAGE | PAGE_ACC | LAST_PAGE; + cmd =3D cpu_to_le32(OP_PROGRAM_PAGE | PAGE_ACC | LAST_PAGE); } =20 if (host->use_ecc) { - cfg0 =3D (host->cfg0 & ~(7U << CW_PER_PAGE)) | - (num_cw - 1) << CW_PER_PAGE; + cfg0 =3D cpu_to_le32((host->cfg0 & ~(7U << CW_PER_PAGE)) | + (num_cw - 1) << CW_PER_PAGE); =20 - cfg1 =3D host->cfg1; - ecc_bch_cfg =3D host->ecc_bch_cfg; + cfg1 =3D cpu_to_le32(host->cfg1); + ecc_bch_cfg =3D cpu_to_le32(host->ecc_bch_cfg); } else { - cfg0 =3D (host->cfg0_raw & ~(7U << CW_PER_PAGE)) | - (num_cw - 1) << CW_PER_PAGE; + cfg0 =3D cpu_to_le32((host->cfg0_raw & ~(7U << CW_PER_PAGE)) | + (num_cw - 1) << CW_PER_PAGE); =20 - cfg1 =3D host->cfg1_raw; - ecc_bch_cfg =3D 1 << ECC_CFG_ECC_DISABLE; + cfg1 =3D cpu_to_le32(host->cfg1_raw); + ecc_bch_cfg =3D cpu_to_le32(1 << ECC_CFG_ECC_DISABLE); } =20 - nandc_set_reg(chip, NAND_FLASH_CMD, cmd); - nandc_set_reg(chip, NAND_DEV0_CFG0, cfg0); - nandc_set_reg(chip, NAND_DEV0_CFG1, cfg1); - nandc_set_reg(chip, NAND_DEV0_ECC_CFG, ecc_bch_cfg); - if (!nandc->props->qpic_v2) - nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg); - nandc_set_reg(chip, NAND_FLASH_STATUS, host->clrflashstatus); - nandc_set_reg(chip, NAND_READ_STATUS, host->clrreadstatus); - nandc_set_reg(chip, NAND_EXEC_CMD, 1); + nandc->regs->cmd =3D cmd; + nandc->regs->cfg0 =3D cfg0; + nandc->regs->cfg1 =3D cfg1; + nandc->regs->ecc_bch_cfg =3D ecc_bch_cfg; + + if (!nandc->props->qpic_version2) + nandc->regs->ecc_buf_cfg =3D cpu_to_le32(host->ecc_buf_cfg); + + nandc->regs->clrflashstatus =3D cpu_to_le32(host->clrflashstatus); + nandc->regs->clrreadstatus =3D cpu_to_le32(host->clrreadstatus); + nandc->regs->exec =3D cpu_to_le32(1); =20 if (read) nandc_set_read_loc(chip, cw, 0, 0, host->use_ecc ? @@ -1121,7 +1088,7 @@ static int read_reg_dma(struct qcom_nand_controller *= nandc, int first, if (first =3D=3D NAND_DEV_CMD_VLD || first =3D=3D NAND_DEV_CMD1) first =3D dev_cmd_reg_addr(nandc, first); =20 - if (nandc->props->is_bam) + if (nandc->props->supports_bam) return prep_bam_dma_desc_cmd(nandc, true, first, vaddr, num_regs, flags); =20 @@ -1136,25 +1103,16 @@ static int read_reg_dma(struct qcom_nand_controller= *nandc, int first, * write_reg_dma: prepares a descriptor to write a given number of * contiguous registers * + * @vaddr: contnigeous memory from where register value will + * be written * @first: offset of the first register in the contiguous block * @num_regs: number of registers to write * @flags: flags to control DMA descriptor preparation */ -static int write_reg_dma(struct qcom_nand_controller *nandc, int first, - int num_regs, unsigned int flags) +static int write_reg_dma(struct qcom_nand_controller *nandc, __le32 *vaddr, + int first, int num_regs, unsigned int flags) { bool flow_control =3D false; - struct nandc_regs *regs =3D nandc->regs; - void *vaddr; - - vaddr =3D offset_to_nandc_reg(regs, first); - - if (first =3D=3D NAND_ERASED_CW_DETECT_CFG) { - if (flags & NAND_ERASED_CW_SET) - vaddr =3D ®s->erased_cw_detect_cfg_set; - else - vaddr =3D ®s->erased_cw_detect_cfg_clr; - } =20 if (first =3D=3D NAND_EXEC_CMD) flags |=3D NAND_BAM_NWD; @@ -1165,7 +1123,7 @@ static int write_reg_dma(struct qcom_nand_controller = *nandc, int first, if (first =3D=3D NAND_DEV_CMD_VLD_RESTORE || first =3D=3D NAND_DEV_CMD_VL= D) first =3D dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD); =20 - if (nandc->props->is_bam) + if (nandc->props->supports_bam) return prep_bam_dma_desc_cmd(nandc, false, first, vaddr, num_regs, flags); =20 @@ -1188,7 +1146,7 @@ static int write_reg_dma(struct qcom_nand_controller = *nandc, int first, static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off, const u8 *vaddr, int size, unsigned int flags) { - if (nandc->props->is_bam) + if (nandc->props->supports_bam) return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags); =20 return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false); @@ -1206,7 +1164,7 @@ static int read_data_dma(struct qcom_nand_controller = *nandc, int reg_off, static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off, const u8 *vaddr, int size, unsigned int flags) { - if (nandc->props->is_bam) + if (nandc->props->supports_bam) return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags); =20 return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false); @@ -1220,13 +1178,14 @@ static void config_nand_page_read(struct nand_chip = *chip) { struct qcom_nand_controller *nandc =3D get_qcom_nand_controller(chip); =20 - write_reg_dma(nandc, NAND_ADDR0, 2, 0); - write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0); - if (!nandc->props->qpic_v2) - write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0); - write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0); - write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, - NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL); + write_reg_dma(nandc, &nandc->regs->addr0, NAND_ADDR0, 2, 0); + write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); + if (!nandc->props->qpic_version2) + write_reg_dma(nandc, &nandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1= , 0); + write_reg_dma(nandc, &nandc->regs->erased_cw_detect_cfg_clr, + NAND_ERASED_CW_DETECT_CFG, 1, 0); + write_reg_dma(nandc, &nandc->regs->erased_cw_detect_cfg_set, + NAND_ERASED_CW_DETECT_CFG, 1, NAND_ERASED_CW_SET | NAND_BAM_NEXT_S= GL); } =20 /* @@ -1239,16 +1198,16 @@ config_nand_cw_read(struct nand_chip *chip, bool us= e_ecc, int cw) struct qcom_nand_controller *nandc =3D get_qcom_nand_controller(chip); struct nand_ecc_ctrl *ecc =3D &chip->ecc; =20 - int reg =3D NAND_READ_LOCATION_0; + __le32 *reg =3D &nandc->regs->read_location0; =20 - if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw)) - reg =3D NAND_READ_LOCATION_LAST_CW_0; + if (nandc->props->qpic_version2 && qcom_nandc_is_last_cw(ecc, cw)) + reg =3D &nandc->regs->read_location_last0; =20 - if (nandc->props->is_bam) - write_reg_dma(nandc, reg, 4, NAND_BAM_NEXT_SGL); + if (nandc->props->supports_bam) + write_reg_dma(nandc, reg, NAND_READ_LOCATION_0, 4, NAND_BAM_NEXT_SGL); =20 - write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); - write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); + write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_= SGL); + write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_= SGL); =20 if (use_ecc) { read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0); @@ -1279,10 +1238,10 @@ static void config_nand_page_write(struct nand_chip= *chip) { struct qcom_nand_controller *nandc =3D get_qcom_nand_controller(chip); =20 - write_reg_dma(nandc, NAND_ADDR0, 2, 0); - write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0); - if (!nandc->props->qpic_v2) - write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, + write_reg_dma(nandc, &nandc->regs->addr0, NAND_ADDR0, 2, 0); + write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); + if (!nandc->props->qpic_version2) + write_reg_dma(nandc, &nandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1, NAND_BAM_NEXT_SGL); } =20 @@ -1294,13 +1253,13 @@ static void config_nand_cw_write(struct nand_chip *= chip) { struct qcom_nand_controller *nandc =3D get_qcom_nand_controller(chip); =20 - write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); - write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); + write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_= SGL); + write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_= SGL); =20 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); =20 - write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0); - write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL); + write_reg_dma(nandc, &nandc->regs->clrflashstatus, NAND_FLASH_STATUS, 1, = 0); + write_reg_dma(nandc, &nandc->regs->clrreadstatus, NAND_READ_STATUS, 1, NA= ND_BAM_NEXT_SGL); } =20 /* helpers to submit/free our list of dma descriptors */ @@ -1311,7 +1270,7 @@ static int submit_descs(struct qcom_nand_controller *= nandc) struct bam_transaction *bam_txn =3D nandc->bam_txn; int ret =3D 0; =20 - if (nandc->props->is_bam) { + if (nandc->props->supports_bam) { if (bam_txn->rx_sgl_pos > bam_txn->rx_sgl_start) { ret =3D prepare_bam_async_desc(nandc, nandc->rx_chan, 0); if (ret) @@ -1336,14 +1295,9 @@ static int submit_descs(struct qcom_nand_controller = *nandc) list_for_each_entry(desc, &nandc->desc_list, node) cookie =3D dmaengine_submit(desc->dma_desc); =20 - if (nandc->props->is_bam) { + if (nandc->props->supports_bam) { bam_txn->last_cmd_desc->callback =3D qpic_bam_dma_done; bam_txn->last_cmd_desc->callback_param =3D bam_txn; - if (bam_txn->last_data_desc) { - bam_txn->last_data_desc->callback =3D qpic_bam_dma_done; - bam_txn->last_data_desc->callback_param =3D bam_txn; - bam_txn->wait_second_completion =3D true; - } =20 dma_async_issue_pending(nandc->tx_chan); dma_async_issue_pending(nandc->rx_chan); @@ -1365,7 +1319,7 @@ static int submit_descs(struct qcom_nand_controller *= nandc) list_for_each_entry_safe(desc, n, &nandc->desc_list, node) { list_del(&desc->node); =20 - if (nandc->props->is_bam) + if (nandc->props->supports_bam) dma_unmap_sg(nandc->dev, desc->bam_sgl, desc->sgl_cnt, desc->dir); else @@ -1382,7 +1336,7 @@ static int submit_descs(struct qcom_nand_controller *= nandc) static void clear_read_regs(struct qcom_nand_controller *nandc) { nandc->reg_read_pos =3D 0; - nandc_read_buffer_sync(nandc, false); + nandc_dev_to_mem(nandc, false); } =20 /* @@ -1446,7 +1400,7 @@ static int check_flash_errors(struct qcom_nand_host *= host, int cw_cnt) struct qcom_nand_controller *nandc =3D get_qcom_nand_controller(chip); int i; =20 - nandc_read_buffer_sync(nandc, true); + nandc_dev_to_mem(nandc, true); =20 for (i =3D 0; i < cw_cnt; i++) { u32 flash =3D le32_to_cpu(nandc->reg_read_buf[i]); @@ -1476,7 +1430,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct n= and_chip *chip, clear_read_regs(nandc); host->use_ecc =3D false; =20 - if (nandc->props->qpic_v2) + if (nandc->props->qpic_version2) raw_cw =3D ecc->steps - 1; =20 clear_bam_transaction(nandc); @@ -1497,7 +1451,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct n= and_chip *chip, oob_size2 =3D host->ecc_bytes_hw + host->spare_bytes; } =20 - if (nandc->props->is_bam) { + if (nandc->props->supports_bam) { nandc_set_read_loc(chip, cw, 0, read_loc, data_size1, 0); read_loc +=3D data_size1; =20 @@ -1621,7 +1575,7 @@ static int parse_read_errors(struct qcom_nand_host *h= ost, u8 *data_buf, u8 *data_buf_start =3D data_buf, *oob_buf_start =3D oob_buf; =20 buf =3D (struct read_stats *)nandc->reg_read_buf; - nandc_read_buffer_sync(nandc, true); + nandc_dev_to_mem(nandc, true); =20 for (i =3D 0; i < ecc->steps; i++, buf++) { u32 flash, buffer, erased_cw; @@ -1734,7 +1688,7 @@ static int read_page_ecc(struct qcom_nand_host *host,= u8 *data_buf, oob_size =3D host->ecc_bytes_hw + host->spare_bytes; } =20 - if (nandc->props->is_bam) { + if (nandc->props->supports_bam) { if (data_buf && oob_buf) { nandc_set_read_loc(chip, i, 0, 0, data_size, 0); nandc_set_read_loc(chip, i, 1, data_size, @@ -2455,14 +2409,14 @@ static int qcom_nand_attach_chip(struct nand_chip *= chip) =20 mtd_set_ooblayout(mtd, &qcom_nand_ooblayout_ops); /* Free the initially allocated BAM transaction for reading the ONFI para= ms */ - if (nandc->props->is_bam) + if (nandc->props->supports_bam) free_bam_transaction(nandc); =20 nandc->max_cwperpage =3D max_t(unsigned int, nandc->max_cwperpage, cwperpage); =20 /* Now allocate the BAM transaction based on updated max_cwperpage */ - if (nandc->props->is_bam) { + if (nandc->props->supports_bam) { nandc->bam_txn =3D alloc_bam_transaction(nandc); if (!nandc->bam_txn) { dev_err(nandc->dev, @@ -2522,7 +2476,7 @@ static int qcom_nand_attach_chip(struct nand_chip *ch= ip) | ecc_mode << ECC_MODE | host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH; =20 - if (!nandc->props->qpic_v2) + if (!nandc->props->qpic_version2) host->ecc_buf_cfg =3D 0x203 << NUM_STEPS; =20 host->clrflashstatus =3D FS_READY_BSY_N; @@ -2556,7 +2510,7 @@ static int qcom_op_cmd_mapping(struct nand_chip *chip= , u8 opcode, cmd =3D OP_FETCH_ID; break; case NAND_CMD_PARAM: - if (nandc->props->qpic_v2) + if (nandc->props->qpic_version2) cmd =3D OP_PAGE_READ_ONFI_READ; else cmd =3D OP_PAGE_READ; @@ -2609,7 +2563,7 @@ static int qcom_parse_instructions(struct nand_chip *= chip, if (ret < 0) return ret; =20 - q_op->cmd_reg =3D ret; + q_op->cmd_reg =3D cpu_to_le32(ret); q_op->rdy_delay_ns =3D instr->delay_ns; break; =20 @@ -2619,10 +2573,10 @@ static int qcom_parse_instructions(struct nand_chip= *chip, addrs =3D &instr->ctx.addr.addrs[offset]; =20 for (i =3D 0; i < min_t(unsigned int, 4, naddrs); i++) - q_op->addr1_reg |=3D addrs[i] << (i * 8); + q_op->addr1_reg |=3D cpu_to_le32(addrs[i] << (i * 8)); =20 if (naddrs > 4) - q_op->addr2_reg |=3D addrs[4]; + q_op->addr2_reg |=3D cpu_to_le32(addrs[4]); =20 q_op->rdy_delay_ns =3D instr->delay_ns; break; @@ -2663,7 +2617,7 @@ static int qcom_wait_rdy_poll(struct nand_chip *chip,= unsigned int time_ms) unsigned long start =3D jiffies + msecs_to_jiffies(time_ms); u32 flash; =20 - nandc_read_buffer_sync(nandc, true); + nandc_dev_to_mem(nandc, true); =20 do { flash =3D le32_to_cpu(nandc->reg_read_buf[0]); @@ -2706,11 +2660,11 @@ static int qcom_read_status_exec(struct nand_chip *= chip, clear_read_regs(nandc); clear_bam_transaction(nandc); =20 - nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg); - nandc_set_reg(chip, NAND_EXEC_CMD, 1); + nandc->regs->cmd =3D q_op.cmd_reg; + nandc->regs->exec =3D cpu_to_le32(1); =20 - write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); - write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); + write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_= SGL); + write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_= SGL); read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); =20 ret =3D submit_descs(nandc); @@ -2719,7 +2673,7 @@ static int qcom_read_status_exec(struct nand_chip *ch= ip, goto err_out; } =20 - nandc_read_buffer_sync(nandc, true); + nandc_dev_to_mem(nandc, true); =20 for (i =3D 0; i < num_cw; i++) { flash_status =3D le32_to_cpu(nandc->reg_read_buf[i]); @@ -2763,16 +2717,14 @@ static int qcom_read_id_type_exec(struct nand_chip = *chip, const struct nand_subo clear_read_regs(nandc); clear_bam_transaction(nandc); =20 - nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg); - nandc_set_reg(chip, NAND_ADDR0, q_op.addr1_reg); - nandc_set_reg(chip, NAND_ADDR1, q_op.addr2_reg); - nandc_set_reg(chip, NAND_FLASH_CHIP_SELECT, - nandc->props->is_bam ? 0 : DM_EN); - - nandc_set_reg(chip, NAND_EXEC_CMD, 1); + nandc->regs->cmd =3D q_op.cmd_reg; + nandc->regs->addr0 =3D q_op.addr1_reg; + nandc->regs->addr1 =3D q_op.addr2_reg; + nandc->regs->chip_sel =3D cpu_to_le32(nandc->props->supports_bam ? 0 : DM= _EN); + nandc->regs->exec =3D cpu_to_le32(1); =20 - write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL); - write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); + write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_= SGL); + write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_= SGL); =20 read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL); =20 @@ -2786,7 +2738,7 @@ static int qcom_read_id_type_exec(struct nand_chip *c= hip, const struct nand_subo op_id =3D q_op.data_instr_idx; len =3D nand_subop_get_data_len(subop, op_id); =20 - nandc_read_buffer_sync(nandc, true); + nandc_dev_to_mem(nandc, true); memcpy(instr->ctx.data.buf.in, nandc->reg_read_buf, len); =20 err_out: @@ -2807,15 +2759,14 @@ static int qcom_misc_cmd_type_exec(struct nand_chip= *chip, const struct nand_sub =20 if (q_op.flag =3D=3D OP_PROGRAM_PAGE) { goto wait_rdy; - } else if (q_op.cmd_reg =3D=3D OP_BLOCK_ERASE) { - q_op.cmd_reg |=3D PAGE_ACC | LAST_PAGE; - nandc_set_reg(chip, NAND_ADDR0, q_op.addr1_reg); - nandc_set_reg(chip, NAND_ADDR1, q_op.addr2_reg); - nandc_set_reg(chip, NAND_DEV0_CFG0, - host->cfg0_raw & ~(7 << CW_PER_PAGE)); - nandc_set_reg(chip, NAND_DEV0_CFG1, host->cfg1_raw); + } else if (q_op.cmd_reg =3D=3D cpu_to_le32(OP_BLOCK_ERASE)) { + q_op.cmd_reg |=3D cpu_to_le32(PAGE_ACC | LAST_PAGE); + nandc->regs->addr0 =3D q_op.addr1_reg; + nandc->regs->addr1 =3D q_op.addr2_reg; + nandc->regs->cfg0 =3D cpu_to_le32(host->cfg0_raw & ~(7 << CW_PER_PAGE)); + nandc->regs->cfg1 =3D cpu_to_le32(host->cfg1_raw); instrs =3D 3; - } else if (q_op.cmd_reg !=3D OP_RESET_DEVICE) { + } else if (q_op.cmd_reg !=3D cpu_to_le32(OP_RESET_DEVICE)) { return 0; } =20 @@ -2826,14 +2777,14 @@ static int qcom_misc_cmd_type_exec(struct nand_chip= *chip, const struct nand_sub clear_read_regs(nandc); clear_bam_transaction(nandc); =20 - nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg); - nandc_set_reg(chip, NAND_EXEC_CMD, 1); + nandc->regs->cmd =3D q_op.cmd_reg; + nandc->regs->exec =3D cpu_to_le32(1); =20 - write_reg_dma(nandc, NAND_FLASH_CMD, instrs, NAND_BAM_NEXT_SGL); - if (q_op.cmd_reg =3D=3D OP_BLOCK_ERASE) - write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL); + write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, instrs, NAND_BAM_= NEXT_SGL); + if (q_op.cmd_reg =3D=3D cpu_to_le32(OP_BLOCK_ERASE)) + write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 2, NAND_BAM_NEX= T_SGL); =20 - write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); + write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_= SGL); read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); =20 ret =3D submit_descs(nandc); @@ -2864,7 +2815,7 @@ static int qcom_param_page_type_exec(struct nand_chip= *chip, const struct nand_ if (ret) return ret; =20 - q_op.cmd_reg |=3D PAGE_ACC | LAST_PAGE; + q_op.cmd_reg |=3D cpu_to_le32(PAGE_ACC | LAST_PAGE); =20 nandc->buf_count =3D 0; nandc->buf_start =3D 0; @@ -2872,38 +2823,38 @@ static int qcom_param_page_type_exec(struct nand_ch= ip *chip, const struct nand_ clear_read_regs(nandc); clear_bam_transaction(nandc); =20 - nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg); - - nandc_set_reg(chip, NAND_ADDR0, 0); - nandc_set_reg(chip, NAND_ADDR1, 0); - nandc_set_reg(chip, NAND_DEV0_CFG0, 0 << CW_PER_PAGE - | 512 << UD_SIZE_BYTES - | 5 << NUM_ADDR_CYCLES - | 0 << SPARE_SIZE_BYTES); - nandc_set_reg(chip, NAND_DEV0_CFG1, 7 << NAND_RECOVERY_CYCLES - | 0 << CS_ACTIVE_BSY - | 17 << BAD_BLOCK_BYTE_NUM - | 1 << BAD_BLOCK_IN_SPARE_AREA - | 2 << WR_RD_BSY_GAP - | 0 << WIDE_FLASH - | 1 << DEV0_CFG1_ECC_DISABLE); - if (!nandc->props->qpic_v2) - nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE); + nandc->regs->cmd =3D q_op.cmd_reg; + nandc->regs->addr0 =3D 0; + nandc->regs->addr1 =3D 0; + + nandc->regs->cfg0 =3D cpu_to_le32(0 << CW_PER_PAGE + | 512 << UD_SIZE_BYTES + | 5 << NUM_ADDR_CYCLES + | 0 << SPARE_SIZE_BYTES); + + nandc->regs->cfg1 =3D cpu_to_le32(7 << NAND_RECOVERY_CYCLES + | 0 << CS_ACTIVE_BSY + | 17 << BAD_BLOCK_BYTE_NUM + | 1 << BAD_BLOCK_IN_SPARE_AREA + | 2 << WR_RD_BSY_GAP + | 0 << WIDE_FLASH + | 1 << DEV0_CFG1_ECC_DISABLE); + + if (!nandc->props->qpic_version2) + nandc->regs->ecc_buf_cfg =3D cpu_to_le32(1 << ECC_CFG_ECC_DISABLE); =20 /* configure CMD1 and VLD for ONFI param probing in QPIC v1 */ - if (!nandc->props->qpic_v2) { - nandc_set_reg(chip, NAND_DEV_CMD_VLD, - (nandc->vld & ~READ_START_VLD)); - nandc_set_reg(chip, NAND_DEV_CMD1, - (nandc->cmd1 & ~(0xFF << READ_ADDR)) - | NAND_CMD_PARAM << READ_ADDR); + if (!nandc->props->qpic_version2) { + nandc->regs->vld =3D cpu_to_le32((nandc->vld & ~READ_START_VLD)); + nandc->regs->cmd1 =3D cpu_to_le32((nandc->cmd1 & ~(0xFF << READ_ADDR)) + | NAND_CMD_PARAM << READ_ADDR); } =20 - nandc_set_reg(chip, NAND_EXEC_CMD, 1); + nandc->regs->exec =3D cpu_to_le32(1); =20 - if (!nandc->props->qpic_v2) { - nandc_set_reg(chip, NAND_DEV_CMD1_RESTORE, nandc->cmd1); - nandc_set_reg(chip, NAND_DEV_CMD_VLD_RESTORE, nandc->vld); + if (!nandc->props->qpic_version2) { + nandc->regs->orig_cmd1 =3D cpu_to_le32(nandc->cmd1); + nandc->regs->orig_vld =3D cpu_to_le32(nandc->vld); } =20 instr =3D q_op.data_instr; @@ -2912,9 +2863,9 @@ static int qcom_param_page_type_exec(struct nand_chip= *chip, const struct nand_ =20 nandc_set_read_loc(chip, 0, 0, 0, len, 1); =20 - if (!nandc->props->qpic_v2) { - write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0); - write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL); + if (!nandc->props->qpic_version2) { + write_reg_dma(nandc, &nandc->regs->vld, NAND_DEV_CMD_VLD, 1, 0); + write_reg_dma(nandc, &nandc->regs->cmd1, NAND_DEV_CMD1, 1, NAND_BAM_NEXT= _SGL); } =20 nandc->buf_count =3D len; @@ -2926,9 +2877,10 @@ static int qcom_param_page_type_exec(struct nand_chi= p *chip, const struct nand_ nandc->buf_count, 0); =20 /* restore CMD1 and VLD regs */ - if (!nandc->props->qpic_v2) { - write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0); - write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1, NAND_BAM_NEXT_SGL); + if (!nandc->props->qpic_version2) { + write_reg_dma(nandc, &nandc->regs->orig_cmd1, NAND_DEV_CMD1_RESTORE, 1, = 0); + write_reg_dma(nandc, &nandc->regs->orig_vld, NAND_DEV_CMD_VLD_RESTORE, 1, + NAND_BAM_NEXT_SGL); } =20 ret =3D submit_descs(nandc); @@ -3017,7 +2969,7 @@ static const struct nand_controller_ops qcom_nandc_op= s =3D { =20 static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc) { - if (nandc->props->is_bam) { + if (nandc->props->supports_bam) { if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma)) dma_unmap_single(nandc->dev, nandc->reg_read_dma, MAX_REG_RD * @@ -3070,7 +3022,7 @@ static int qcom_nandc_alloc(struct qcom_nand_controll= er *nandc) if (!nandc->reg_read_buf) return -ENOMEM; =20 - if (nandc->props->is_bam) { + if (nandc->props->supports_bam) { nandc->reg_read_dma =3D dma_map_single(nandc->dev, nandc->reg_read_buf, MAX_REG_RD * @@ -3151,15 +3103,15 @@ static int qcom_nandc_setup(struct qcom_nand_contro= ller *nandc) u32 nand_ctrl; =20 /* kill onenand */ - if (!nandc->props->is_qpic) + if (!nandc->props->nandc_part_of_qpic) nandc_write(nandc, SFLASHC_BURST_CFG, 0); =20 - if (!nandc->props->qpic_v2) + if (!nandc->props->qpic_version2) nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD), NAND_DEV_CMD_VLD_VAL); =20 /* enable ADM or BAM DMA */ - if (nandc->props->is_bam) { + if (nandc->props->supports_bam) { nand_ctrl =3D nandc_read(nandc, NAND_CTRL); =20 /* @@ -3176,7 +3128,7 @@ static int qcom_nandc_setup(struct qcom_nand_controll= er *nandc) } =20 /* save the original values of these registers */ - if (!nandc->props->qpic_v2) { + if (!nandc->props->qpic_version2) { nandc->cmd1 =3D nandc_read(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD1)= ); nandc->vld =3D NAND_DEV_CMD_VLD_VAL; } @@ -3349,7 +3301,7 @@ static int qcom_nandc_parse_dt(struct platform_device= *pdev) struct device_node *np =3D nandc->dev->of_node; int ret; =20 - if (!nandc->props->is_bam) { + if (!nandc->props->supports_bam) { ret =3D of_property_read_u32(np, "qcom,cmd-crci", &nandc->cmd_crci); if (ret) { @@ -3474,30 +3426,30 @@ static void qcom_nandc_remove(struct platform_devic= e *pdev) =20 static const struct qcom_nandc_props ipq806x_nandc_props =3D { .ecc_modes =3D (ECC_RS_4BIT | ECC_BCH_8BIT), - .is_bam =3D false, + .supports_bam =3D false, .use_codeword_fixup =3D true, .dev_cmd_reg_start =3D 0x0, }; =20 static const struct qcom_nandc_props ipq4019_nandc_props =3D { .ecc_modes =3D (ECC_BCH_4BIT | ECC_BCH_8BIT), - .is_bam =3D true, - .is_qpic =3D true, + .supports_bam =3D true, + .nandc_part_of_qpic =3D true, .dev_cmd_reg_start =3D 0x0, }; =20 static const struct qcom_nandc_props ipq8074_nandc_props =3D { .ecc_modes =3D (ECC_BCH_4BIT | ECC_BCH_8BIT), - .is_bam =3D true, - .is_qpic =3D true, + .supports_bam =3D true, + .nandc_part_of_qpic =3D true, .dev_cmd_reg_start =3D 0x7000, }; =20 static const struct qcom_nandc_props sdx55_nandc_props =3D { .ecc_modes =3D (ECC_BCH_4BIT | ECC_BCH_8BIT), - .is_bam =3D true, - .is_qpic =3D true, - .qpic_v2 =3D true, + .supports_bam =3D true, + .nandc_part_of_qpic =3D true, + .qpic_version2 =3D true, .dev_cmd_reg_start =3D 0x7000, }; =20 --=20 2.34.1 From nobody Sat Nov 30 03:41:48 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F8D7189BB9; Thu, 12 Sep 2024 06:16:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726121776; cv=none; b=FbXuSq4ZhVUVtElcYVU90D/RnW9gapM7pnvqWOdjBjMLzaet5rbseiECSgPdWJALMfOOswuGjeHDpuHVIGz4cNObIj6RkY/26gRiu2BY3YZ4/Rpx9wvZPOBgPkSJlReZCZ1gM2BpD+3WD7zXSuxQXO3KA6XbiievSfAJQlyY73c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726121776; c=relaxed/simple; bh=GqHOqlAEtB9XtwAkMF16+yZpJ5iTVUSPAdk6VRDKHDY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Atzi99BNMtZA63/glNoRpPe1Bfqir9XR9bFYDTwpwzzxUvnyiofOpPeP3EI+zmJIQbO1Xq7q1uRlaiXBYW9uFzL5KGABBJUHuLorw2FqQ4eGZZoPnVwXs7GbciCyVtckz5aFI0Mg8ybj9dlB+wF9vs95pdSqBkls74YNLuoxR8Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=VOnmFgQJ; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="VOnmFgQJ" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48C2LLgg026795; Thu, 12 Sep 2024 06:15:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= eVdiBxOVd8s4CEvFUtkJ0jUNI372DjeteCfigOlDFp0=; b=VOnmFgQJ9eBGSI6y /PjDr6kIuZ+mJ3PHoCCEGM1LmJgqMudJJeTKIS3AlDawW6K3OCDfDTaE/nuzCBOz Hdrrg90oyNwlKejpvVyU4etsu18Mw6EoF7LduMhnT2FxiZa3BA5esapVEuoMHvce tZeKKTeNbIxzH9Bmw4DjfqPqKc4LOFkrunJXmtSn7Rjy0hq84DpzAOh3+qZmHcMR Xz0IaNDX8J+s8eHw24dsZa9X3M29Gg81ESC+40zk70ckqcnox8SNU41H8mbNh8xz SrbCkhrTtAvSpW3d0jUCDz/wfkfgkgV0c5kSU5Zk/ax5Mn+KDgSYB4h7vVOPsouu jOzsrg== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41gy6ec0u7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Sep 2024 06:15:42 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48C6FfZi003896 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Sep 2024 06:15:41 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Sep 2024 23:15:35 -0700 From: Md Sadre Alam To: , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v9 3/8] mtd: rawnand: qcom: Add qcom prefix to common api Date: Thu, 12 Sep 2024 11:44:58 +0530 Message-ID: <20240912061503.3468147-4-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240912061503.3468147-1-quic_mdalam@quicinc.com> References: <20240912061503.3468147-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: CXyaDNTeITqDZFXGqQ1STzRxbSk0VpHI X-Proofpoint-ORIG-GUID: CXyaDNTeITqDZFXGqQ1STzRxbSk0VpHI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 suspectscore=0 bulkscore=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 impostorscore=0 mlxlogscore=999 spamscore=0 adultscore=0 priorityscore=1501 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409120043 Content-Type: text/plain; charset="utf-8" Add qcom prefix to all the api which will be commonly used by spi nand driver and raw nand driver. Signed-off-by: Md Sadre Alam --- Change in [v9] * No change Change in [v8] * No change Change in [v7] * No change Change in [v6] * No change Change in [v5] * Add qcom_ prefix to all common API. Change in [v4] * This patch was not included in [v4] Change in [v3] * This patch was not included in [v3] Change in [v2] * This patch was not included in [v2] Change in [v1] * This patch was not included in [v1] drivers/mtd/nand/raw/qcom_nandc.c | 320 +++++++++++++++--------------- 1 file changed, 160 insertions(+), 160 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_= nandc.c index d134329330fe..daf8f73b25bc 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -53,7 +53,7 @@ #define NAND_READ_LOCATION_LAST_CW_2 0xf48 #define NAND_READ_LOCATION_LAST_CW_3 0xf4c =20 -/* dummy register offsets, used by write_reg_dma */ +/* dummy register offsets, used by qcom_write_reg_dma */ #define NAND_DEV_CMD1_RESTORE 0xdead #define NAND_DEV_CMD_VLD_RESTORE 0xbeef =20 @@ -211,7 +211,7 @@ =20 /* * Flags used in DMA descriptor preparation helper functions - * (i.e. read_reg_dma/write_reg_dma/read_data_dma/write_data_dma) + * (i.e. qcom_read_reg_dma/qcom_write_reg_dma/qcom_read_data_dma/qcom_writ= e_data_dma) */ /* Don't set the EOT in current tx BAM sgl */ #define NAND_BAM_NO_EOT BIT(0) @@ -550,7 +550,7 @@ struct qcom_nandc_props { }; =20 /* Frees the BAM transaction memory */ -static void free_bam_transaction(struct qcom_nand_controller *nandc) +static void qcom_free_bam_transaction(struct qcom_nand_controller *nandc) { struct bam_transaction *bam_txn =3D nandc->bam_txn; =20 @@ -559,7 +559,7 @@ static void free_bam_transaction(struct qcom_nand_contr= oller *nandc) =20 /* Allocates and Initializes the BAM transaction */ static struct bam_transaction * -alloc_bam_transaction(struct qcom_nand_controller *nandc) +qcom_alloc_bam_transaction(struct qcom_nand_controller *nandc) { struct bam_transaction *bam_txn; size_t bam_txn_size; @@ -595,7 +595,7 @@ alloc_bam_transaction(struct qcom_nand_controller *nand= c) } =20 /* Clears the BAM transaction indexes */ -static void clear_bam_transaction(struct qcom_nand_controller *nandc) +static void qcom_clear_bam_transaction(struct qcom_nand_controller *nandc) { struct bam_transaction *bam_txn =3D nandc->bam_txn; =20 @@ -614,7 +614,7 @@ static void clear_bam_transaction(struct qcom_nand_cont= roller *nandc) } =20 /* Callback for DMA descriptor completion */ -static void qpic_bam_dma_done(void *data) +static void qcom_qpic_bam_dma_done(void *data) { struct bam_transaction *bam_txn =3D data; =20 @@ -644,7 +644,7 @@ static inline void nandc_write(struct qcom_nand_control= ler *nandc, int offset, iowrite32(val, nandc->base + offset); } =20 -static inline void nandc_dev_to_mem(struct qcom_nand_controller *nandc, bo= ol is_cpu) +static inline void qcom_nandc_dev_to_mem(struct qcom_nand_controller *nand= c, bool is_cpu) { if (!nandc->props->supports_bam) return; @@ -824,9 +824,9 @@ static void update_rw_regs(struct qcom_nand_host *host,= int num_cw, bool read, i * for BAM. This descriptor will be added in the NAND DMA descriptor queue * which will be submitted to DMA engine. */ -static int prepare_bam_async_desc(struct qcom_nand_controller *nandc, - struct dma_chan *chan, - unsigned long flags) +static int qcom_prepare_bam_async_desc(struct qcom_nand_controller *nandc, + struct dma_chan *chan, + unsigned long flags) { struct desc_info *desc; struct scatterlist *sgl; @@ -903,9 +903,9 @@ static int prepare_bam_async_desc(struct qcom_nand_cont= roller *nandc, * NAND_BAM_NEXT_SGL will be used for starting the separate SGL * after the current command element. */ -static int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool = read, - int reg_off, const void *vaddr, - int size, unsigned int flags) +static int qcom_prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, = bool read, + int reg_off, const void *vaddr, + int size, unsigned int flags) { int bam_ce_size; int i, ret; @@ -943,9 +943,9 @@ static int prep_bam_dma_desc_cmd(struct qcom_nand_contr= oller *nandc, bool read, bam_txn->bam_ce_start =3D bam_txn->bam_ce_pos; =20 if (flags & NAND_BAM_NWD) { - ret =3D prepare_bam_async_desc(nandc, nandc->cmd_chan, - DMA_PREP_FENCE | - DMA_PREP_CMD); + ret =3D qcom_prepare_bam_async_desc(nandc, nandc->cmd_chan, + DMA_PREP_FENCE | + DMA_PREP_CMD); if (ret) return ret; } @@ -958,9 +958,8 @@ static int prep_bam_dma_desc_cmd(struct qcom_nand_contr= oller *nandc, bool read, * Prepares the data descriptor for BAM DMA which will be used for NAND * data reads and writes. */ -static int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool= read, - const void *vaddr, - int size, unsigned int flags) +static int qcom_prep_bam_dma_desc_data(struct qcom_nand_controller *nandc,= bool read, + const void *vaddr, int size, unsigned int flags) { int ret; struct bam_transaction *bam_txn =3D nandc->bam_txn; @@ -979,8 +978,8 @@ static int prep_bam_dma_desc_data(struct qcom_nand_cont= roller *nandc, bool read, * is not set, form the DMA descriptor */ if (!(flags & NAND_BAM_NO_EOT)) { - ret =3D prepare_bam_async_desc(nandc, nandc->tx_chan, - DMA_PREP_INTERRUPT); + ret =3D qcom_prepare_bam_async_desc(nandc, nandc->tx_chan, + DMA_PREP_INTERRUPT); if (ret) return ret; } @@ -989,9 +988,9 @@ static int prep_bam_dma_desc_data(struct qcom_nand_cont= roller *nandc, bool read, return 0; } =20 -static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read, - int reg_off, const void *vaddr, int size, - bool flow_control) +static int qcom_prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool= read, + int reg_off, const void *vaddr, int size, + bool flow_control) { struct desc_info *desc; struct dma_async_tx_descriptor *dma_desc; @@ -1069,15 +1068,15 @@ static int prep_adm_dma_desc(struct qcom_nand_contr= oller *nandc, bool read, } =20 /* - * read_reg_dma: prepares a descriptor to read a given number of + * qcom_read_reg_dma: prepares a descriptor to read a given number of * contiguous registers to the reg_read_buf pointer * * @first: offset of the first register in the contiguous block * @num_regs: number of registers to read * @flags: flags to control DMA descriptor preparation */ -static int read_reg_dma(struct qcom_nand_controller *nandc, int first, - int num_regs, unsigned int flags) +static int qcom_read_reg_dma(struct qcom_nand_controller *nandc, int first, + int num_regs, unsigned int flags) { bool flow_control =3D false; void *vaddr; @@ -1089,18 +1088,18 @@ static int read_reg_dma(struct qcom_nand_controller= *nandc, int first, first =3D dev_cmd_reg_addr(nandc, first); =20 if (nandc->props->supports_bam) - return prep_bam_dma_desc_cmd(nandc, true, first, vaddr, + return qcom_prep_bam_dma_desc_cmd(nandc, true, first, vaddr, num_regs, flags); =20 if (first =3D=3D NAND_READ_ID || first =3D=3D NAND_FLASH_STATUS) flow_control =3D true; =20 - return prep_adm_dma_desc(nandc, true, first, vaddr, + return qcom_prep_adm_dma_desc(nandc, true, first, vaddr, num_regs * sizeof(u32), flow_control); } =20 /* - * write_reg_dma: prepares a descriptor to write a given number of + * qcom_write_reg_dma: prepares a descriptor to write a given number of * contiguous registers * * @vaddr: contnigeous memory from where register value will @@ -1109,8 +1108,8 @@ static int read_reg_dma(struct qcom_nand_controller *= nandc, int first, * @num_regs: number of registers to write * @flags: flags to control DMA descriptor preparation */ -static int write_reg_dma(struct qcom_nand_controller *nandc, __le32 *vaddr, - int first, int num_regs, unsigned int flags) +static int qcom_write_reg_dma(struct qcom_nand_controller *nandc, __le32 *= vaddr, + int first, int num_regs, unsigned int flags) { bool flow_control =3D false; =20 @@ -1124,18 +1123,18 @@ static int write_reg_dma(struct qcom_nand_controlle= r *nandc, __le32 *vaddr, first =3D dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD); =20 if (nandc->props->supports_bam) - return prep_bam_dma_desc_cmd(nandc, false, first, vaddr, + return qcom_prep_bam_dma_desc_cmd(nandc, false, first, vaddr, num_regs, flags); =20 if (first =3D=3D NAND_FLASH_CMD) flow_control =3D true; =20 - return prep_adm_dma_desc(nandc, false, first, vaddr, + return qcom_prep_adm_dma_desc(nandc, false, first, vaddr, num_regs * sizeof(u32), flow_control); } =20 /* - * read_data_dma: prepares a DMA descriptor to transfer data from the + * qcom_read_data_dma: prepares a DMA descriptor to transfer data from the * controller's internal buffer to the buffer 'vaddr' * * @reg_off: offset within the controller's data buffer @@ -1143,17 +1142,17 @@ static int write_reg_dma(struct qcom_nand_controlle= r *nandc, __le32 *vaddr, * @size: DMA transaction size in bytes * @flags: flags to control DMA descriptor preparation */ -static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off, - const u8 *vaddr, int size, unsigned int flags) +static int qcom_read_data_dma(struct qcom_nand_controller *nandc, int reg_= off, + const u8 *vaddr, int size, unsigned int flags) { if (nandc->props->supports_bam) - return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags); + return qcom_prep_bam_dma_desc_data(nandc, true, vaddr, size, flags); =20 - return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false); + return qcom_prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false); } =20 /* - * write_data_dma: prepares a DMA descriptor to transfer data from + * qcom_write_data_dma: prepares a DMA descriptor to transfer data from * 'vaddr' to the controller's internal buffer * * @reg_off: offset within the controller's data buffer @@ -1161,13 +1160,13 @@ static int read_data_dma(struct qcom_nand_controlle= r *nandc, int reg_off, * @size: DMA transaction size in bytes * @flags: flags to control DMA descriptor preparation */ -static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off, - const u8 *vaddr, int size, unsigned int flags) +static int qcom_write_data_dma(struct qcom_nand_controller *nandc, int reg= _off, + const u8 *vaddr, int size, unsigned int flags) { if (nandc->props->supports_bam) - return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags); + return qcom_prep_bam_dma_desc_data(nandc, false, vaddr, size, flags); =20 - return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false); + return qcom_prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false); } =20 /* @@ -1178,14 +1177,14 @@ static void config_nand_page_read(struct nand_chip = *chip) { struct qcom_nand_controller *nandc =3D get_qcom_nand_controller(chip); =20 - write_reg_dma(nandc, &nandc->regs->addr0, NAND_ADDR0, 2, 0); - write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); + qcom_write_reg_dma(nandc, &nandc->regs->addr0, NAND_ADDR0, 2, 0); + qcom_write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); if (!nandc->props->qpic_version2) - write_reg_dma(nandc, &nandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1= , 0); - write_reg_dma(nandc, &nandc->regs->erased_cw_detect_cfg_clr, - NAND_ERASED_CW_DETECT_CFG, 1, 0); - write_reg_dma(nandc, &nandc->regs->erased_cw_detect_cfg_set, - NAND_ERASED_CW_DETECT_CFG, 1, NAND_ERASED_CW_SET | NAND_BAM_NEXT_S= GL); + qcom_write_reg_dma(nandc, &nandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_C= FG, 1, 0); + qcom_write_reg_dma(nandc, &nandc->regs->erased_cw_detect_cfg_clr, + NAND_ERASED_CW_DETECT_CFG, 1, 0); + qcom_write_reg_dma(nandc, &nandc->regs->erased_cw_detect_cfg_set, + NAND_ERASED_CW_DETECT_CFG, 1, NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL= ); } =20 /* @@ -1204,17 +1203,17 @@ config_nand_cw_read(struct nand_chip *chip, bool us= e_ecc, int cw) reg =3D &nandc->regs->read_location_last0; =20 if (nandc->props->supports_bam) - write_reg_dma(nandc, reg, NAND_READ_LOCATION_0, 4, NAND_BAM_NEXT_SGL); + qcom_write_reg_dma(nandc, reg, NAND_READ_LOCATION_0, 4, NAND_BAM_NEXT_SG= L); =20 - write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_= SGL); - write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_= SGL); + qcom_write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_= NEXT_SGL); + qcom_write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_= NEXT_SGL); =20 if (use_ecc) { - read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0); - read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1, - NAND_BAM_NEXT_SGL); + qcom_read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0); + qcom_read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1, + NAND_BAM_NEXT_SGL); } else { - read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); + qcom_read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); } } =20 @@ -1238,11 +1237,11 @@ static void config_nand_page_write(struct nand_chip= *chip) { struct qcom_nand_controller *nandc =3D get_qcom_nand_controller(chip); =20 - write_reg_dma(nandc, &nandc->regs->addr0, NAND_ADDR0, 2, 0); - write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); + qcom_write_reg_dma(nandc, &nandc->regs->addr0, NAND_ADDR0, 2, 0); + qcom_write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); if (!nandc->props->qpic_version2) - write_reg_dma(nandc, &nandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1, - NAND_BAM_NEXT_SGL); + qcom_write_reg_dma(nandc, &nandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_C= FG, 1, + NAND_BAM_NEXT_SGL); } =20 /* @@ -1253,17 +1252,18 @@ static void config_nand_cw_write(struct nand_chip *= chip) { struct qcom_nand_controller *nandc =3D get_qcom_nand_controller(chip); =20 - write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_= SGL); - write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_= SGL); + qcom_write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_= NEXT_SGL); + qcom_write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_= NEXT_SGL); =20 - read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); + qcom_read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); =20 - write_reg_dma(nandc, &nandc->regs->clrflashstatus, NAND_FLASH_STATUS, 1, = 0); - write_reg_dma(nandc, &nandc->regs->clrreadstatus, NAND_READ_STATUS, 1, NA= ND_BAM_NEXT_SGL); + qcom_write_reg_dma(nandc, &nandc->regs->clrflashstatus, NAND_FLASH_STATUS= , 1, 0); + qcom_write_reg_dma(nandc, &nandc->regs->clrreadstatus, NAND_READ_STATUS, = 1, + NAND_BAM_NEXT_SGL); } =20 /* helpers to submit/free our list of dma descriptors */ -static int submit_descs(struct qcom_nand_controller *nandc) +static int qcom_submit_descs(struct qcom_nand_controller *nandc) { struct desc_info *desc, *n; dma_cookie_t cookie =3D 0; @@ -1272,21 +1272,21 @@ static int submit_descs(struct qcom_nand_controller= *nandc) =20 if (nandc->props->supports_bam) { if (bam_txn->rx_sgl_pos > bam_txn->rx_sgl_start) { - ret =3D prepare_bam_async_desc(nandc, nandc->rx_chan, 0); + ret =3D qcom_prepare_bam_async_desc(nandc, nandc->rx_chan, 0); if (ret) goto err_unmap_free_desc; } =20 if (bam_txn->tx_sgl_pos > bam_txn->tx_sgl_start) { - ret =3D prepare_bam_async_desc(nandc, nandc->tx_chan, - DMA_PREP_INTERRUPT); + ret =3D qcom_prepare_bam_async_desc(nandc, nandc->tx_chan, + DMA_PREP_INTERRUPT); if (ret) goto err_unmap_free_desc; } =20 if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) { - ret =3D prepare_bam_async_desc(nandc, nandc->cmd_chan, - DMA_PREP_CMD); + ret =3D qcom_prepare_bam_async_desc(nandc, nandc->cmd_chan, + DMA_PREP_CMD); if (ret) goto err_unmap_free_desc; } @@ -1296,7 +1296,7 @@ static int submit_descs(struct qcom_nand_controller *= nandc) cookie =3D dmaengine_submit(desc->dma_desc); =20 if (nandc->props->supports_bam) { - bam_txn->last_cmd_desc->callback =3D qpic_bam_dma_done; + bam_txn->last_cmd_desc->callback =3D qcom_qpic_bam_dma_done; bam_txn->last_cmd_desc->callback_param =3D bam_txn; =20 dma_async_issue_pending(nandc->tx_chan); @@ -1314,7 +1314,7 @@ static int submit_descs(struct qcom_nand_controller *= nandc) err_unmap_free_desc: /* * Unmap the dma sg_list and free the desc allocated by both - * prepare_bam_async_desc() and prep_adm_dma_desc() functions. + * qcom_prepare_bam_async_desc() and qcom_prep_adm_dma_desc() functions. */ list_for_each_entry_safe(desc, n, &nandc->desc_list, node) { list_del(&desc->node); @@ -1333,10 +1333,10 @@ static int submit_descs(struct qcom_nand_controller= *nandc) } =20 /* reset the register read buffer for next NAND operation */ -static void clear_read_regs(struct qcom_nand_controller *nandc) +static void qcom_clear_read_regs(struct qcom_nand_controller *nandc) { nandc->reg_read_pos =3D 0; - nandc_dev_to_mem(nandc, false); + qcom_nandc_dev_to_mem(nandc, false); } =20 /* @@ -1400,7 +1400,7 @@ static int check_flash_errors(struct qcom_nand_host *= host, int cw_cnt) struct qcom_nand_controller *nandc =3D get_qcom_nand_controller(chip); int i; =20 - nandc_dev_to_mem(nandc, true); + qcom_nandc_dev_to_mem(nandc, true); =20 for (i =3D 0; i < cw_cnt; i++) { u32 flash =3D le32_to_cpu(nandc->reg_read_buf[i]); @@ -1427,13 +1427,13 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct= nand_chip *chip, nand_read_page_op(chip, page, 0, NULL, 0); nandc->buf_count =3D 0; nandc->buf_start =3D 0; - clear_read_regs(nandc); + qcom_clear_read_regs(nandc); host->use_ecc =3D false; =20 if (nandc->props->qpic_version2) raw_cw =3D ecc->steps - 1; =20 - clear_bam_transaction(nandc); + qcom_clear_bam_transaction(nandc); set_address(host, host->cw_size * cw, page); update_rw_regs(host, 1, true, raw_cw); config_nand_page_read(chip); @@ -1466,18 +1466,18 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct= nand_chip *chip, =20 config_nand_cw_read(chip, false, raw_cw); =20 - read_data_dma(nandc, reg_off, data_buf, data_size1, 0); + qcom_read_data_dma(nandc, reg_off, data_buf, data_size1, 0); reg_off +=3D data_size1; =20 - read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0); + qcom_read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0); reg_off +=3D oob_size1; =20 - read_data_dma(nandc, reg_off, data_buf + data_size1, data_size2, 0); + qcom_read_data_dma(nandc, reg_off, data_buf + data_size1, data_size2, 0); reg_off +=3D data_size2; =20 - read_data_dma(nandc, reg_off, oob_buf + oob_size1, oob_size2, 0); + qcom_read_data_dma(nandc, reg_off, oob_buf + oob_size1, oob_size2, 0); =20 - ret =3D submit_descs(nandc); + ret =3D qcom_submit_descs(nandc); if (ret) { dev_err(nandc->dev, "failure to read raw cw %d\n", cw); return ret; @@ -1575,7 +1575,7 @@ static int parse_read_errors(struct qcom_nand_host *h= ost, u8 *data_buf, u8 *data_buf_start =3D data_buf, *oob_buf_start =3D oob_buf; =20 buf =3D (struct read_stats *)nandc->reg_read_buf; - nandc_dev_to_mem(nandc, true); + qcom_nandc_dev_to_mem(nandc, true); =20 for (i =3D 0; i < ecc->steps; i++, buf++) { u32 flash, buffer, erased_cw; @@ -1704,8 +1704,8 @@ static int read_page_ecc(struct qcom_nand_host *host,= u8 *data_buf, config_nand_cw_read(chip, true, i); =20 if (data_buf) - read_data_dma(nandc, FLASH_BUF_ACC, data_buf, - data_size, 0); + qcom_read_data_dma(nandc, FLASH_BUF_ACC, data_buf, + data_size, 0); =20 /* * when ecc is enabled, the controller doesn't read the real @@ -1720,8 +1720,8 @@ static int read_page_ecc(struct qcom_nand_host *host,= u8 *data_buf, for (j =3D 0; j < host->bbm_size; j++) *oob_buf++ =3D 0xff; =20 - read_data_dma(nandc, FLASH_BUF_ACC + data_size, - oob_buf, oob_size, 0); + qcom_read_data_dma(nandc, FLASH_BUF_ACC + data_size, + oob_buf, oob_size, 0); } =20 if (data_buf) @@ -1730,7 +1730,7 @@ static int read_page_ecc(struct qcom_nand_host *host,= u8 *data_buf, oob_buf +=3D oob_size; } =20 - ret =3D submit_descs(nandc); + ret =3D qcom_submit_descs(nandc); if (ret) { dev_err(nandc->dev, "failure to read page/oob\n"); return ret; @@ -1751,7 +1751,7 @@ static int copy_last_cw(struct qcom_nand_host *host, = int page) int size; int ret; =20 - clear_read_regs(nandc); + qcom_clear_read_regs(nandc); =20 size =3D host->use_ecc ? host->cw_data : host->cw_size; =20 @@ -1763,9 +1763,9 @@ static int copy_last_cw(struct qcom_nand_host *host, = int page) =20 config_nand_single_cw_page_read(chip, host->use_ecc, ecc->steps - 1); =20 - read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0); + qcom_read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0); =20 - ret =3D submit_descs(nandc); + ret =3D qcom_submit_descs(nandc); if (ret) dev_err(nandc->dev, "failed to copy last codeword\n"); =20 @@ -1851,14 +1851,14 @@ static int qcom_nandc_read_page(struct nand_chip *c= hip, u8 *buf, nandc->buf_count =3D 0; nandc->buf_start =3D 0; host->use_ecc =3D true; - clear_read_regs(nandc); + qcom_clear_read_regs(nandc); set_address(host, 0, page); update_rw_regs(host, ecc->steps, true, 0); =20 data_buf =3D buf; oob_buf =3D oob_required ? chip->oob_poi : NULL; =20 - clear_bam_transaction(nandc); + qcom_clear_bam_transaction(nandc); =20 return read_page_ecc(host, data_buf, oob_buf, page); } @@ -1899,8 +1899,8 @@ static int qcom_nandc_read_oob(struct nand_chip *chip= , int page) if (host->nr_boot_partitions) qcom_nandc_codeword_fixup(host, page); =20 - clear_read_regs(nandc); - clear_bam_transaction(nandc); + qcom_clear_read_regs(nandc); + qcom_clear_bam_transaction(nandc); =20 host->use_ecc =3D true; set_address(host, 0, page); @@ -1927,8 +1927,8 @@ static int qcom_nandc_write_page(struct nand_chip *ch= ip, const u8 *buf, set_address(host, 0, page); nandc->buf_count =3D 0; nandc->buf_start =3D 0; - clear_read_regs(nandc); - clear_bam_transaction(nandc); + qcom_clear_read_regs(nandc); + qcom_clear_bam_transaction(nandc); =20 data_buf =3D (u8 *)buf; oob_buf =3D chip->oob_poi; @@ -1949,8 +1949,8 @@ static int qcom_nandc_write_page(struct nand_chip *ch= ip, const u8 *buf, oob_size =3D ecc->bytes; } =20 - write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size, - i =3D=3D (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0); + qcom_write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size, + i =3D=3D (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0); =20 /* * when ECC is enabled, we don't really need to write anything @@ -1962,8 +1962,8 @@ static int qcom_nandc_write_page(struct nand_chip *ch= ip, const u8 *buf, if (qcom_nandc_is_last_cw(ecc, i)) { oob_buf +=3D host->bbm_size; =20 - write_data_dma(nandc, FLASH_BUF_ACC + data_size, - oob_buf, oob_size, 0); + qcom_write_data_dma(nandc, FLASH_BUF_ACC + data_size, + oob_buf, oob_size, 0); } =20 config_nand_cw_write(chip); @@ -1972,7 +1972,7 @@ static int qcom_nandc_write_page(struct nand_chip *ch= ip, const u8 *buf, oob_buf +=3D oob_size; } =20 - ret =3D submit_descs(nandc); + ret =3D qcom_submit_descs(nandc); if (ret) { dev_err(nandc->dev, "failure to write page\n"); return ret; @@ -1997,8 +1997,8 @@ static int qcom_nandc_write_page_raw(struct nand_chip= *chip, qcom_nandc_codeword_fixup(host, page); =20 nand_prog_page_begin_op(chip, page, 0, NULL, 0); - clear_read_regs(nandc); - clear_bam_transaction(nandc); + qcom_clear_read_regs(nandc); + qcom_clear_bam_transaction(nandc); =20 data_buf =3D (u8 *)buf; oob_buf =3D chip->oob_poi; @@ -2024,28 +2024,28 @@ static int qcom_nandc_write_page_raw(struct nand_ch= ip *chip, oob_size2 =3D host->ecc_bytes_hw + host->spare_bytes; } =20 - write_data_dma(nandc, reg_off, data_buf, data_size1, - NAND_BAM_NO_EOT); + qcom_write_data_dma(nandc, reg_off, data_buf, data_size1, + NAND_BAM_NO_EOT); reg_off +=3D data_size1; data_buf +=3D data_size1; =20 - write_data_dma(nandc, reg_off, oob_buf, oob_size1, - NAND_BAM_NO_EOT); + qcom_write_data_dma(nandc, reg_off, oob_buf, oob_size1, + NAND_BAM_NO_EOT); reg_off +=3D oob_size1; oob_buf +=3D oob_size1; =20 - write_data_dma(nandc, reg_off, data_buf, data_size2, - NAND_BAM_NO_EOT); + qcom_write_data_dma(nandc, reg_off, data_buf, data_size2, + NAND_BAM_NO_EOT); reg_off +=3D data_size2; data_buf +=3D data_size2; =20 - write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0); + qcom_write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0); oob_buf +=3D oob_size2; =20 config_nand_cw_write(chip); } =20 - ret =3D submit_descs(nandc); + ret =3D qcom_submit_descs(nandc); if (ret) { dev_err(nandc->dev, "failure to write raw page\n"); return ret; @@ -2075,7 +2075,7 @@ static int qcom_nandc_write_oob(struct nand_chip *chi= p, int page) qcom_nandc_codeword_fixup(host, page); =20 host->use_ecc =3D true; - clear_bam_transaction(nandc); + qcom_clear_bam_transaction(nandc); =20 /* calculate the data and oob size for the last codeword/step */ data_size =3D ecc->size - ((ecc->steps - 1) << 2); @@ -2090,11 +2090,11 @@ static int qcom_nandc_write_oob(struct nand_chip *c= hip, int page) update_rw_regs(host, 1, false, 0); =20 config_nand_page_write(chip); - write_data_dma(nandc, FLASH_BUF_ACC, - nandc->data_buffer, data_size + oob_size, 0); + qcom_write_data_dma(nandc, FLASH_BUF_ACC, + nandc->data_buffer, data_size + oob_size, 0); config_nand_cw_write(chip); =20 - ret =3D submit_descs(nandc); + ret =3D qcom_submit_descs(nandc); if (ret) { dev_err(nandc->dev, "failure to write oob\n"); return ret; @@ -2121,7 +2121,7 @@ static int qcom_nandc_block_bad(struct nand_chip *chi= p, loff_t ofs) */ host->use_ecc =3D false; =20 - clear_bam_transaction(nandc); + qcom_clear_bam_transaction(nandc); ret =3D copy_last_cw(host, page); if (ret) goto err; @@ -2148,8 +2148,8 @@ static int qcom_nandc_block_markbad(struct nand_chip = *chip, loff_t ofs) struct nand_ecc_ctrl *ecc =3D &chip->ecc; int page, ret; =20 - clear_read_regs(nandc); - clear_bam_transaction(nandc); + qcom_clear_read_regs(nandc); + qcom_clear_bam_transaction(nandc); =20 /* * to mark the BBM as bad, we flash the entire last codeword with 0s. @@ -2166,11 +2166,11 @@ static int qcom_nandc_block_markbad(struct nand_chi= p *chip, loff_t ofs) update_rw_regs(host, 1, false, ecc->steps - 1); =20 config_nand_page_write(chip); - write_data_dma(nandc, FLASH_BUF_ACC, - nandc->data_buffer, host->cw_size, 0); + qcom_write_data_dma(nandc, FLASH_BUF_ACC, + nandc->data_buffer, host->cw_size, 0); config_nand_cw_write(chip); =20 - ret =3D submit_descs(nandc); + ret =3D qcom_submit_descs(nandc); if (ret) { dev_err(nandc->dev, "failure to update BBM\n"); return ret; @@ -2410,14 +2410,14 @@ static int qcom_nand_attach_chip(struct nand_chip *= chip) mtd_set_ooblayout(mtd, &qcom_nand_ooblayout_ops); /* Free the initially allocated BAM transaction for reading the ONFI para= ms */ if (nandc->props->supports_bam) - free_bam_transaction(nandc); + qcom_free_bam_transaction(nandc); =20 nandc->max_cwperpage =3D max_t(unsigned int, nandc->max_cwperpage, cwperpage); =20 /* Now allocate the BAM transaction based on updated max_cwperpage */ if (nandc->props->supports_bam) { - nandc->bam_txn =3D alloc_bam_transaction(nandc); + nandc->bam_txn =3D qcom_alloc_bam_transaction(nandc); if (!nandc->bam_txn) { dev_err(nandc->dev, "failed to allocate bam transaction\n"); @@ -2617,7 +2617,7 @@ static int qcom_wait_rdy_poll(struct nand_chip *chip,= unsigned int time_ms) unsigned long start =3D jiffies + msecs_to_jiffies(time_ms); u32 flash; =20 - nandc_dev_to_mem(nandc, true); + qcom_nandc_dev_to_mem(nandc, true); =20 do { flash =3D le32_to_cpu(nandc->reg_read_buf[0]); @@ -2657,23 +2657,23 @@ static int qcom_read_status_exec(struct nand_chip *= chip, nandc->buf_start =3D 0; host->use_ecc =3D false; =20 - clear_read_regs(nandc); - clear_bam_transaction(nandc); + qcom_clear_read_regs(nandc); + qcom_clear_bam_transaction(nandc); =20 nandc->regs->cmd =3D q_op.cmd_reg; nandc->regs->exec =3D cpu_to_le32(1); =20 - write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_= SGL); - write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_= SGL); - read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); + qcom_write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_= NEXT_SGL); + qcom_write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_= NEXT_SGL); + qcom_read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); =20 - ret =3D submit_descs(nandc); + ret =3D qcom_submit_descs(nandc); if (ret) { dev_err(nandc->dev, "failure in submitting status descriptor\n"); goto err_out; } =20 - nandc_dev_to_mem(nandc, true); + qcom_nandc_dev_to_mem(nandc, true); =20 for (i =3D 0; i < num_cw; i++) { flash_status =3D le32_to_cpu(nandc->reg_read_buf[i]); @@ -2714,8 +2714,8 @@ static int qcom_read_id_type_exec(struct nand_chip *c= hip, const struct nand_subo nandc->buf_start =3D 0; host->use_ecc =3D false; =20 - clear_read_regs(nandc); - clear_bam_transaction(nandc); + qcom_clear_read_regs(nandc); + qcom_clear_bam_transaction(nandc); =20 nandc->regs->cmd =3D q_op.cmd_reg; nandc->regs->addr0 =3D q_op.addr1_reg; @@ -2723,12 +2723,12 @@ static int qcom_read_id_type_exec(struct nand_chip = *chip, const struct nand_subo nandc->regs->chip_sel =3D cpu_to_le32(nandc->props->supports_bam ? 0 : DM= _EN); nandc->regs->exec =3D cpu_to_le32(1); =20 - write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_= SGL); - write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_= SGL); + qcom_write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 4, NAND_BAM_= NEXT_SGL); + qcom_write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_= NEXT_SGL); =20 - read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL); + qcom_read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL); =20 - ret =3D submit_descs(nandc); + ret =3D qcom_submit_descs(nandc); if (ret) { dev_err(nandc->dev, "failure in submitting read id descriptor\n"); goto err_out; @@ -2738,7 +2738,7 @@ static int qcom_read_id_type_exec(struct nand_chip *c= hip, const struct nand_subo op_id =3D q_op.data_instr_idx; len =3D nand_subop_get_data_len(subop, op_id); =20 - nandc_dev_to_mem(nandc, true); + qcom_nandc_dev_to_mem(nandc, true); memcpy(instr->ctx.data.buf.in, nandc->reg_read_buf, len); =20 err_out: @@ -2774,20 +2774,20 @@ static int qcom_misc_cmd_type_exec(struct nand_chip= *chip, const struct nand_sub nandc->buf_start =3D 0; host->use_ecc =3D false; =20 - clear_read_regs(nandc); - clear_bam_transaction(nandc); + qcom_clear_read_regs(nandc); + qcom_clear_bam_transaction(nandc); =20 nandc->regs->cmd =3D q_op.cmd_reg; nandc->regs->exec =3D cpu_to_le32(1); =20 - write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, instrs, NAND_BAM_= NEXT_SGL); + qcom_write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, instrs, NAND= _BAM_NEXT_SGL); if (q_op.cmd_reg =3D=3D cpu_to_le32(OP_BLOCK_ERASE)) - write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 2, NAND_BAM_NEX= T_SGL); + qcom_write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 2, NAND_BA= M_NEXT_SGL); =20 - write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_= SGL); - read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); + qcom_write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_= NEXT_SGL); + qcom_read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); =20 - ret =3D submit_descs(nandc); + ret =3D qcom_submit_descs(nandc); if (ret) { dev_err(nandc->dev, "failure in submitting misc descriptor\n"); goto err_out; @@ -2820,8 +2820,8 @@ static int qcom_param_page_type_exec(struct nand_chip= *chip, const struct nand_ nandc->buf_count =3D 0; nandc->buf_start =3D 0; host->use_ecc =3D false; - clear_read_regs(nandc); - clear_bam_transaction(nandc); + qcom_clear_read_regs(nandc); + qcom_clear_bam_transaction(nandc); =20 nandc->regs->cmd =3D q_op.cmd_reg; nandc->regs->addr0 =3D 0; @@ -2864,8 +2864,8 @@ static int qcom_param_page_type_exec(struct nand_chip= *chip, const struct nand_ nandc_set_read_loc(chip, 0, 0, 0, len, 1); =20 if (!nandc->props->qpic_version2) { - write_reg_dma(nandc, &nandc->regs->vld, NAND_DEV_CMD_VLD, 1, 0); - write_reg_dma(nandc, &nandc->regs->cmd1, NAND_DEV_CMD1, 1, NAND_BAM_NEXT= _SGL); + qcom_write_reg_dma(nandc, &nandc->regs->vld, NAND_DEV_CMD_VLD, 1, 0); + qcom_write_reg_dma(nandc, &nandc->regs->cmd1, NAND_DEV_CMD1, 1, NAND_BAM= _NEXT_SGL); } =20 nandc->buf_count =3D len; @@ -2873,17 +2873,17 @@ static int qcom_param_page_type_exec(struct nand_ch= ip *chip, const struct nand_ =20 config_nand_single_cw_page_read(chip, false, 0); =20 - read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, - nandc->buf_count, 0); + qcom_read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, + nandc->buf_count, 0); =20 /* restore CMD1 and VLD regs */ if (!nandc->props->qpic_version2) { - write_reg_dma(nandc, &nandc->regs->orig_cmd1, NAND_DEV_CMD1_RESTORE, 1, = 0); - write_reg_dma(nandc, &nandc->regs->orig_vld, NAND_DEV_CMD_VLD_RESTORE, 1, - NAND_BAM_NEXT_SGL); + qcom_write_reg_dma(nandc, &nandc->regs->orig_cmd1, NAND_DEV_CMD1_RESTORE= , 1, 0); + qcom_write_reg_dma(nandc, &nandc->regs->orig_vld, NAND_DEV_CMD_VLD_RESTO= RE, 1, + NAND_BAM_NEXT_SGL); } =20 - ret =3D submit_descs(nandc); + ret =3D qcom_submit_descs(nandc); if (ret) { dev_err(nandc->dev, "failure in submitting param page descriptor\n"); goto err_out; @@ -3067,7 +3067,7 @@ static int qcom_nandc_alloc(struct qcom_nand_controll= er *nandc) * maximum codeword size */ nandc->max_cwperpage =3D 1; - nandc->bam_txn =3D alloc_bam_transaction(nandc); + nandc->bam_txn =3D qcom_alloc_bam_transaction(nandc); if (!nandc->bam_txn) { dev_err(nandc->dev, "failed to allocate bam transaction\n"); --=20 2.34.1 From nobody Sat Nov 30 03:41:48 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CE2718CC0F; Thu, 12 Sep 2024 06:16:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726121782; cv=none; b=FB/mEbuK8ZOFokKjCd2/H5MD9CFsmrsMeuqG7kL7mGmjk3S8Tpgmzu+UDKLThf1NVqv8WNQsZVsA70klj5fj/5zujDdnI/AOPMlh7Rc6E445NDaFn2kveWGnLNpQ7BD/7W3ZzYxxe0oAO8G/izpY/Lvx0/5UudFBiY17+ZiEbjU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726121782; c=relaxed/simple; bh=eI6ldKbV4b6FUVrV+wV9cNXtYozzhyoBIcSSmKBMNlY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JFtm7fNAbj0qTh7zwTGII4mTsmZuqM6n1siHiWVjKdCLn1oQxS9zS0sT8yow/mXC+1WtpgEV/AMd++9gbLtd8WjxEvZAd6N5MEW1PnW6aVfQ7dv5ru9XI1IUP9i/Au9UbyI0H9q/Y873ieUWTQo0f9DK+QxFWGKOfLsGPY5wI1A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=MLPlklfv; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="MLPlklfv" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48C2L8h9017360; Thu, 12 Sep 2024 06:15:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Fu02s8SnA3uZ3H96d1sjg6e56N8ZXAbz8ARIksSF4iE=; b=MLPlklfvC55Z8dNz nX5fwJf9CbNdjC4OkZorIqsSq+Vg04TsqMW6ET7LNPi5RrxkWnx4TlBrbd23fwh7 b/h9jEwVbXb164PTMMXtljtnWIpiRpgKQqSNzmSpfj8T7QRQA5tBvbhQKQY5KyrJ QftcXDl/4Mt6uqTSPAL3J2TPR0Uow+wxy2dpqdgy5J0GIimFIaw+FAuwBOIJBuZf 8MS28SwK+HEnahEylPiRuDLoqR9W7hOsTvDpRDXrNonHg510n0+yaTn321CsEupy kTw5lrVePoeXFq52q5rwLkCSzdWmjjkaPydwYG27JzcZtveMCUPLDQEEBXjUbBkJ 1FR9Og== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41gy6sv658-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Sep 2024 06:15:48 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48C6Fl3I012468 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Sep 2024 06:15:47 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Sep 2024 23:15:41 -0700 From: Md Sadre Alam To: , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v9 4/8] mtd: nand: Add qpic_common API file Date: Thu, 12 Sep 2024 11:44:59 +0530 Message-ID: <20240912061503.3468147-5-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240912061503.3468147-1-quic_mdalam@quicinc.com> References: <20240912061503.3468147-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: KggYGiAUTIZLRBWvMM1uNn9qVncFWidK X-Proofpoint-ORIG-GUID: KggYGiAUTIZLRBWvMM1uNn9qVncFWidK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 suspectscore=0 mlxlogscore=999 malwarescore=0 mlxscore=0 bulkscore=0 adultscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409120043 Content-Type: text/plain; charset="utf-8" Add qpic_common.c file which hold all the common qpic APIs which will be used by both qpic raw nand driver and qpic spi nand driver. Signed-off-by: Md Sadre Alam --- Change in [v9] * No Change=20 Change in [v8] * Removed "inline" from qcom_nandc_dev_to_mem() Change in [v7] * Removed partition.h * Updated commit message heading * Made CONFIG_MTD_NAND_QCOM as bool Change in [v6] * made changes to select qpic_common.c based on either CONFIG_MTD_NAND_QCOM=3Dy or CONFIG_SPI_QPIC_SNAND=3Dy * Removed rawnand.h from qpic_common.c * change nand_controller variable as a pointer type. Change in [v5] * Remove multiple dma call back to avoid race condition Change in [v4] * Added kernel doc for all common api as per kernel doc standard * Added QPIC_COMMON config to build qpic_common.c Change in [v3] * Added original copy right * Removed all EXPORT_SYMBOL() * Made this common api file more generic * Added qcom_ prefix to all api in this file * Removed devm_kfree and added kfree * Moved to_qcom_nand_controller() to raw nand driver since it was only used by raw nand driver, so not needed as common * Added kernel doc for all api * made reverse tree of variable declaration in=20 prep_adm_dma_desc() function * Added if(!ret) condition in prep_adm_dma_desc() function * Initialized slave_conf as 0 while declaration Change in [v2] * Posted initial support for common api file Change in [v1] * Posted as RFC patch for design review drivers/mtd/nand/Makefile | 4 + drivers/mtd/nand/qpic_common.c | 738 +++++++++++++++++ drivers/mtd/nand/raw/Kconfig | 2 +- drivers/mtd/nand/raw/qcom_nandc.c | 1092 +------------------------- include/linux/mtd/nand-qpic-common.h | 468 +++++++++++ 5 files changed, 1223 insertions(+), 1081 deletions(-) create mode 100644 drivers/mtd/nand/qpic_common.c create mode 100644 include/linux/mtd/nand-qpic-common.h diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 19e1291ac4d5..760a6e4efdac 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -4,6 +4,10 @@ nandcore-objs :=3D core.o bbt.o obj-$(CONFIG_MTD_NAND_CORE) +=3D nandcore.o obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) +=3D ecc-mtk.o =20 +ifeq ($(CONFIG_MTD_NAND_QCOM),y) +obj-y +=3D qpic_common.o +endif + obj-y +=3D onenand/ obj-y +=3D raw/ obj-y +=3D spi/ diff --git a/drivers/mtd/nand/qpic_common.c b/drivers/mtd/nand/qpic_common.c new file mode 100644 index 000000000000..2fe1a82307b4 --- /dev/null +++ b/drivers/mtd/nand/qpic_common.c @@ -0,0 +1,738 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * qcom_free_bam_transaction() - Frees the BAM transaction memory + * @nandc: qpic nand controller + * + * This function frees the bam transaction memory + */ +void qcom_free_bam_transaction(struct qcom_nand_controller *nandc) +{ + struct bam_transaction *bam_txn =3D nandc->bam_txn; + + kfree(bam_txn); +} + +/** + * qcom_alloc_bam_transaction() - allocate BAM transaction + * @nandc: qpic nand controller + * + * This function will allocate and initialize the BAM transaction structure + */ +struct bam_transaction * +qcom_alloc_bam_transaction(struct qcom_nand_controller *nandc) +{ + struct bam_transaction *bam_txn; + size_t bam_txn_size; + unsigned int num_cw =3D nandc->max_cwperpage; + void *bam_txn_buf; + + bam_txn_size =3D + sizeof(*bam_txn) + num_cw * + ((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) + + (sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) + + (sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL)); + + bam_txn_buf =3D kzalloc(bam_txn_size, GFP_KERNEL); + if (!bam_txn_buf) + return NULL; + + bam_txn =3D bam_txn_buf; + bam_txn_buf +=3D sizeof(*bam_txn); + + bam_txn->bam_ce =3D bam_txn_buf; + bam_txn_buf +=3D + sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS * num_cw; + + bam_txn->cmd_sgl =3D bam_txn_buf; + bam_txn_buf +=3D + sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL * num_cw; + + bam_txn->data_sgl =3D bam_txn_buf; + + init_completion(&bam_txn->txn_done); + + return bam_txn; +} + +/** + * qcom_clear_bam_transaction() - Clears the BAM transaction + * @nandc: qpic nand controller + * + * This function will clear the BAM transaction indexes. + */ +void qcom_clear_bam_transaction(struct qcom_nand_controller *nandc) +{ + struct bam_transaction *bam_txn =3D nandc->bam_txn; + + if (!nandc->props->supports_bam) + return; + + memset(&bam_txn->bam_ce_pos, 0, sizeof(u32) * 8); + bam_txn->last_data_desc =3D NULL; + + sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage * + QPIC_PER_CW_CMD_SGL); + sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage * + QPIC_PER_CW_DATA_SGL); + + reinit_completion(&bam_txn->txn_done); +} + +/** + * qcom_qpic_bam_dma_done() - Callback for DMA descriptor completion + * @data: data pointer + * + * This function is a callback for DMA descriptor completion + */ +void qcom_qpic_bam_dma_done(void *data) +{ + struct bam_transaction *bam_txn =3D data; + + complete(&bam_txn->txn_done); +} + +/** + * qcom_nandc_dev_to_mem() - Check for dma sync for cpu or device + * @nandc: qpic nand controller + * @is_cpu: cpu or Device + * + * This function will check for dma sync for cpu or device + */ +inline void qcom_nandc_dev_to_mem(struct qcom_nand_controller *nandc, bool= is_cpu) +{ + if (!nandc->props->supports_bam) + return; + + if (is_cpu) + dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_dma, + MAX_REG_RD * + sizeof(*nandc->reg_read_buf), + DMA_FROM_DEVICE); + else + dma_sync_single_for_device(nandc->dev, nandc->reg_read_dma, + MAX_REG_RD * + sizeof(*nandc->reg_read_buf), + DMA_FROM_DEVICE); +} + +/** + * qcom_prepare_bam_async_desc() - Prepare DMA descriptor + * @nandc: qpic nand controller + * @chan: dma channel + * @flags: flags to control DMA descriptor preparation + * + * This function maps the scatter gather list for DMA transfer and forms t= he + * DMA descriptor for BAM.This descriptor will be added in the NAND DMA + * descriptor queue which will be submitted to DMA engine. + */ +int qcom_prepare_bam_async_desc(struct qcom_nand_controller *nandc, + struct dma_chan *chan, unsigned long flags) +{ + struct desc_info *desc; + struct scatterlist *sgl; + unsigned int sgl_cnt; + int ret; + struct bam_transaction *bam_txn =3D nandc->bam_txn; + enum dma_transfer_direction dir_eng; + struct dma_async_tx_descriptor *dma_desc; + + desc =3D kzalloc(sizeof(*desc), GFP_KERNEL); + if (!desc) + return -ENOMEM; + + if (chan =3D=3D nandc->cmd_chan) { + sgl =3D &bam_txn->cmd_sgl[bam_txn->cmd_sgl_start]; + sgl_cnt =3D bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start; + bam_txn->cmd_sgl_start =3D bam_txn->cmd_sgl_pos; + dir_eng =3D DMA_MEM_TO_DEV; + desc->dir =3D DMA_TO_DEVICE; + } else if (chan =3D=3D nandc->tx_chan) { + sgl =3D &bam_txn->data_sgl[bam_txn->tx_sgl_start]; + sgl_cnt =3D bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start; + bam_txn->tx_sgl_start =3D bam_txn->tx_sgl_pos; + dir_eng =3D DMA_MEM_TO_DEV; + desc->dir =3D DMA_TO_DEVICE; + } else { + sgl =3D &bam_txn->data_sgl[bam_txn->rx_sgl_start]; + sgl_cnt =3D bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start; + bam_txn->rx_sgl_start =3D bam_txn->rx_sgl_pos; + dir_eng =3D DMA_DEV_TO_MEM; + desc->dir =3D DMA_FROM_DEVICE; + } + + sg_mark_end(sgl + sgl_cnt - 1); + ret =3D dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir); + if (ret =3D=3D 0) { + dev_err(nandc->dev, "failure in mapping desc\n"); + kfree(desc); + return -ENOMEM; + } + + desc->sgl_cnt =3D sgl_cnt; + desc->bam_sgl =3D sgl; + + dma_desc =3D dmaengine_prep_slave_sg(chan, sgl, sgl_cnt, dir_eng, + flags); + + if (!dma_desc) { + dev_err(nandc->dev, "failure in prep desc\n"); + dma_unmap_sg(nandc->dev, sgl, sgl_cnt, desc->dir); + kfree(desc); + return -EINVAL; + } + + desc->dma_desc =3D dma_desc; + + /* update last data/command descriptor */ + if (chan =3D=3D nandc->cmd_chan) + bam_txn->last_cmd_desc =3D dma_desc; + else + bam_txn->last_data_desc =3D dma_desc; + + list_add_tail(&desc->node, &nandc->desc_list); + + return 0; +} + +/** + * qcom_prep_bam_dma_desc_cmd() - Prepares the command descriptor for BAM = DMA + * @nandc: qpic nand controller + * @read: read or write type + * @reg_off: offset within the controller's data buffer + * @vaddr: virtual address of the buffer we want to write to + * @size: DMA transaction size in bytes + * @flags: flags to control DMA descriptor preparation + * + * This function will prepares the command descriptor for BAM DMA + * which will be used for NAND register reads and writes. + */ +int qcom_prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool re= ad, + int reg_off, const void *vaddr, + int size, unsigned int flags) +{ + int bam_ce_size; + int i, ret; + struct bam_cmd_element *bam_ce_buffer; + struct bam_transaction *bam_txn =3D nandc->bam_txn; + + bam_ce_buffer =3D &bam_txn->bam_ce[bam_txn->bam_ce_pos]; + + /* fill the command desc */ + for (i =3D 0; i < size; i++) { + if (read) + bam_prep_ce(&bam_ce_buffer[i], + nandc_reg_phys(nandc, reg_off + 4 * i), + BAM_READ_COMMAND, + reg_buf_dma_addr(nandc, + (__le32 *)vaddr + i)); + else + bam_prep_ce_le32(&bam_ce_buffer[i], + nandc_reg_phys(nandc, reg_off + 4 * i), + BAM_WRITE_COMMAND, + *((__le32 *)vaddr + i)); + } + + bam_txn->bam_ce_pos +=3D size; + + /* use the separate sgl after this command */ + if (flags & NAND_BAM_NEXT_SGL) { + bam_ce_buffer =3D &bam_txn->bam_ce[bam_txn->bam_ce_start]; + bam_ce_size =3D (bam_txn->bam_ce_pos - + bam_txn->bam_ce_start) * + sizeof(struct bam_cmd_element); + sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos], + bam_ce_buffer, bam_ce_size); + bam_txn->cmd_sgl_pos++; + bam_txn->bam_ce_start =3D bam_txn->bam_ce_pos; + + if (flags & NAND_BAM_NWD) { + ret =3D qcom_prepare_bam_async_desc(nandc, nandc->cmd_chan, + DMA_PREP_FENCE | DMA_PREP_CMD); + if (ret) + return ret; + } + } + + return 0; +} + +/** + * qcom_prep_bam_dma_desc_data() - Prepares the data descriptor for BAM DMA + * @nandc: qpic nand controller + * @read: read or write type + * @vaddr: virtual address of the buffer we want to write to + * @size: DMA transaction size in bytes + * @flags: flags to control DMA descriptor preparation + * + * This function will prepares the data descriptor for BAM DMA which + * will be used for NAND data reads and writes. + */ +int qcom_prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool r= ead, + const void *vaddr, int size, unsigned int flags) +{ + int ret; + struct bam_transaction *bam_txn =3D nandc->bam_txn; + + if (read) { + sg_set_buf(&bam_txn->data_sgl[bam_txn->rx_sgl_pos], + vaddr, size); + bam_txn->rx_sgl_pos++; + } else { + sg_set_buf(&bam_txn->data_sgl[bam_txn->tx_sgl_pos], + vaddr, size); + bam_txn->tx_sgl_pos++; + + /* + * BAM will only set EOT for DMA_PREP_INTERRUPT so if this flag + * is not set, form the DMA descriptor + */ + if (!(flags & NAND_BAM_NO_EOT)) { + ret =3D qcom_prepare_bam_async_desc(nandc, nandc->tx_chan, + DMA_PREP_INTERRUPT); + if (ret) + return ret; + } + } + + return 0; +} + +/** + * qcom_prep_adm_dma_desc() - Prepare descriptor for adma + * @nandc: qpic nand controller + * @read: read or write type + * @reg_off: offset within the controller's data buffer + * @vaddr: virtual address of the buffer we want to write to + * @size: adm dma transaction size in bytes + * @flow_control: flow controller + * + * This function will prepare descriptor for adma + */ +int qcom_prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read, + int reg_off, const void *vaddr, int size, + bool flow_control) +{ + struct qcom_adm_peripheral_config periph_conf =3D {}; + struct dma_async_tx_descriptor *dma_desc; + struct dma_slave_config slave_conf =3D {0}; + enum dma_transfer_direction dir_eng; + struct desc_info *desc; + struct scatterlist *sgl; + int ret; + + desc =3D kzalloc(sizeof(*desc), GFP_KERNEL); + if (!desc) + return -ENOMEM; + + sgl =3D &desc->adm_sgl; + + sg_init_one(sgl, vaddr, size); + + if (read) { + dir_eng =3D DMA_DEV_TO_MEM; + desc->dir =3D DMA_FROM_DEVICE; + } else { + dir_eng =3D DMA_MEM_TO_DEV; + desc->dir =3D DMA_TO_DEVICE; + } + + ret =3D dma_map_sg(nandc->dev, sgl, 1, desc->dir); + if (!ret) { + ret =3D -ENOMEM; + goto err; + } + + slave_conf.device_fc =3D flow_control; + if (read) { + slave_conf.src_maxburst =3D 16; + slave_conf.src_addr =3D nandc->base_dma + reg_off; + if (nandc->data_crci) { + periph_conf.crci =3D nandc->data_crci; + slave_conf.peripheral_config =3D &periph_conf; + slave_conf.peripheral_size =3D sizeof(periph_conf); + } + } else { + slave_conf.dst_maxburst =3D 16; + slave_conf.dst_addr =3D nandc->base_dma + reg_off; + if (nandc->cmd_crci) { + periph_conf.crci =3D nandc->cmd_crci; + slave_conf.peripheral_config =3D &periph_conf; + slave_conf.peripheral_size =3D sizeof(periph_conf); + } + } + + ret =3D dmaengine_slave_config(nandc->chan, &slave_conf); + if (ret) { + dev_err(nandc->dev, "failed to configure dma channel\n"); + goto err; + } + + dma_desc =3D dmaengine_prep_slave_sg(nandc->chan, sgl, 1, dir_eng, 0); + if (!dma_desc) { + dev_err(nandc->dev, "failed to prepare desc\n"); + ret =3D -EINVAL; + goto err; + } + + desc->dma_desc =3D dma_desc; + + list_add_tail(&desc->node, &nandc->desc_list); + + return 0; +err: + kfree(desc); + + return ret; +} + +/** + * qcom_read_reg_dma() - read a given number of registers to the reg_read_= buf pointer + * @nandc: qpic nand controller + * @first: offset of the first register in the contiguous block + * @num_regs: number of registers to read + * @flags: flags to control DMA descriptor preparation + * + * This function will prepares a descriptor to read a given number of + * contiguous registers to the reg_read_buf pointer. + */ +int qcom_read_reg_dma(struct qcom_nand_controller *nandc, int first, + int num_regs, unsigned int flags) +{ + bool flow_control =3D false; + void *vaddr; + + vaddr =3D nandc->reg_read_buf + nandc->reg_read_pos; + nandc->reg_read_pos +=3D num_regs; + + if (first =3D=3D NAND_DEV_CMD_VLD || first =3D=3D NAND_DEV_CMD1) + first =3D dev_cmd_reg_addr(nandc, first); + + if (nandc->props->supports_bam) + return qcom_prep_bam_dma_desc_cmd(nandc, true, first, vaddr, + num_regs, flags); + + if (first =3D=3D NAND_READ_ID || first =3D=3D NAND_FLASH_STATUS) + flow_control =3D true; + + return qcom_prep_adm_dma_desc(nandc, true, first, vaddr, + num_regs * sizeof(u32), flow_control); +} + +/** + * qcom_write_reg_dma() - write a given number of registers + * @nandc: qpic nand controller + * @vaddr: contnigeous memory from where register value will + * be written + * @first: offset of the first register in the contiguous block + * @num_regs: number of registers to write + * @flags: flags to control DMA descriptor preparation + * + * This function will prepares a descriptor to write a given number of + * contiguous registers + */ +int qcom_write_reg_dma(struct qcom_nand_controller *nandc, __le32 *vaddr, + int first, int num_regs, unsigned int flags) +{ + bool flow_control =3D false; + + if (first =3D=3D NAND_EXEC_CMD) + flags |=3D NAND_BAM_NWD; + + if (first =3D=3D NAND_DEV_CMD1_RESTORE || first =3D=3D NAND_DEV_CMD1) + first =3D dev_cmd_reg_addr(nandc, NAND_DEV_CMD1); + + if (first =3D=3D NAND_DEV_CMD_VLD_RESTORE || first =3D=3D NAND_DEV_CMD_VL= D) + first =3D dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD); + + if (nandc->props->supports_bam) + return qcom_prep_bam_dma_desc_cmd(nandc, false, first, vaddr, + num_regs, flags); + + if (first =3D=3D NAND_FLASH_CMD) + flow_control =3D true; + + return qcom_prep_adm_dma_desc(nandc, false, first, vaddr, + num_regs * sizeof(u32), flow_control); +} + +/** + * qcom_read_data_dma() - transfer data + * @nandc: qpic nand controller + * @reg_off: offset within the controller's data buffer + * @vaddr: virtual address of the buffer we want to write to + * @size: DMA transaction size in bytes + * @flags: flags to control DMA descriptor preparation + * + * This function will prepares a DMA descriptor to transfer data from the + * controller's internal buffer to the buffer 'vaddr' + */ +int qcom_read_data_dma(struct qcom_nand_controller *nandc, int reg_off, + const u8 *vaddr, int size, unsigned int flags) +{ + if (nandc->props->supports_bam) + return qcom_prep_bam_dma_desc_data(nandc, true, vaddr, size, flags); + + return qcom_prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false); +} + +/** + * qcom_write_data_dma() - transfer data + * @nandc: qpic nand controller + * @reg_off: offset within the controller's data buffer + * @vaddr: virtual address of the buffer we want to read from + * @size: DMA transaction size in bytes + * @flags: flags to control DMA descriptor preparation + * + * This function will prepares a DMA descriptor to transfer data from + * 'vaddr' to the controller's internal buffer + */ +int qcom_write_data_dma(struct qcom_nand_controller *nandc, int reg_off, + const u8 *vaddr, int size, unsigned int flags) +{ + if (nandc->props->supports_bam) + return qcom_prep_bam_dma_desc_data(nandc, false, vaddr, size, flags); + + return qcom_prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false); +} + +/** + * qcom_submit_descs() - submit dma descriptor + * @nandc: qpic nand controller + * + * This function will submit all the prepared dma descriptor + * cmd or data descriptor + */ +int qcom_submit_descs(struct qcom_nand_controller *nandc) +{ + struct desc_info *desc, *n; + dma_cookie_t cookie =3D 0; + struct bam_transaction *bam_txn =3D nandc->bam_txn; + int ret =3D 0; + + if (nandc->props->supports_bam) { + if (bam_txn->rx_sgl_pos > bam_txn->rx_sgl_start) { + ret =3D qcom_prepare_bam_async_desc(nandc, nandc->rx_chan, 0); + if (ret) + goto err_unmap_free_desc; + } + + if (bam_txn->tx_sgl_pos > bam_txn->tx_sgl_start) { + ret =3D qcom_prepare_bam_async_desc(nandc, nandc->tx_chan, + DMA_PREP_INTERRUPT); + if (ret) + goto err_unmap_free_desc; + } + + if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) { + ret =3D qcom_prepare_bam_async_desc(nandc, nandc->cmd_chan, + DMA_PREP_CMD); + if (ret) + goto err_unmap_free_desc; + } + } + + list_for_each_entry(desc, &nandc->desc_list, node) + cookie =3D dmaengine_submit(desc->dma_desc); + + if (nandc->props->supports_bam) { + bam_txn->last_cmd_desc->callback =3D qcom_qpic_bam_dma_done; + bam_txn->last_cmd_desc->callback_param =3D bam_txn; + + dma_async_issue_pending(nandc->tx_chan); + dma_async_issue_pending(nandc->rx_chan); + dma_async_issue_pending(nandc->cmd_chan); + + if (!wait_for_completion_timeout(&bam_txn->txn_done, + QPIC_NAND_COMPLETION_TIMEOUT)) + ret =3D -ETIMEDOUT; + } else { + if (dma_sync_wait(nandc->chan, cookie) !=3D DMA_COMPLETE) + ret =3D -ETIMEDOUT; + } + +err_unmap_free_desc: + /* + * Unmap the dma sg_list and free the desc allocated by both + * qcom_prepare_bam_async_desc() and qcom_prep_adm_dma_desc() functions. + */ + list_for_each_entry_safe(desc, n, &nandc->desc_list, node) { + list_del(&desc->node); + + if (nandc->props->supports_bam) + dma_unmap_sg(nandc->dev, desc->bam_sgl, + desc->sgl_cnt, desc->dir); + else + dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1, + desc->dir); + + kfree(desc); + } + + return ret; +} + +/** + * qcom_clear_read_regs() - reset the read register buffer + * @nandc: qpic nand controller + * + * This function reset the register read buffer for next NAND operation + */ +void qcom_clear_read_regs(struct qcom_nand_controller *nandc) +{ + nandc->reg_read_pos =3D 0; + qcom_nandc_dev_to_mem(nandc, false); +} + +/** + * qcom_nandc_unalloc() - unallocate qpic nand controller + * @nandc: qpic nand controller + * + * This function will unallocate memory alloacted for qpic nand controller + */ +void qcom_nandc_unalloc(struct qcom_nand_controller *nandc) +{ + if (nandc->props->supports_bam) { + if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma)) + dma_unmap_single(nandc->dev, nandc->reg_read_dma, + MAX_REG_RD * + sizeof(*nandc->reg_read_buf), + DMA_FROM_DEVICE); + + if (nandc->tx_chan) + dma_release_channel(nandc->tx_chan); + + if (nandc->rx_chan) + dma_release_channel(nandc->rx_chan); + + if (nandc->cmd_chan) + dma_release_channel(nandc->cmd_chan); + } else { + if (nandc->chan) + dma_release_channel(nandc->chan); + } +} + +/** + * qcom_nandc_alloc() - Allocate qpic nand controller + * @nandc: qpic nand controller + * + * This function will allocate memory for qpic nand controller + */ +int qcom_nandc_alloc(struct qcom_nand_controller *nandc) +{ + int ret; + + ret =3D dma_set_coherent_mask(nandc->dev, DMA_BIT_MASK(32)); + if (ret) { + dev_err(nandc->dev, "failed to set DMA mask\n"); + return ret; + } + + /* + * we use the internal buffer for reading ONFI params, reading small + * data like ID and status, and preforming read-copy-write operations + * when writing to a codeword partially. 532 is the maximum possible + * size of a codeword for our nand controller + */ + nandc->buf_size =3D 532; + + nandc->data_buffer =3D devm_kzalloc(nandc->dev, nandc->buf_size, GFP_KERN= EL); + if (!nandc->data_buffer) + return -ENOMEM; + + nandc->regs =3D devm_kzalloc(nandc->dev, sizeof(*nandc->regs), GFP_KERNEL= ); + if (!nandc->regs) + return -ENOMEM; + + nandc->reg_read_buf =3D devm_kcalloc(nandc->dev, MAX_REG_RD, + sizeof(*nandc->reg_read_buf), + GFP_KERNEL); + if (!nandc->reg_read_buf) + return -ENOMEM; + + if (nandc->props->supports_bam) { + nandc->reg_read_dma =3D + dma_map_single(nandc->dev, nandc->reg_read_buf, + MAX_REG_RD * + sizeof(*nandc->reg_read_buf), + DMA_FROM_DEVICE); + if (dma_mapping_error(nandc->dev, nandc->reg_read_dma)) { + dev_err(nandc->dev, "failed to DMA MAP reg buffer\n"); + return -EIO; + } + + nandc->tx_chan =3D dma_request_chan(nandc->dev, "tx"); + if (IS_ERR(nandc->tx_chan)) { + ret =3D PTR_ERR(nandc->tx_chan); + nandc->tx_chan =3D NULL; + dev_err_probe(nandc->dev, ret, + "tx DMA channel request failed\n"); + goto unalloc; + } + + nandc->rx_chan =3D dma_request_chan(nandc->dev, "rx"); + if (IS_ERR(nandc->rx_chan)) { + ret =3D PTR_ERR(nandc->rx_chan); + nandc->rx_chan =3D NULL; + dev_err_probe(nandc->dev, ret, + "rx DMA channel request failed\n"); + goto unalloc; + } + + nandc->cmd_chan =3D dma_request_chan(nandc->dev, "cmd"); + if (IS_ERR(nandc->cmd_chan)) { + ret =3D PTR_ERR(nandc->cmd_chan); + nandc->cmd_chan =3D NULL; + dev_err_probe(nandc->dev, ret, + "cmd DMA channel request failed\n"); + goto unalloc; + } + + /* + * Initially allocate BAM transaction to read ONFI param page. + * After detecting all the devices, this BAM transaction will + * be freed and the next BAM transaction will be allocated with + * maximum codeword size + */ + nandc->max_cwperpage =3D 1; + nandc->bam_txn =3D qcom_alloc_bam_transaction(nandc); + if (!nandc->bam_txn) { + dev_err(nandc->dev, + "failed to allocate bam transaction\n"); + ret =3D -ENOMEM; + goto unalloc; + } + } else { + nandc->chan =3D dma_request_chan(nandc->dev, "rxtx"); + if (IS_ERR(nandc->chan)) { + ret =3D PTR_ERR(nandc->chan); + nandc->chan =3D NULL; + dev_err_probe(nandc->dev, ret, + "rxtx DMA channel request failed\n"); + return ret; + } + } + + INIT_LIST_HEAD(&nandc->desc_list); + INIT_LIST_HEAD(&nandc->host_list); + + return 0; +unalloc: + qcom_nandc_unalloc(nandc); + return ret; +} diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 614257308516..54c6fe98189e 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -330,7 +330,7 @@ config MTD_NAND_HISI504 Enables support for NAND controller on Hisilicon SoC Hip04. =20 config MTD_NAND_QCOM - tristate "QCOM NAND controller" + bool "QCOM NAND controller" depends on ARCH_QCOM || COMPILE_TEST depends on HAS_IOMEM help diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_= nandc.c index daf8f73b25bc..91f1eb781cb2 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -15,417 +15,7 @@ #include #include #include - -/* NANDc reg offsets */ -#define NAND_FLASH_CMD 0x00 -#define NAND_ADDR0 0x04 -#define NAND_ADDR1 0x08 -#define NAND_FLASH_CHIP_SELECT 0x0c -#define NAND_EXEC_CMD 0x10 -#define NAND_FLASH_STATUS 0x14 -#define NAND_BUFFER_STATUS 0x18 -#define NAND_DEV0_CFG0 0x20 -#define NAND_DEV0_CFG1 0x24 -#define NAND_DEV0_ECC_CFG 0x28 -#define NAND_AUTO_STATUS_EN 0x2c -#define NAND_DEV1_CFG0 0x30 -#define NAND_DEV1_CFG1 0x34 -#define NAND_READ_ID 0x40 -#define NAND_READ_STATUS 0x44 -#define NAND_DEV_CMD0 0xa0 -#define NAND_DEV_CMD1 0xa4 -#define NAND_DEV_CMD2 0xa8 -#define NAND_DEV_CMD_VLD 0xac -#define SFLASHC_BURST_CFG 0xe0 -#define NAND_ERASED_CW_DETECT_CFG 0xe8 -#define NAND_ERASED_CW_DETECT_STATUS 0xec -#define NAND_EBI2_ECC_BUF_CFG 0xf0 -#define FLASH_BUF_ACC 0x100 - -#define NAND_CTRL 0xf00 -#define NAND_VERSION 0xf08 -#define NAND_READ_LOCATION_0 0xf20 -#define NAND_READ_LOCATION_1 0xf24 -#define NAND_READ_LOCATION_2 0xf28 -#define NAND_READ_LOCATION_3 0xf2c -#define NAND_READ_LOCATION_LAST_CW_0 0xf40 -#define NAND_READ_LOCATION_LAST_CW_1 0xf44 -#define NAND_READ_LOCATION_LAST_CW_2 0xf48 -#define NAND_READ_LOCATION_LAST_CW_3 0xf4c - -/* dummy register offsets, used by qcom_write_reg_dma */ -#define NAND_DEV_CMD1_RESTORE 0xdead -#define NAND_DEV_CMD_VLD_RESTORE 0xbeef - -/* NAND_FLASH_CMD bits */ -#define PAGE_ACC BIT(4) -#define LAST_PAGE BIT(5) - -/* NAND_FLASH_CHIP_SELECT bits */ -#define NAND_DEV_SEL 0 -#define DM_EN BIT(2) - -/* NAND_FLASH_STATUS bits */ -#define FS_OP_ERR BIT(4) -#define FS_READY_BSY_N BIT(5) -#define FS_MPU_ERR BIT(8) -#define FS_DEVICE_STS_ERR BIT(16) -#define FS_DEVICE_WP BIT(23) - -/* NAND_BUFFER_STATUS bits */ -#define BS_UNCORRECTABLE_BIT BIT(8) -#define BS_CORRECTABLE_ERR_MSK 0x1f - -/* NAND_DEVn_CFG0 bits */ -#define DISABLE_STATUS_AFTER_WRITE 4 -#define CW_PER_PAGE 6 -#define UD_SIZE_BYTES 9 -#define UD_SIZE_BYTES_MASK GENMASK(18, 9) -#define ECC_PARITY_SIZE_BYTES_RS 19 -#define SPARE_SIZE_BYTES 23 -#define SPARE_SIZE_BYTES_MASK GENMASK(26, 23) -#define NUM_ADDR_CYCLES 27 -#define STATUS_BFR_READ 30 -#define SET_RD_MODE_AFTER_STATUS 31 - -/* NAND_DEVn_CFG0 bits */ -#define DEV0_CFG1_ECC_DISABLE 0 -#define WIDE_FLASH 1 -#define NAND_RECOVERY_CYCLES 2 -#define CS_ACTIVE_BSY 5 -#define BAD_BLOCK_BYTE_NUM 6 -#define BAD_BLOCK_IN_SPARE_AREA 16 -#define WR_RD_BSY_GAP 17 -#define ENABLE_BCH_ECC 27 - -/* NAND_DEV0_ECC_CFG bits */ -#define ECC_CFG_ECC_DISABLE 0 -#define ECC_SW_RESET 1 -#define ECC_MODE 4 -#define ECC_PARITY_SIZE_BYTES_BCH 8 -#define ECC_NUM_DATA_BYTES 16 -#define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16) -#define ECC_FORCE_CLK_OPEN 30 - -/* NAND_DEV_CMD1 bits */ -#define READ_ADDR 0 - -/* NAND_DEV_CMD_VLD bits */ -#define READ_START_VLD BIT(0) -#define READ_STOP_VLD BIT(1) -#define WRITE_START_VLD BIT(2) -#define ERASE_START_VLD BIT(3) -#define SEQ_READ_START_VLD BIT(4) - -/* NAND_EBI2_ECC_BUF_CFG bits */ -#define NUM_STEPS 0 - -/* NAND_ERASED_CW_DETECT_CFG bits */ -#define ERASED_CW_ECC_MASK 1 -#define AUTO_DETECT_RES 0 -#define MASK_ECC BIT(ERASED_CW_ECC_MASK) -#define RESET_ERASED_DET BIT(AUTO_DETECT_RES) -#define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES) -#define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC) -#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC) - -/* NAND_ERASED_CW_DETECT_STATUS bits */ -#define PAGE_ALL_ERASED BIT(7) -#define CODEWORD_ALL_ERASED BIT(6) -#define PAGE_ERASED BIT(5) -#define CODEWORD_ERASED BIT(4) -#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED) -#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED) - -/* NAND_READ_LOCATION_n bits */ -#define READ_LOCATION_OFFSET 0 -#define READ_LOCATION_SIZE 16 -#define READ_LOCATION_LAST 31 - -/* Version Mask */ -#define NAND_VERSION_MAJOR_MASK 0xf0000000 -#define NAND_VERSION_MAJOR_SHIFT 28 -#define NAND_VERSION_MINOR_MASK 0x0fff0000 -#define NAND_VERSION_MINOR_SHIFT 16 - -/* NAND OP_CMDs */ -#define OP_PAGE_READ 0x2 -#define OP_PAGE_READ_WITH_ECC 0x3 -#define OP_PAGE_READ_WITH_ECC_SPARE 0x4 -#define OP_PAGE_READ_ONFI_READ 0x5 -#define OP_PROGRAM_PAGE 0x6 -#define OP_PAGE_PROGRAM_WITH_ECC 0x7 -#define OP_PROGRAM_PAGE_SPARE 0x9 -#define OP_BLOCK_ERASE 0xa -#define OP_CHECK_STATUS 0xc -#define OP_FETCH_ID 0xb -#define OP_RESET_DEVICE 0xd - -/* Default Value for NAND_DEV_CMD_VLD */ -#define NAND_DEV_CMD_VLD_VAL (READ_START_VLD | WRITE_START_VLD | \ - ERASE_START_VLD | SEQ_READ_START_VLD) - -/* NAND_CTRL bits */ -#define BAM_MODE_EN BIT(0) - -/* - * the NAND controller performs reads/writes with ECC in 516 byte chunks. - * the driver calls the chunks 'step' or 'codeword' interchangeably - */ -#define NANDC_STEP_SIZE 512 - -/* - * the largest page size we support is 8K, this will have 16 steps/codewor= ds - * of 512 bytes each - */ -#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE) - -/* we read at most 3 registers per codeword scan */ -#define MAX_REG_RD (3 * MAX_NUM_STEPS) - -/* ECC modes supported by the controller */ -#define ECC_NONE BIT(0) -#define ECC_RS_4BIT BIT(1) -#define ECC_BCH_4BIT BIT(2) -#define ECC_BCH_8BIT BIT(3) - -/* - * Returns the actual register address for all NAND_DEV_ registers - * (i.e. NAND_DEV_CMD0, NAND_DEV_CMD1, NAND_DEV_CMD2 and NAND_DEV_CMD_VLD) - */ -#define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + = (reg)) - -/* Returns the NAND register physical address */ -#define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset)) - -/* Returns the dma address for reg read buffer */ -#define reg_buf_dma_addr(chip, vaddr) \ - ((chip)->reg_read_dma + \ - ((u8 *)(vaddr) - (u8 *)(chip)->reg_read_buf)) - -#define QPIC_PER_CW_CMD_ELEMENTS 32 -#define QPIC_PER_CW_CMD_SGL 32 -#define QPIC_PER_CW_DATA_SGL 8 - -#define QPIC_NAND_COMPLETION_TIMEOUT msecs_to_jiffies(2000) - -/* - * Flags used in DMA descriptor preparation helper functions - * (i.e. qcom_read_reg_dma/qcom_write_reg_dma/qcom_read_data_dma/qcom_writ= e_data_dma) - */ -/* Don't set the EOT in current tx BAM sgl */ -#define NAND_BAM_NO_EOT BIT(0) -/* Set the NWD flag in current BAM sgl */ -#define NAND_BAM_NWD BIT(1) -/* Finish writing in the current BAM sgl and start writing in another BAM = sgl */ -#define NAND_BAM_NEXT_SGL BIT(2) -/* - * Erased codeword status is being used two times in single transfer so th= is - * flag will determine the current value of erased codeword status register - */ -#define NAND_ERASED_CW_SET BIT(4) - -#define MAX_ADDRESS_CYCLE 5 - -/* - * This data type corresponds to the BAM transaction which will be used fo= r all - * NAND transfers. - * @bam_ce - the array of BAM command elements - * @cmd_sgl - sgl for NAND BAM command pipe - * @data_sgl - sgl for NAND BAM consumer/producer pipe - * @last_data_desc - last DMA desc in data channel (tx/rx). - * @last_cmd_desc - last DMA desc in command channel. - * @txn_done - completion for NAND transfer. - * @bam_ce_pos - the index in bam_ce which is available for next sgl - * @bam_ce_start - the index in bam_ce which marks the start position ce - * for current sgl. It will be used for size calculation - * for current sgl - * @cmd_sgl_pos - current index in command sgl. - * @cmd_sgl_start - start index in command sgl. - * @tx_sgl_pos - current index in data sgl for tx. - * @tx_sgl_start - start index in data sgl for tx. - * @rx_sgl_pos - current index in data sgl for rx. - * @rx_sgl_start - start index in data sgl for rx. - */ -struct bam_transaction { - struct bam_cmd_element *bam_ce; - struct scatterlist *cmd_sgl; - struct scatterlist *data_sgl; - struct dma_async_tx_descriptor *last_data_desc; - struct dma_async_tx_descriptor *last_cmd_desc; - struct completion txn_done; - u32 bam_ce_pos; - u32 bam_ce_start; - u32 cmd_sgl_pos; - u32 cmd_sgl_start; - u32 tx_sgl_pos; - u32 tx_sgl_start; - u32 rx_sgl_pos; - u32 rx_sgl_start; -}; - -/* - * This data type corresponds to the nand dma descriptor - * @dma_desc - low level DMA engine descriptor - * @list - list for desc_info - * - * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only u= sed by - * ADM - * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM - * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM - * @dir - DMA transfer direction - */ -struct desc_info { - struct dma_async_tx_descriptor *dma_desc; - struct list_head node; - - union { - struct scatterlist adm_sgl; - struct { - struct scatterlist *bam_sgl; - int sgl_cnt; - }; - }; - enum dma_data_direction dir; -}; - -/* - * holds the current register values that we want to write. acts as a cont= iguous - * chunk of memory which we use to write the controller registers through = DMA. - */ -struct nandc_regs { - __le32 cmd; - __le32 addr0; - __le32 addr1; - __le32 chip_sel; - __le32 exec; - - __le32 cfg0; - __le32 cfg1; - __le32 ecc_bch_cfg; - - __le32 clrflashstatus; - __le32 clrreadstatus; - - __le32 cmd1; - __le32 vld; - - __le32 orig_cmd1; - __le32 orig_vld; - - __le32 ecc_buf_cfg; - __le32 read_location0; - __le32 read_location1; - __le32 read_location2; - __le32 read_location3; - __le32 read_location_last0; - __le32 read_location_last1; - __le32 read_location_last2; - __le32 read_location_last3; - - __le32 erased_cw_detect_cfg_clr; - __le32 erased_cw_detect_cfg_set; -}; - -/* - * NAND controller data struct - * - * @dev: parent device - * - * @base: MMIO base - * - * @core_clk: controller clock - * @aon_clk: another controller clock - * - * @regs: a contiguous chunk of memory for DMA register - * writes. contains the register values to be - * written to controller - * - * @props: properties of current NAND controller, - * initialized via DT match data - * - * @controller: base controller structure - * @host_list: list containing all the chips attached to the - * controller - * - * @chan: dma channel - * @cmd_crci: ADM DMA CRCI for command flow control - * @data_crci: ADM DMA CRCI for data flow control - * - * @desc_list: DMA descriptor list (list of desc_infos) - * - * @data_buffer: our local DMA buffer for page read/writes, - * used when we can't use the buffer provided - * by upper layers directly - * @reg_read_buf: local buffer for reading back registers via DMA - * - * @base_phys: physical base address of controller registers - * @base_dma: dma base address of controller registers - * @reg_read_dma: contains dma address for register read buffer - * - * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf - * functions - * @max_cwperpage: maximum QPIC codewords required. calculated - * from all connected NAND devices pagesize - * - * @reg_read_pos: marker for data read in reg_read_buf - * - * @cmd1/vld: some fixed controller register values - * - * @exec_opwrite: flag to select correct number of code word - * while reading status - */ -struct qcom_nand_controller { - struct device *dev; - - void __iomem *base; - - struct clk *core_clk; - struct clk *aon_clk; - - struct nandc_regs *regs; - struct bam_transaction *bam_txn; - - const struct qcom_nandc_props *props; - - struct nand_controller controller; - struct list_head host_list; - - union { - /* will be used only by QPIC for BAM DMA */ - struct { - struct dma_chan *tx_chan; - struct dma_chan *rx_chan; - struct dma_chan *cmd_chan; - }; - - /* will be used only by EBI2 for ADM DMA */ - struct { - struct dma_chan *chan; - unsigned int cmd_crci; - unsigned int data_crci; - }; - }; - - struct list_head desc_list; - - u8 *data_buffer; - __le32 *reg_read_buf; - - phys_addr_t base_phys; - dma_addr_t base_dma; - dma_addr_t reg_read_dma; - - int buf_size; - int buf_count; - int buf_start; - unsigned int max_cwperpage; - - int reg_read_pos; - - u32 cmd1, vld; - bool exec_opwrite; -}; +#include =20 /* * NAND special boot partitions @@ -530,97 +120,6 @@ struct qcom_nand_host { bool bch_enabled; }; =20 -/* - * This data type corresponds to the NAND controller properties which vari= es - * among different NAND controllers. - * @ecc_modes - ecc mode for NAND - * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset - * @supports_bam - whether NAND controller is using BAM - * @nandc_part_of_qpic - whether NAND controller is part of qpic IP - * @qpic_version2 - flag to indicate QPIC IP version 2 - * @use_codeword_fixup - whether NAND has different layout for boot partit= ions - */ -struct qcom_nandc_props { - u32 ecc_modes; - u32 dev_cmd_reg_start; - bool supports_bam; - bool nandc_part_of_qpic; - bool qpic_version2; - bool use_codeword_fixup; -}; - -/* Frees the BAM transaction memory */ -static void qcom_free_bam_transaction(struct qcom_nand_controller *nandc) -{ - struct bam_transaction *bam_txn =3D nandc->bam_txn; - - devm_kfree(nandc->dev, bam_txn); -} - -/* Allocates and Initializes the BAM transaction */ -static struct bam_transaction * -qcom_alloc_bam_transaction(struct qcom_nand_controller *nandc) -{ - struct bam_transaction *bam_txn; - size_t bam_txn_size; - unsigned int num_cw =3D nandc->max_cwperpage; - void *bam_txn_buf; - - bam_txn_size =3D - sizeof(*bam_txn) + num_cw * - ((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) + - (sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) + - (sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL)); - - bam_txn_buf =3D devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL); - if (!bam_txn_buf) - return NULL; - - bam_txn =3D bam_txn_buf; - bam_txn_buf +=3D sizeof(*bam_txn); - - bam_txn->bam_ce =3D bam_txn_buf; - bam_txn_buf +=3D - sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS * num_cw; - - bam_txn->cmd_sgl =3D bam_txn_buf; - bam_txn_buf +=3D - sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL * num_cw; - - bam_txn->data_sgl =3D bam_txn_buf; - - init_completion(&bam_txn->txn_done); - - return bam_txn; -} - -/* Clears the BAM transaction indexes */ -static void qcom_clear_bam_transaction(struct qcom_nand_controller *nandc) -{ - struct bam_transaction *bam_txn =3D nandc->bam_txn; - - if (!nandc->props->supports_bam) - return; - - memset(&bam_txn->bam_ce_pos, 0, sizeof(u32) * 8); - bam_txn->last_data_desc =3D NULL; - - sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage * - QPIC_PER_CW_CMD_SGL); - sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage * - QPIC_PER_CW_DATA_SGL); - - reinit_completion(&bam_txn->txn_done); -} - -/* Callback for DMA descriptor completion */ -static void qcom_qpic_bam_dma_done(void *data) -{ - struct bam_transaction *bam_txn =3D data; - - complete(&bam_txn->txn_done); -} - static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *c= hip) { return container_of(chip, struct qcom_nand_host, chip); @@ -629,8 +128,8 @@ static inline struct qcom_nand_host *to_qcom_nand_host(= struct nand_chip *chip) static inline struct qcom_nand_controller * get_qcom_nand_controller(struct nand_chip *chip) { - return container_of(chip->controller, struct qcom_nand_controller, - controller); + return (struct qcom_nand_controller *) + ((u8 *)chip->controller - sizeof(struct qcom_nand_controller)); } =20 static inline u32 nandc_read(struct qcom_nand_controller *nandc, int offse= t) @@ -644,23 +143,6 @@ static inline void nandc_write(struct qcom_nand_contro= ller *nandc, int offset, iowrite32(val, nandc->base + offset); } =20 -static inline void qcom_nandc_dev_to_mem(struct qcom_nand_controller *nand= c, bool is_cpu) -{ - if (!nandc->props->supports_bam) - return; - - if (is_cpu) - dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_dma, - MAX_REG_RD * - sizeof(*nandc->reg_read_buf), - DMA_FROM_DEVICE); - else - dma_sync_single_for_device(nandc->dev, nandc->reg_read_dma, - MAX_REG_RD * - sizeof(*nandc->reg_read_buf), - DMA_FROM_DEVICE); -} - /* Helper to check the code word, whether it is last cw or not */ static bool qcom_nandc_is_last_cw(struct nand_ecc_ctrl *ecc, int cw) { @@ -819,356 +301,6 @@ static void update_rw_regs(struct qcom_nand_host *hos= t, int num_cw, bool read, i host->cw_data : host->cw_size, 1); } =20 -/* - * Maps the scatter gather list for DMA transfer and forms the DMA descrip= tor - * for BAM. This descriptor will be added in the NAND DMA descriptor queue - * which will be submitted to DMA engine. - */ -static int qcom_prepare_bam_async_desc(struct qcom_nand_controller *nandc, - struct dma_chan *chan, - unsigned long flags) -{ - struct desc_info *desc; - struct scatterlist *sgl; - unsigned int sgl_cnt; - int ret; - struct bam_transaction *bam_txn =3D nandc->bam_txn; - enum dma_transfer_direction dir_eng; - struct dma_async_tx_descriptor *dma_desc; - - desc =3D kzalloc(sizeof(*desc), GFP_KERNEL); - if (!desc) - return -ENOMEM; - - if (chan =3D=3D nandc->cmd_chan) { - sgl =3D &bam_txn->cmd_sgl[bam_txn->cmd_sgl_start]; - sgl_cnt =3D bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start; - bam_txn->cmd_sgl_start =3D bam_txn->cmd_sgl_pos; - dir_eng =3D DMA_MEM_TO_DEV; - desc->dir =3D DMA_TO_DEVICE; - } else if (chan =3D=3D nandc->tx_chan) { - sgl =3D &bam_txn->data_sgl[bam_txn->tx_sgl_start]; - sgl_cnt =3D bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start; - bam_txn->tx_sgl_start =3D bam_txn->tx_sgl_pos; - dir_eng =3D DMA_MEM_TO_DEV; - desc->dir =3D DMA_TO_DEVICE; - } else { - sgl =3D &bam_txn->data_sgl[bam_txn->rx_sgl_start]; - sgl_cnt =3D bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start; - bam_txn->rx_sgl_start =3D bam_txn->rx_sgl_pos; - dir_eng =3D DMA_DEV_TO_MEM; - desc->dir =3D DMA_FROM_DEVICE; - } - - sg_mark_end(sgl + sgl_cnt - 1); - ret =3D dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir); - if (ret =3D=3D 0) { - dev_err(nandc->dev, "failure in mapping desc\n"); - kfree(desc); - return -ENOMEM; - } - - desc->sgl_cnt =3D sgl_cnt; - desc->bam_sgl =3D sgl; - - dma_desc =3D dmaengine_prep_slave_sg(chan, sgl, sgl_cnt, dir_eng, - flags); - - if (!dma_desc) { - dev_err(nandc->dev, "failure in prep desc\n"); - dma_unmap_sg(nandc->dev, sgl, sgl_cnt, desc->dir); - kfree(desc); - return -EINVAL; - } - - desc->dma_desc =3D dma_desc; - - /* update last data/command descriptor */ - if (chan =3D=3D nandc->cmd_chan) - bam_txn->last_cmd_desc =3D dma_desc; - else - bam_txn->last_data_desc =3D dma_desc; - - list_add_tail(&desc->node, &nandc->desc_list); - - return 0; -} - -/* - * Prepares the command descriptor for BAM DMA which will be used for NAND - * register reads and writes. The command descriptor requires the command - * to be formed in command element type so this function uses the command - * element from bam transaction ce array and fills the same with required - * data. A single SGL can contain multiple command elements so - * NAND_BAM_NEXT_SGL will be used for starting the separate SGL - * after the current command element. - */ -static int qcom_prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, = bool read, - int reg_off, const void *vaddr, - int size, unsigned int flags) -{ - int bam_ce_size; - int i, ret; - struct bam_cmd_element *bam_ce_buffer; - struct bam_transaction *bam_txn =3D nandc->bam_txn; - - bam_ce_buffer =3D &bam_txn->bam_ce[bam_txn->bam_ce_pos]; - - /* fill the command desc */ - for (i =3D 0; i < size; i++) { - if (read) - bam_prep_ce(&bam_ce_buffer[i], - nandc_reg_phys(nandc, reg_off + 4 * i), - BAM_READ_COMMAND, - reg_buf_dma_addr(nandc, - (__le32 *)vaddr + i)); - else - bam_prep_ce_le32(&bam_ce_buffer[i], - nandc_reg_phys(nandc, reg_off + 4 * i), - BAM_WRITE_COMMAND, - *((__le32 *)vaddr + i)); - } - - bam_txn->bam_ce_pos +=3D size; - - /* use the separate sgl after this command */ - if (flags & NAND_BAM_NEXT_SGL) { - bam_ce_buffer =3D &bam_txn->bam_ce[bam_txn->bam_ce_start]; - bam_ce_size =3D (bam_txn->bam_ce_pos - - bam_txn->bam_ce_start) * - sizeof(struct bam_cmd_element); - sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos], - bam_ce_buffer, bam_ce_size); - bam_txn->cmd_sgl_pos++; - bam_txn->bam_ce_start =3D bam_txn->bam_ce_pos; - - if (flags & NAND_BAM_NWD) { - ret =3D qcom_prepare_bam_async_desc(nandc, nandc->cmd_chan, - DMA_PREP_FENCE | - DMA_PREP_CMD); - if (ret) - return ret; - } - } - - return 0; -} - -/* - * Prepares the data descriptor for BAM DMA which will be used for NAND - * data reads and writes. - */ -static int qcom_prep_bam_dma_desc_data(struct qcom_nand_controller *nandc,= bool read, - const void *vaddr, int size, unsigned int flags) -{ - int ret; - struct bam_transaction *bam_txn =3D nandc->bam_txn; - - if (read) { - sg_set_buf(&bam_txn->data_sgl[bam_txn->rx_sgl_pos], - vaddr, size); - bam_txn->rx_sgl_pos++; - } else { - sg_set_buf(&bam_txn->data_sgl[bam_txn->tx_sgl_pos], - vaddr, size); - bam_txn->tx_sgl_pos++; - - /* - * BAM will only set EOT for DMA_PREP_INTERRUPT so if this flag - * is not set, form the DMA descriptor - */ - if (!(flags & NAND_BAM_NO_EOT)) { - ret =3D qcom_prepare_bam_async_desc(nandc, nandc->tx_chan, - DMA_PREP_INTERRUPT); - if (ret) - return ret; - } - } - - return 0; -} - -static int qcom_prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool= read, - int reg_off, const void *vaddr, int size, - bool flow_control) -{ - struct desc_info *desc; - struct dma_async_tx_descriptor *dma_desc; - struct scatterlist *sgl; - struct dma_slave_config slave_conf; - struct qcom_adm_peripheral_config periph_conf =3D {}; - enum dma_transfer_direction dir_eng; - int ret; - - desc =3D kzalloc(sizeof(*desc), GFP_KERNEL); - if (!desc) - return -ENOMEM; - - sgl =3D &desc->adm_sgl; - - sg_init_one(sgl, vaddr, size); - - if (read) { - dir_eng =3D DMA_DEV_TO_MEM; - desc->dir =3D DMA_FROM_DEVICE; - } else { - dir_eng =3D DMA_MEM_TO_DEV; - desc->dir =3D DMA_TO_DEVICE; - } - - ret =3D dma_map_sg(nandc->dev, sgl, 1, desc->dir); - if (ret =3D=3D 0) { - ret =3D -ENOMEM; - goto err; - } - - memset(&slave_conf, 0x00, sizeof(slave_conf)); - - slave_conf.device_fc =3D flow_control; - if (read) { - slave_conf.src_maxburst =3D 16; - slave_conf.src_addr =3D nandc->base_dma + reg_off; - if (nandc->data_crci) { - periph_conf.crci =3D nandc->data_crci; - slave_conf.peripheral_config =3D &periph_conf; - slave_conf.peripheral_size =3D sizeof(periph_conf); - } - } else { - slave_conf.dst_maxburst =3D 16; - slave_conf.dst_addr =3D nandc->base_dma + reg_off; - if (nandc->cmd_crci) { - periph_conf.crci =3D nandc->cmd_crci; - slave_conf.peripheral_config =3D &periph_conf; - slave_conf.peripheral_size =3D sizeof(periph_conf); - } - } - - ret =3D dmaengine_slave_config(nandc->chan, &slave_conf); - if (ret) { - dev_err(nandc->dev, "failed to configure dma channel\n"); - goto err; - } - - dma_desc =3D dmaengine_prep_slave_sg(nandc->chan, sgl, 1, dir_eng, 0); - if (!dma_desc) { - dev_err(nandc->dev, "failed to prepare desc\n"); - ret =3D -EINVAL; - goto err; - } - - desc->dma_desc =3D dma_desc; - - list_add_tail(&desc->node, &nandc->desc_list); - - return 0; -err: - kfree(desc); - - return ret; -} - -/* - * qcom_read_reg_dma: prepares a descriptor to read a given number of - * contiguous registers to the reg_read_buf pointer - * - * @first: offset of the first register in the contiguous block - * @num_regs: number of registers to read - * @flags: flags to control DMA descriptor preparation - */ -static int qcom_read_reg_dma(struct qcom_nand_controller *nandc, int first, - int num_regs, unsigned int flags) -{ - bool flow_control =3D false; - void *vaddr; - - vaddr =3D nandc->reg_read_buf + nandc->reg_read_pos; - nandc->reg_read_pos +=3D num_regs; - - if (first =3D=3D NAND_DEV_CMD_VLD || first =3D=3D NAND_DEV_CMD1) - first =3D dev_cmd_reg_addr(nandc, first); - - if (nandc->props->supports_bam) - return qcom_prep_bam_dma_desc_cmd(nandc, true, first, vaddr, - num_regs, flags); - - if (first =3D=3D NAND_READ_ID || first =3D=3D NAND_FLASH_STATUS) - flow_control =3D true; - - return qcom_prep_adm_dma_desc(nandc, true, first, vaddr, - num_regs * sizeof(u32), flow_control); -} - -/* - * qcom_write_reg_dma: prepares a descriptor to write a given number of - * contiguous registers - * - * @vaddr: contnigeous memory from where register value will - * be written - * @first: offset of the first register in the contiguous block - * @num_regs: number of registers to write - * @flags: flags to control DMA descriptor preparation - */ -static int qcom_write_reg_dma(struct qcom_nand_controller *nandc, __le32 *= vaddr, - int first, int num_regs, unsigned int flags) -{ - bool flow_control =3D false; - - if (first =3D=3D NAND_EXEC_CMD) - flags |=3D NAND_BAM_NWD; - - if (first =3D=3D NAND_DEV_CMD1_RESTORE || first =3D=3D NAND_DEV_CMD1) - first =3D dev_cmd_reg_addr(nandc, NAND_DEV_CMD1); - - if (first =3D=3D NAND_DEV_CMD_VLD_RESTORE || first =3D=3D NAND_DEV_CMD_VL= D) - first =3D dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD); - - if (nandc->props->supports_bam) - return qcom_prep_bam_dma_desc_cmd(nandc, false, first, vaddr, - num_regs, flags); - - if (first =3D=3D NAND_FLASH_CMD) - flow_control =3D true; - - return qcom_prep_adm_dma_desc(nandc, false, first, vaddr, - num_regs * sizeof(u32), flow_control); -} - -/* - * qcom_read_data_dma: prepares a DMA descriptor to transfer data from the - * controller's internal buffer to the buffer 'vaddr' - * - * @reg_off: offset within the controller's data buffer - * @vaddr: virtual address of the buffer we want to write to - * @size: DMA transaction size in bytes - * @flags: flags to control DMA descriptor preparation - */ -static int qcom_read_data_dma(struct qcom_nand_controller *nandc, int reg_= off, - const u8 *vaddr, int size, unsigned int flags) -{ - if (nandc->props->supports_bam) - return qcom_prep_bam_dma_desc_data(nandc, true, vaddr, size, flags); - - return qcom_prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false); -} - -/* - * qcom_write_data_dma: prepares a DMA descriptor to transfer data from - * 'vaddr' to the controller's internal buffer - * - * @reg_off: offset within the controller's data buffer - * @vaddr: virtual address of the buffer we want to read from - * @size: DMA transaction size in bytes - * @flags: flags to control DMA descriptor preparation - */ -static int qcom_write_data_dma(struct qcom_nand_controller *nandc, int reg= _off, - const u8 *vaddr, int size, unsigned int flags) -{ - if (nandc->props->supports_bam) - return qcom_prep_bam_dma_desc_data(nandc, false, vaddr, size, flags); - - return qcom_prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false); -} - /* * Helper to prepare DMA descriptors for configuring registers * before reading a NAND page. @@ -1262,83 +394,6 @@ static void config_nand_cw_write(struct nand_chip *ch= ip) NAND_BAM_NEXT_SGL); } =20 -/* helpers to submit/free our list of dma descriptors */ -static int qcom_submit_descs(struct qcom_nand_controller *nandc) -{ - struct desc_info *desc, *n; - dma_cookie_t cookie =3D 0; - struct bam_transaction *bam_txn =3D nandc->bam_txn; - int ret =3D 0; - - if (nandc->props->supports_bam) { - if (bam_txn->rx_sgl_pos > bam_txn->rx_sgl_start) { - ret =3D qcom_prepare_bam_async_desc(nandc, nandc->rx_chan, 0); - if (ret) - goto err_unmap_free_desc; - } - - if (bam_txn->tx_sgl_pos > bam_txn->tx_sgl_start) { - ret =3D qcom_prepare_bam_async_desc(nandc, nandc->tx_chan, - DMA_PREP_INTERRUPT); - if (ret) - goto err_unmap_free_desc; - } - - if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) { - ret =3D qcom_prepare_bam_async_desc(nandc, nandc->cmd_chan, - DMA_PREP_CMD); - if (ret) - goto err_unmap_free_desc; - } - } - - list_for_each_entry(desc, &nandc->desc_list, node) - cookie =3D dmaengine_submit(desc->dma_desc); - - if (nandc->props->supports_bam) { - bam_txn->last_cmd_desc->callback =3D qcom_qpic_bam_dma_done; - bam_txn->last_cmd_desc->callback_param =3D bam_txn; - - dma_async_issue_pending(nandc->tx_chan); - dma_async_issue_pending(nandc->rx_chan); - dma_async_issue_pending(nandc->cmd_chan); - - if (!wait_for_completion_timeout(&bam_txn->txn_done, - QPIC_NAND_COMPLETION_TIMEOUT)) - ret =3D -ETIMEDOUT; - } else { - if (dma_sync_wait(nandc->chan, cookie) !=3D DMA_COMPLETE) - ret =3D -ETIMEDOUT; - } - -err_unmap_free_desc: - /* - * Unmap the dma sg_list and free the desc allocated by both - * qcom_prepare_bam_async_desc() and qcom_prep_adm_dma_desc() functions. - */ - list_for_each_entry_safe(desc, n, &nandc->desc_list, node) { - list_del(&desc->node); - - if (nandc->props->supports_bam) - dma_unmap_sg(nandc->dev, desc->bam_sgl, - desc->sgl_cnt, desc->dir); - else - dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1, - desc->dir); - - kfree(desc); - } - - return ret; -} - -/* reset the register read buffer for next NAND operation */ -static void qcom_clear_read_regs(struct qcom_nand_controller *nandc) -{ - nandc->reg_read_pos =3D 0; - qcom_nandc_dev_to_mem(nandc, false); -} - /* * when using BCH ECC, the HW flags an error in NAND_FLASH_STATUS if it re= ad * an erased CW, and reports an erased CW in NAND_ERASED_CW_DETECT_STATUS. @@ -2967,141 +2022,14 @@ static const struct nand_controller_ops qcom_nandc= _ops =3D { .exec_op =3D qcom_nand_exec_op, }; =20 -static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc) -{ - if (nandc->props->supports_bam) { - if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma)) - dma_unmap_single(nandc->dev, nandc->reg_read_dma, - MAX_REG_RD * - sizeof(*nandc->reg_read_buf), - DMA_FROM_DEVICE); - - if (nandc->tx_chan) - dma_release_channel(nandc->tx_chan); - - if (nandc->rx_chan) - dma_release_channel(nandc->rx_chan); - - if (nandc->cmd_chan) - dma_release_channel(nandc->cmd_chan); - } else { - if (nandc->chan) - dma_release_channel(nandc->chan); - } -} - -static int qcom_nandc_alloc(struct qcom_nand_controller *nandc) -{ - int ret; - - ret =3D dma_set_coherent_mask(nandc->dev, DMA_BIT_MASK(32)); - if (ret) { - dev_err(nandc->dev, "failed to set DMA mask\n"); - return ret; - } - - /* - * we use the internal buffer for reading ONFI params, reading small - * data like ID and status, and preforming read-copy-write operations - * when writing to a codeword partially. 532 is the maximum possible - * size of a codeword for our nand controller - */ - nandc->buf_size =3D 532; - - nandc->data_buffer =3D devm_kzalloc(nandc->dev, nandc->buf_size, GFP_KERN= EL); - if (!nandc->data_buffer) - return -ENOMEM; - - nandc->regs =3D devm_kzalloc(nandc->dev, sizeof(*nandc->regs), GFP_KERNEL= ); - if (!nandc->regs) - return -ENOMEM; - - nandc->reg_read_buf =3D devm_kcalloc(nandc->dev, MAX_REG_RD, - sizeof(*nandc->reg_read_buf), - GFP_KERNEL); - if (!nandc->reg_read_buf) - return -ENOMEM; - - if (nandc->props->supports_bam) { - nandc->reg_read_dma =3D - dma_map_single(nandc->dev, nandc->reg_read_buf, - MAX_REG_RD * - sizeof(*nandc->reg_read_buf), - DMA_FROM_DEVICE); - if (dma_mapping_error(nandc->dev, nandc->reg_read_dma)) { - dev_err(nandc->dev, "failed to DMA MAP reg buffer\n"); - return -EIO; - } - - nandc->tx_chan =3D dma_request_chan(nandc->dev, "tx"); - if (IS_ERR(nandc->tx_chan)) { - ret =3D PTR_ERR(nandc->tx_chan); - nandc->tx_chan =3D NULL; - dev_err_probe(nandc->dev, ret, - "tx DMA channel request failed\n"); - goto unalloc; - } - - nandc->rx_chan =3D dma_request_chan(nandc->dev, "rx"); - if (IS_ERR(nandc->rx_chan)) { - ret =3D PTR_ERR(nandc->rx_chan); - nandc->rx_chan =3D NULL; - dev_err_probe(nandc->dev, ret, - "rx DMA channel request failed\n"); - goto unalloc; - } - - nandc->cmd_chan =3D dma_request_chan(nandc->dev, "cmd"); - if (IS_ERR(nandc->cmd_chan)) { - ret =3D PTR_ERR(nandc->cmd_chan); - nandc->cmd_chan =3D NULL; - dev_err_probe(nandc->dev, ret, - "cmd DMA channel request failed\n"); - goto unalloc; - } - - /* - * Initially allocate BAM transaction to read ONFI param page. - * After detecting all the devices, this BAM transaction will - * be freed and the next BAM transaction will be allocated with - * maximum codeword size - */ - nandc->max_cwperpage =3D 1; - nandc->bam_txn =3D qcom_alloc_bam_transaction(nandc); - if (!nandc->bam_txn) { - dev_err(nandc->dev, - "failed to allocate bam transaction\n"); - ret =3D -ENOMEM; - goto unalloc; - } - } else { - nandc->chan =3D dma_request_chan(nandc->dev, "rxtx"); - if (IS_ERR(nandc->chan)) { - ret =3D PTR_ERR(nandc->chan); - nandc->chan =3D NULL; - dev_err_probe(nandc->dev, ret, - "rxtx DMA channel request failed\n"); - return ret; - } - } - - INIT_LIST_HEAD(&nandc->desc_list); - INIT_LIST_HEAD(&nandc->host_list); - - nand_controller_init(&nandc->controller); - nandc->controller.ops =3D &qcom_nandc_ops; - - return 0; -unalloc: - qcom_nandc_unalloc(nandc); - return ret; -} - /* one time setup of a few nand controller registers */ static int qcom_nandc_setup(struct qcom_nand_controller *nandc) { u32 nand_ctrl; =20 + nand_controller_init(nandc->controller); + nandc->controller->ops =3D &qcom_nandc_ops; + /* kill onenand */ if (!nandc->props->nandc_part_of_qpic) nandc_write(nandc, SFLASHC_BURST_CFG, 0); @@ -3240,7 +2168,7 @@ static int qcom_nand_host_init_and_register(struct qc= om_nand_controller *nandc, chip->legacy.block_bad =3D qcom_nandc_block_bad; chip->legacy.block_markbad =3D qcom_nandc_block_markbad; =20 - chip->controller =3D &nandc->controller; + chip->controller =3D nandc->controller; chip->options |=3D NAND_NO_SUBPAGE_WRITE | NAND_USES_DMA | NAND_SKIP_BBTSCAN; =20 @@ -3323,17 +2251,21 @@ static int qcom_nandc_parse_dt(struct platform_devi= ce *pdev) static int qcom_nandc_probe(struct platform_device *pdev) { struct qcom_nand_controller *nandc; + struct nand_controller *controller; const void *dev_data; struct device *dev =3D &pdev->dev; struct resource *res; int ret; =20 - nandc =3D devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL); + nandc =3D devm_kzalloc(&pdev->dev, sizeof(*nandc) + sizeof(*controller), + GFP_KERNEL); if (!nandc) return -ENOMEM; + controller =3D (struct nand_controller *)&nandc[1]; =20 platform_set_drvdata(pdev, nandc); nandc->dev =3D dev; + nandc->controller =3D controller; =20 dev_data =3D of_device_get_match_data(dev); if (!dev_data) { diff --git a/include/linux/mtd/nand-qpic-common.h b/include/linux/mtd/nand-= qpic-common.h new file mode 100644 index 000000000000..425994429387 --- /dev/null +++ b/include/linux/mtd/nand-qpic-common.h @@ -0,0 +1,468 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * QCOM QPIC common APIs header file + * + * Copyright (c) 2023 Qualcomm Inc. + * Authors: Md sadre Alam + * + */ +#ifndef __MTD_NAND_QPIC_COMMON_H__ +#define __MTD_NAND_QPIC_COMMON_H__ + +/* NANDc reg offsets */ +#define NAND_FLASH_CMD 0x00 +#define NAND_ADDR0 0x04 +#define NAND_ADDR1 0x08 +#define NAND_FLASH_CHIP_SELECT 0x0c +#define NAND_EXEC_CMD 0x10 +#define NAND_FLASH_STATUS 0x14 +#define NAND_BUFFER_STATUS 0x18 +#define NAND_DEV0_CFG0 0x20 +#define NAND_DEV0_CFG1 0x24 +#define NAND_DEV0_ECC_CFG 0x28 +#define NAND_AUTO_STATUS_EN 0x2c +#define NAND_DEV1_CFG0 0x30 +#define NAND_DEV1_CFG1 0x34 +#define NAND_READ_ID 0x40 +#define NAND_READ_STATUS 0x44 +#define NAND_DEV_CMD0 0xa0 +#define NAND_DEV_CMD1 0xa4 +#define NAND_DEV_CMD2 0xa8 +#define NAND_DEV_CMD_VLD 0xac +#define SFLASHC_BURST_CFG 0xe0 +#define NAND_ERASED_CW_DETECT_CFG 0xe8 +#define NAND_ERASED_CW_DETECT_STATUS 0xec +#define NAND_EBI2_ECC_BUF_CFG 0xf0 +#define FLASH_BUF_ACC 0x100 + +#define NAND_CTRL 0xf00 +#define NAND_VERSION 0xf08 +#define NAND_READ_LOCATION_0 0xf20 +#define NAND_READ_LOCATION_1 0xf24 +#define NAND_READ_LOCATION_2 0xf28 +#define NAND_READ_LOCATION_3 0xf2c +#define NAND_READ_LOCATION_LAST_CW_0 0xf40 +#define NAND_READ_LOCATION_LAST_CW_1 0xf44 +#define NAND_READ_LOCATION_LAST_CW_2 0xf48 +#define NAND_READ_LOCATION_LAST_CW_3 0xf4c + +/* dummy register offsets, used by qcom_write_reg_dma */ +#define NAND_DEV_CMD1_RESTORE 0xdead +#define NAND_DEV_CMD_VLD_RESTORE 0xbeef + +/* NAND_FLASH_CMD bits */ +#define PAGE_ACC BIT(4) +#define LAST_PAGE BIT(5) + +/* NAND_FLASH_CHIP_SELECT bits */ +#define NAND_DEV_SEL 0 +#define DM_EN BIT(2) + +/* NAND_FLASH_STATUS bits */ +#define FS_OP_ERR BIT(4) +#define FS_READY_BSY_N BIT(5) +#define FS_MPU_ERR BIT(8) +#define FS_DEVICE_STS_ERR BIT(16) +#define FS_DEVICE_WP BIT(23) + +/* NAND_BUFFER_STATUS bits */ +#define BS_UNCORRECTABLE_BIT BIT(8) +#define BS_CORRECTABLE_ERR_MSK 0x1f + +/* NAND_DEVn_CFG0 bits */ +#define DISABLE_STATUS_AFTER_WRITE 4 +#define CW_PER_PAGE 6 +#define UD_SIZE_BYTES 9 +#define UD_SIZE_BYTES_MASK GENMASK(18, 9) +#define ECC_PARITY_SIZE_BYTES_RS 19 +#define SPARE_SIZE_BYTES 23 +#define SPARE_SIZE_BYTES_MASK GENMASK(26, 23) +#define NUM_ADDR_CYCLES 27 +#define STATUS_BFR_READ 30 +#define SET_RD_MODE_AFTER_STATUS 31 + +/* NAND_DEVn_CFG0 bits */ +#define DEV0_CFG1_ECC_DISABLE 0 +#define WIDE_FLASH 1 +#define NAND_RECOVERY_CYCLES 2 +#define CS_ACTIVE_BSY 5 +#define BAD_BLOCK_BYTE_NUM 6 +#define BAD_BLOCK_IN_SPARE_AREA 16 +#define WR_RD_BSY_GAP 17 +#define ENABLE_BCH_ECC 27 + +/* NAND_DEV0_ECC_CFG bits */ +#define ECC_CFG_ECC_DISABLE 0 +#define ECC_SW_RESET 1 +#define ECC_MODE 4 +#define ECC_PARITY_SIZE_BYTES_BCH 8 +#define ECC_NUM_DATA_BYTES 16 +#define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16) +#define ECC_FORCE_CLK_OPEN 30 + +/* NAND_DEV_CMD1 bits */ +#define READ_ADDR 0 + +/* NAND_DEV_CMD_VLD bits */ +#define READ_START_VLD BIT(0) +#define READ_STOP_VLD BIT(1) +#define WRITE_START_VLD BIT(2) +#define ERASE_START_VLD BIT(3) +#define SEQ_READ_START_VLD BIT(4) + +/* NAND_EBI2_ECC_BUF_CFG bits */ +#define NUM_STEPS 0 + +/* NAND_ERASED_CW_DETECT_CFG bits */ +#define ERASED_CW_ECC_MASK 1 +#define AUTO_DETECT_RES 0 +#define MASK_ECC BIT(ERASED_CW_ECC_MASK) +#define RESET_ERASED_DET BIT(AUTO_DETECT_RES) +#define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES) +#define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC) +#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC) + +/* NAND_ERASED_CW_DETECT_STATUS bits */ +#define PAGE_ALL_ERASED BIT(7) +#define CODEWORD_ALL_ERASED BIT(6) +#define PAGE_ERASED BIT(5) +#define CODEWORD_ERASED BIT(4) +#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED) +#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED) + +/* NAND_READ_LOCATION_n bits */ +#define READ_LOCATION_OFFSET 0 +#define READ_LOCATION_SIZE 16 +#define READ_LOCATION_LAST 31 + +/* Version Mask */ +#define NAND_VERSION_MAJOR_MASK 0xf0000000 +#define NAND_VERSION_MAJOR_SHIFT 28 +#define NAND_VERSION_MINOR_MASK 0x0fff0000 +#define NAND_VERSION_MINOR_SHIFT 16 + +/* NAND OP_CMDs */ +#define OP_PAGE_READ 0x2 +#define OP_PAGE_READ_WITH_ECC 0x3 +#define OP_PAGE_READ_WITH_ECC_SPARE 0x4 +#define OP_PAGE_READ_ONFI_READ 0x5 +#define OP_PROGRAM_PAGE 0x6 +#define OP_PAGE_PROGRAM_WITH_ECC 0x7 +#define OP_PROGRAM_PAGE_SPARE 0x9 +#define OP_BLOCK_ERASE 0xa +#define OP_CHECK_STATUS 0xc +#define OP_FETCH_ID 0xb +#define OP_RESET_DEVICE 0xd + +/* Default Value for NAND_DEV_CMD_VLD */ +#define NAND_DEV_CMD_VLD_VAL (READ_START_VLD | WRITE_START_VLD | \ + ERASE_START_VLD | SEQ_READ_START_VLD) + +/* NAND_CTRL bits */ +#define BAM_MODE_EN BIT(0) + +/* + * the NAND controller performs reads/writes with ECC in 516 byte chunks. + * the driver calls the chunks 'step' or 'codeword' interchangeably + */ +#define NANDC_STEP_SIZE 512 + +/* + * the largest page size we support is 8K, this will have 16 steps/codewor= ds + * of 512 bytes each + */ +#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE) + +/* we read at most 3 registers per codeword scan */ +#define MAX_REG_RD (3 * MAX_NUM_STEPS) + +/* ECC modes supported by the controller */ +#define ECC_NONE BIT(0) +#define ECC_RS_4BIT BIT(1) +#define ECC_BCH_4BIT BIT(2) +#define ECC_BCH_8BIT BIT(3) + +/* + * Returns the actual register address for all NAND_DEV_ registers + * (i.e. NAND_DEV_CMD0, NAND_DEV_CMD1, NAND_DEV_CMD2 and NAND_DEV_CMD_VLD) + */ +#define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + = (reg)) + +/* Returns the NAND register physical address */ +#define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset)) + +/* Returns the dma address for reg read buffer */ +#define reg_buf_dma_addr(chip, vaddr) \ + ((chip)->reg_read_dma + \ + ((u8 *)(vaddr) - (u8 *)(chip)->reg_read_buf)) + +#define QPIC_PER_CW_CMD_ELEMENTS 32 +#define QPIC_PER_CW_CMD_SGL 32 +#define QPIC_PER_CW_DATA_SGL 8 + +#define QPIC_NAND_COMPLETION_TIMEOUT msecs_to_jiffies(2000) + +/* + * Flags used in DMA descriptor preparation helper functions + * (i.e. qcom_read_reg_dma/qcom_write_reg_dma/qcom_read_data_dma/qcom_writ= e_data_dma) + */ +/* Don't set the EOT in current tx BAM sgl */ +#define NAND_BAM_NO_EOT BIT(0) +/* Set the NWD flag in current BAM sgl */ +#define NAND_BAM_NWD BIT(1) +/* Finish writing in the current BAM sgl and start writing in another BAM = sgl */ +#define NAND_BAM_NEXT_SGL BIT(2) +/* + * Erased codeword status is being used two times in single transfer so th= is + * flag will determine the current value of erased codeword status register + */ +#define NAND_ERASED_CW_SET BIT(4) + +#define MAX_ADDRESS_CYCLE 5 + +/* + * This data type corresponds to the BAM transaction which will be used fo= r all + * NAND transfers. + * @bam_ce - the array of BAM command elements + * @cmd_sgl - sgl for NAND BAM command pipe + * @data_sgl - sgl for NAND BAM consumer/producer pipe + * @last_data_desc - last DMA desc in data channel (tx/rx). + * @last_cmd_desc - last DMA desc in command channel. + * @txn_done - completion for NAND transfer. + * @bam_ce_pos - the index in bam_ce which is available for next sgl + * @bam_ce_start - the index in bam_ce which marks the start position ce + * for current sgl. It will be used for size calculation + * for current sgl + * @cmd_sgl_pos - current index in command sgl. + * @cmd_sgl_start - start index in command sgl. + * @tx_sgl_pos - current index in data sgl for tx. + * @tx_sgl_start - start index in data sgl for tx. + * @rx_sgl_pos - current index in data sgl for rx. + * @rx_sgl_start - start index in data sgl for rx. + */ +struct bam_transaction { + struct bam_cmd_element *bam_ce; + struct scatterlist *cmd_sgl; + struct scatterlist *data_sgl; + struct dma_async_tx_descriptor *last_data_desc; + struct dma_async_tx_descriptor *last_cmd_desc; + struct completion txn_done; + u32 bam_ce_pos; + u32 bam_ce_start; + u32 cmd_sgl_pos; + u32 cmd_sgl_start; + u32 tx_sgl_pos; + u32 tx_sgl_start; + u32 rx_sgl_pos; + u32 rx_sgl_start; +}; + +/* + * This data type corresponds to the nand dma descriptor + * @dma_desc - low level DMA engine descriptor + * @list - list for desc_info + * + * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only u= sed by + * ADM + * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM + * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM + * @dir - DMA transfer direction + */ +struct desc_info { + struct dma_async_tx_descriptor *dma_desc; + struct list_head node; + + union { + struct scatterlist adm_sgl; + struct { + struct scatterlist *bam_sgl; + int sgl_cnt; + }; + }; + enum dma_data_direction dir; +}; + +/* + * holds the current register values that we want to write. acts as a cont= iguous + * chunk of memory which we use to write the controller registers through = DMA. + */ +struct nandc_regs { + __le32 cmd; + __le32 addr0; + __le32 addr1; + __le32 chip_sel; + __le32 exec; + + __le32 cfg0; + __le32 cfg1; + __le32 ecc_bch_cfg; + + __le32 clrflashstatus; + __le32 clrreadstatus; + + __le32 cmd1; + __le32 vld; + + __le32 orig_cmd1; + __le32 orig_vld; + + __le32 ecc_buf_cfg; + __le32 read_location0; + __le32 read_location1; + __le32 read_location2; + __le32 read_location3; + __le32 read_location_last0; + __le32 read_location_last1; + __le32 read_location_last2; + __le32 read_location_last3; + + __le32 erased_cw_detect_cfg_clr; + __le32 erased_cw_detect_cfg_set; +}; + +/* + * NAND controller data struct + * + * @dev: parent device + * + * @base: MMIO base + * + * @core_clk: controller clock + * @aon_clk: another controller clock + * + * @regs: a contiguous chunk of memory for DMA register + * writes. contains the register values to be + * written to controller + * + * @props: properties of current NAND controller, + * initialized via DT match data + * + * @controller: base controller structure + * @host_list: list containing all the chips attached to the + * controller + * + * @chan: dma channel + * @cmd_crci: ADM DMA CRCI for command flow control + * @data_crci: ADM DMA CRCI for data flow control + * + * @desc_list: DMA descriptor list (list of desc_infos) + * + * @data_buffer: our local DMA buffer for page read/writes, + * used when we can't use the buffer provided + * by upper layers directly + * @reg_read_buf: local buffer for reading back registers via DMA + * + * @base_phys: physical base address of controller registers + * @base_dma: dma base address of controller registers + * @reg_read_dma: contains dma address for register read buffer + * + * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf + * functions + * @max_cwperpage: maximum QPIC codewords required. calculated + * from all connected NAND devices pagesize + * + * @reg_read_pos: marker for data read in reg_read_buf + * + * @cmd1/vld: some fixed controller register values + * + * @exec_opwrite: flag to select correct number of code word + * while reading status + */ +struct qcom_nand_controller { + struct device *dev; + + void __iomem *base; + + struct clk *core_clk; + struct clk *aon_clk; + + struct nandc_regs *regs; + struct bam_transaction *bam_txn; + + const struct qcom_nandc_props *props; + + struct nand_controller *controller; + struct list_head host_list; + + union { + /* will be used only by QPIC for BAM DMA */ + struct { + struct dma_chan *tx_chan; + struct dma_chan *rx_chan; + struct dma_chan *cmd_chan; + }; + + /* will be used only by EBI2 for ADM DMA */ + struct { + struct dma_chan *chan; + unsigned int cmd_crci; + unsigned int data_crci; + }; + }; + + struct list_head desc_list; + + u8 *data_buffer; + __le32 *reg_read_buf; + + phys_addr_t base_phys; + dma_addr_t base_dma; + dma_addr_t reg_read_dma; + + int buf_size; + int buf_count; + int buf_start; + unsigned int max_cwperpage; + + int reg_read_pos; + + u32 cmd1, vld; + bool exec_opwrite; +}; + +/* + * This data type corresponds to the NAND controller properties which vari= es + * among different NAND controllers. + * @ecc_modes - ecc mode for NAND + * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset + * @supports_bam - whether NAND controller is using BAM + * @nandc_part_of_qpic - whether NAND controller is part of qpic IP + * @qpic_version2 - flag to indicate QPIC IP version 2 + * @use_codeword_fixup - whether NAND has different layout for boot partit= ions + */ +struct qcom_nandc_props { + u32 ecc_modes; + u32 dev_cmd_reg_start; + bool supports_bam; + bool nandc_part_of_qpic; + bool qpic_version2; + bool use_codeword_fixup; +}; + +void qcom_free_bam_transaction(struct qcom_nand_controller *nandc); +struct bam_transaction *qcom_alloc_bam_transaction(struct qcom_nand_contro= ller *nandc); +void qcom_clear_bam_transaction(struct qcom_nand_controller *nandc); +void qcom_qpic_bam_dma_done(void *data); +void qcom_nandc_dev_to_mem(struct qcom_nand_controller *nandc, bool is_cpu= ); +int qcom_prepare_bam_async_desc(struct qcom_nand_controller *nandc, + struct dma_chan *chan, unsigned long flags); +int qcom_prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool re= ad, + int reg_off, const void *vaddr, int size, unsigned int flags); +int qcom_prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool r= ead, + const void *vaddr, int size, unsigned int flags); +int qcom_prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read, = int reg_off, + const void *vaddr, int size, bool flow_control); +int qcom_read_reg_dma(struct qcom_nand_controller *nandc, int first, int n= um_regs, + unsigned int flags); +int qcom_write_reg_dma(struct qcom_nand_controller *nandc, __le32 *vaddr, = int first, + int num_regs, unsigned int flags); +int qcom_read_data_dma(struct qcom_nand_controller *nandc, int reg_off, co= nst u8 *vaddr, + int size, unsigned int flags); +int qcom_write_data_dma(struct qcom_nand_controller *nandc, int reg_off, c= onst u8 *vaddr, + int size, unsigned int flags); +int qcom_submit_descs(struct qcom_nand_controller *nandc); +void qcom_clear_read_regs(struct qcom_nand_controller *nandc); +void qcom_nandc_unalloc(struct qcom_nand_controller *nandc); +int qcom_nandc_alloc(struct qcom_nand_controller *nandc); +#endif + --=20 2.34.1 From nobody Sat Nov 30 03:41:48 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2ED718BC2C; Thu, 12 Sep 2024 06:16:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726121777; cv=none; b=rESWy7Wq/EvlInIVoA+FyyzMSGtTeawdvv0dct3HtLBJsTH7Ls0C3OAS2EGLZZDDhOEFRlWQvCW3uB9kMDmhA2CFjKW0KxxpozHpvDDuszxQILTSKsZ9jF6qEw6VdT4z/mMxqEBtoP2HO7AHyh/blu5DEveYZ7u/HrzAcufGFd4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726121777; c=relaxed/simple; bh=PK+z9FVMPrCuM3JQrPNZtI1g6nUAEoJmt+uA3qbMK9Y=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nD/Lx95VsxJoqYG5hm5Pxw8jcDhOvqN3vGGpCWL75x54fadQNJqr7m0Fe5cmGQXFermkQOIpZtGp3hv3E6B1YNCSdnkLtYzng9/mj4ejrKtp8m74hVIDpERaNEZI84+6besrw2g9E5mngp4h38bjeuvOakfaCEB1VQ0i+Cm/Aw4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=ffLCVmyt; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ffLCVmyt" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48C2Kx0U013919; Thu, 12 Sep 2024 06:15:54 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= ULvIzO2hcCDSlb1v8oVTIVXgzvmgFY3AD/j5mhrnyVA=; b=ffLCVmytlA4tJIJB LeTqsJVA7yAu1Q0vgVRYrffu85P9G2mCftl4xM5aEVYDinnLu3LRDzlZ7Sz9KZaH R6iLLXDBxerAOOk9oWghpG4XmRjzMC+fHb/q+MAZKZUHLDKLESMHa80SPPdDFC/X R4q05CjugjhCkgGPFCI1TEorV/2DIf8dh2p7s+zFEEFijGD2amo9xDlL+VrTEJFc Pm70VpNox5lzbnehguICZ/AITJ7zuU2wGPtxg7XpypmsfT78+0r/1xsBHEpZcWEj 562hIeST39Qk3UoTLd2FazWkzj16i3CbSaIGgikfxiC87yXtsTljAgbAIIbpfD25 hnnnzQ== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41gy8p4435-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Sep 2024 06:15:53 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48C6FqAb003982 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Sep 2024 06:15:52 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Sep 2024 23:15:47 -0700 From: Md Sadre Alam To: , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v9 5/8] mtd: rawnand: qcom: use FIELD_PREP and GENMASK Date: Thu, 12 Sep 2024 11:45:00 +0530 Message-ID: <20240912061503.3468147-6-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240912061503.3468147-1-quic_mdalam@quicinc.com> References: <20240912061503.3468147-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: fFp0SyXka2WLMUDW8FJis1WfvCa5UitH X-Proofpoint-ORIG-GUID: fFp0SyXka2WLMUDW8FJis1WfvCa5UitH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 impostorscore=0 mlxscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 mlxlogscore=999 lowpriorityscore=0 adultscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409120043 Content-Type: text/plain; charset="utf-8" Use the bitfield macro FIELD_PREP, and GENMASK to do the shift and mask in one go. This makes the code more readable. Signed-off-by: Md Sadre Alam --- Change in [v9] * In update_rw_regs() api added cpu_to_le32() macro to fix compilation issue reported by kernel test bot * In qcom_param_page_type_exec() api added cpu_to_le32() macro to fix compilation issue reported by kernel test bot =20 Change in [v8] * No change Change in [v7] * No change Change in [v6] * Added FIELD_PREP() and GENMASK() macro Change in [v5] * This patch was not included in [v1] Change in [v4] * This patch was not included in [v4] Change in [v3] * This patch was not included in [v3] Change in [v2] * This patch was not included in [v2] Change in [v1] * This patch was not included in [v1] drivers/mtd/nand/raw/qcom_nandc.c | 97 ++++++++++++++-------------- include/linux/mtd/nand-qpic-common.h | 31 +++++---- 2 files changed, 67 insertions(+), 61 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_= nandc.c index 91f1eb781cb2..c1159dbc8eba 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -281,7 +281,7 @@ static void update_rw_regs(struct qcom_nand_host *host,= int num_cw, bool read, i (num_cw - 1) << CW_PER_PAGE); =20 cfg1 =3D cpu_to_le32(host->cfg1_raw); - ecc_bch_cfg =3D cpu_to_le32(1 << ECC_CFG_ECC_DISABLE); + ecc_bch_cfg =3D cpu_to_le32(ECC_CFG_ECC_DISABLE); } =20 nandc->regs->cmd =3D cmd; @@ -1494,42 +1494,41 @@ static int qcom_nand_attach_chip(struct nand_chip *= chip) host->cw_size =3D host->cw_data + ecc->bytes; bad_block_byte =3D mtd->writesize - host->cw_size * (cwperpage - 1) + 1; =20 - host->cfg0 =3D (cwperpage - 1) << CW_PER_PAGE - | host->cw_data << UD_SIZE_BYTES - | 0 << DISABLE_STATUS_AFTER_WRITE - | 5 << NUM_ADDR_CYCLES - | host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_RS - | 0 << STATUS_BFR_READ - | 1 << SET_RD_MODE_AFTER_STATUS - | host->spare_bytes << SPARE_SIZE_BYTES; - - host->cfg1 =3D 7 << NAND_RECOVERY_CYCLES - | 0 << CS_ACTIVE_BSY - | bad_block_byte << BAD_BLOCK_BYTE_NUM - | 0 << BAD_BLOCK_IN_SPARE_AREA - | 2 << WR_RD_BSY_GAP - | wide_bus << WIDE_FLASH - | host->bch_enabled << ENABLE_BCH_ECC; - - host->cfg0_raw =3D (cwperpage - 1) << CW_PER_PAGE - | host->cw_size << UD_SIZE_BYTES - | 5 << NUM_ADDR_CYCLES - | 0 << SPARE_SIZE_BYTES; - - host->cfg1_raw =3D 7 << NAND_RECOVERY_CYCLES - | 0 << CS_ACTIVE_BSY - | 17 << BAD_BLOCK_BYTE_NUM - | 1 << BAD_BLOCK_IN_SPARE_AREA - | 2 << WR_RD_BSY_GAP - | wide_bus << WIDE_FLASH - | 1 << DEV0_CFG1_ECC_DISABLE; - - host->ecc_bch_cfg =3D !host->bch_enabled << ECC_CFG_ECC_DISABLE - | 0 << ECC_SW_RESET - | host->cw_data << ECC_NUM_DATA_BYTES - | 1 << ECC_FORCE_CLK_OPEN - | ecc_mode << ECC_MODE - | host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH; + host->cfg0 =3D FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) | + FIELD_PREP(UD_SIZE_BYTES_MASK, host->cw_data) | + FIELD_PREP(DISABLE_STATUS_AFTER_WRITE, 0) | + FIELD_PREP(NUM_ADDR_CYCLES_MASK, 5) | + FIELD_PREP(ECC_PARITY_SIZE_BYTES_RS, host->ecc_bytes_hw) | + FIELD_PREP(STATUS_BFR_READ, 0) | + FIELD_PREP(SET_RD_MODE_AFTER_STATUS, 1) | + FIELD_PREP(SPARE_SIZE_BYTES_MASK, host->spare_bytes); + + host->cfg1 =3D FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) | + FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, bad_block_byte) | + FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 0) | + FIELD_PREP(WR_RD_BSY_GAP_MASK, 2) | + FIELD_PREP(WIDE_FLASH, wide_bus) | + FIELD_PREP(ENABLE_BCH_ECC, host->bch_enabled); + + host->cfg0_raw =3D FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) | + FIELD_PREP(UD_SIZE_BYTES_MASK, host->cw_size) | + FIELD_PREP(NUM_ADDR_CYCLES_MASK, 5) | + FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0); + + host->cfg1_raw =3D FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) | + FIELD_PREP(CS_ACTIVE_BSY, 0) | + FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) | + FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) | + FIELD_PREP(WR_RD_BSY_GAP_MASK, 2) | + FIELD_PREP(WIDE_FLASH, wide_bus) | + FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1); + + host->ecc_bch_cfg =3D FIELD_PREP(ECC_CFG_ECC_DISABLE, !host->bch_enabled)= | + FIELD_PREP(ECC_SW_RESET, 0) | + FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, host->cw_data) | + FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) | + FIELD_PREP(ECC_MODE_MASK, ecc_mode) | + FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, host->ecc_bytes_hw); =20 if (!nandc->props->qpic_version2) host->ecc_buf_cfg =3D 0x203 << NUM_STEPS; @@ -1882,21 +1881,21 @@ static int qcom_param_page_type_exec(struct nand_ch= ip *chip, const struct nand_ nandc->regs->addr0 =3D 0; nandc->regs->addr1 =3D 0; =20 - nandc->regs->cfg0 =3D cpu_to_le32(0 << CW_PER_PAGE - | 512 << UD_SIZE_BYTES - | 5 << NUM_ADDR_CYCLES - | 0 << SPARE_SIZE_BYTES); + host->cfg0 =3D FIELD_PREP(CW_PER_PAGE_MASK, 0) | + FIELD_PREP(UD_SIZE_BYTES_MASK, 512) | + FIELD_PREP(NUM_ADDR_CYCLES_MASK, 5) | + FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0); =20 - nandc->regs->cfg1 =3D cpu_to_le32(7 << NAND_RECOVERY_CYCLES - | 0 << CS_ACTIVE_BSY - | 17 << BAD_BLOCK_BYTE_NUM - | 1 << BAD_BLOCK_IN_SPARE_AREA - | 2 << WR_RD_BSY_GAP - | 0 << WIDE_FLASH - | 1 << DEV0_CFG1_ECC_DISABLE); + host->cfg1 =3D FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) | + FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) | + FIELD_PREP(CS_ACTIVE_BSY, 0) | + FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) | + FIELD_PREP(WR_RD_BSY_GAP_MASK, 2) | + FIELD_PREP(WIDE_FLASH, 0) | + FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1); =20 if (!nandc->props->qpic_version2) - nandc->regs->ecc_buf_cfg =3D cpu_to_le32(1 << ECC_CFG_ECC_DISABLE); + nandc->regs->ecc_buf_cfg =3D cpu_to_le32(ECC_CFG_ECC_DISABLE); =20 /* configure CMD1 and VLD for ONFI param probing in QPIC v1 */ if (!nandc->props->qpic_version2) { diff --git a/include/linux/mtd/nand-qpic-common.h b/include/linux/mtd/nand-= qpic-common.h index 425994429387..e79c79775eb8 100644 --- a/include/linux/mtd/nand-qpic-common.h +++ b/include/linux/mtd/nand-qpic-common.h @@ -70,35 +70,42 @@ #define BS_CORRECTABLE_ERR_MSK 0x1f =20 /* NAND_DEVn_CFG0 bits */ -#define DISABLE_STATUS_AFTER_WRITE 4 +#define DISABLE_STATUS_AFTER_WRITE BIT(4) #define CW_PER_PAGE 6 +#define CW_PER_PAGE_MASK GENMASK(8, 6) #define UD_SIZE_BYTES 9 #define UD_SIZE_BYTES_MASK GENMASK(18, 9) -#define ECC_PARITY_SIZE_BYTES_RS 19 +#define ECC_PARITY_SIZE_BYTES_RS GENMASK(22, 19) #define SPARE_SIZE_BYTES 23 #define SPARE_SIZE_BYTES_MASK GENMASK(26, 23) #define NUM_ADDR_CYCLES 27 -#define STATUS_BFR_READ 30 -#define SET_RD_MODE_AFTER_STATUS 31 +#define NUM_ADDR_CYCLES_MASK GENMASK(29, 27) +#define STATUS_BFR_READ BIT(30) +#define SET_RD_MODE_AFTER_STATUS BIT(31) =20 /* NAND_DEVn_CFG0 bits */ -#define DEV0_CFG1_ECC_DISABLE 0 -#define WIDE_FLASH 1 +#define DEV0_CFG1_ECC_DISABLE BIT(0) +#define WIDE_FLASH BIT(1) #define NAND_RECOVERY_CYCLES 2 -#define CS_ACTIVE_BSY 5 +#define NAND_RECOVERY_CYCLES_MASK GENMASK(4, 2) +#define CS_ACTIVE_BSY BIT(5) #define BAD_BLOCK_BYTE_NUM 6 -#define BAD_BLOCK_IN_SPARE_AREA 16 +#define BAD_BLOCK_BYTE_NUM_MASK GENMASK(15, 6) +#define BAD_BLOCK_IN_SPARE_AREA BIT(16) #define WR_RD_BSY_GAP 17 -#define ENABLE_BCH_ECC 27 +#define WR_RD_BSY_GAP_MASK GENMASK(22, 17) +#define ENABLE_BCH_ECC BIT(27) =20 /* NAND_DEV0_ECC_CFG bits */ -#define ECC_CFG_ECC_DISABLE 0 -#define ECC_SW_RESET 1 +#define ECC_CFG_ECC_DISABLE BIT(0) +#define ECC_SW_RESET BIT(1) #define ECC_MODE 4 +#define ECC_MODE_MASK GENMASK(5, 4) #define ECC_PARITY_SIZE_BYTES_BCH 8 +#define ECC_PARITY_SIZE_BYTES_BCH_MASK GENMASK(12, 8) #define ECC_NUM_DATA_BYTES 16 #define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16) -#define ECC_FORCE_CLK_OPEN 30 +#define ECC_FORCE_CLK_OPEN BIT(30) =20 /* NAND_DEV_CMD1 bits */ #define READ_ADDR 0 --=20 2.34.1 From nobody Sat Nov 30 03:41:48 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CEEC818BC00; Thu, 12 Sep 2024 06:16:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726121795; cv=none; b=JIcD+7LIq+kdA6Z2Wp9CjkmvWZdahBeoKrjdw5UCG08EGgyHZfcQO8IHJP0G4mBoB4zolU0E2fLZZR+4A2WD3b/ebe4XJDGKLAFJHvfzGEwme4/g2+jDqRXT5HeNx4vZxwGZNACc/m1w3dAWuMuNJMTFiTyWXZGGwcJZZNT9uJM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726121795; c=relaxed/simple; bh=WC3OMLdt5tFbme8ihXL8DO2XCMuPM9bJm7ZuxVSQooQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=IPvTn8shD2o2KqTRfs0DkMGnhVT3uhdZ1GNVYQ+/6Lv/nf5UQOzX5IvEMGBu/T7aIZY5IxSsc+NFEaEwSwFJF0GrJbjVO/Ab3baZCpGaDaeeLk5YKGubJgh4QpIa5KCMDmw/YcKi5Uj9NqhpfE5CHHBia9CtJzi4YcrFyhM8Lyk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=DrnPKL7W; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="DrnPKL7W" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48C2L7Vh028482; Thu, 12 Sep 2024 06:16:00 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= t938qCLGrIct8Qr8bVHKAHRok21cq6AQkcGnlYI97ig=; b=DrnPKL7We02PUie9 r41h6GYiNZH5Y7PCBIDqZIVKe/SMI/wd9B2ebdbLRGxWKwtRnuzASNgZgfDpxxzh KsNkVxO28ul0/5TSW22o7ChbWQvtye0szxzO2YFxIRA0HKmS7sQtXIpPqqJwY2ZD +HiiIDAiOGmT4z5dN4z4K1OQYlOiYTdHzxOMHuERb4GK2QcWaIsfPqYt5XJUyIrU 2/v7HGmsaqhXvJIRg12OGfGUYETQ6/uPmwXqQnlZBttc4UMziClQjZL6TsY6CIv6 UtCtg5qQutBeuHM8TWldpJWbdjP4enlOCfTSQeuHQRGIO0DP7m41i0RRjt2QoXb8 hieMBw== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41gy7344ps-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Sep 2024 06:15:59 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48C6FwX7012555 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Sep 2024 06:15:58 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Sep 2024 23:15:52 -0700 From: Md Sadre Alam To: , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v9 6/8] spi: spi-qpic: add driver for QCOM SPI NAND flash Interface Date: Thu, 12 Sep 2024 11:45:01 +0530 Message-ID: <20240912061503.3468147-7-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240912061503.3468147-1-quic_mdalam@quicinc.com> References: <20240912061503.3468147-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 70gbbtS9Y-DvTi_R0BxFrzvKSDpy3b7S X-Proofpoint-GUID: 70gbbtS9Y-DvTi_R0BxFrzvKSDpy3b7S X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 suspectscore=0 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409120043 Content-Type: text/plain; charset="utf-8" This driver implements support for the SPI-NAND mode of QCOM NAND Flash Interface as a SPI-MEM controller with pipelined ECC capability. Co-developed-by: Sricharan Ramabadhran Signed-off-by: Sricharan Ramabadhran Co-developed-by: Varadarajan Narayanan Signed-off-by: Varadarajan Narayanan Signed-off-by: Md Sadre Alam --- Change in [v9] * Changed data type of addr1, addr2, cmd, to __le32 in qpic_spi_nand structure * In qcom_spi_set_read_loc_first() api added cpu_to_le32() macro to fix compilation warning * In qcom_spi_set_read_loc_last() api added cpu_to_le32() macro to fix compilation warning * In qcom_spi_init() api added cpu_to_le32() macro to fix compilation warning * In qcom_spi_ecc_init_ctx_pipelined() api removed unused variables reqs, user, step_size, strength and added cpu_to_le32() macro as well to fix compilation warning * In qcom_spi_read_last_cw() api added cpu_to_le32() macro to fix compilati= on warning * In qcom_spi_check_error() api added cpu_to_le32() macro to fix compilation warning * In qcom_spi_read_page_ecc() api added cpu_to_le32() macro to fix compilat= ion warning * In qcom_spi_read_page_oob() api added cpu_to_le32() macro to fix compilat= ion warning * In qcom_spi_program_raw() api added cpu_to_le32() macro to fix compilation warning * In qcom_spi_program_ecc() api added cpu_to_le32() macro to fix compilation warning * In qcom_spi_program_oob() api added cpu_to_le32() macro to fix compilation warning * In qcom_spi_send_cmdaddr() api added cpu_to_le32() macro to fix compilati= on warning * In qcom_spi_io_op() api added cpu_to_le32() macro to fix compilation warning Change in [v8] * Included "bitfield.h" file to /spi-qpic-snand.c to fix compilation warning reported by kernel test robot * Removed unused variable "steps" in=20 qcom_spi_ecc_init_ctx_pipelined() to fix compilation warning Change in [v7] * Added read_oob() and write_oob() api * Handled offset value for oob layout * Made CONFIG_SPI_QPIC_SNAND as bool * Added macro ecceng_to_qspi() * Added FIELD_PREP() Macro in spi init * Added else condition in=20 qcom_spi_ecc_finish_io_req_pipelined() for corrected ecc * Handled multiple error condition for api qcom_spi_cmd_mapping() * Fix typo for printing debug message =20 Change in [v6] * Added separate qpic_spi_nand{...} struct * moved qpic_ecc and qcom_ecc_stats struct to spi-qpic-snand.c file, since its spi nand specific * Added FIELD_PREP() and GENMASK() macro * Removed rawnand.h and partition.h from=20 spi-qpic-snand.c * Removed oob_buff assignment form qcom_spi_write_page_cache * Added qcom_nand_unalloc() in remove() path * Fixes all all comments Change in [v5] * Added raw_read() and raw_write() api * Updated commit message * Removed register indirection * Added qcom_spi_ prefix to all the api * Removed snand_set_reg() api. * Fixed nandbiterr issue * Removed hardcoded num_cw and made it variable * Removed hardcoded value for mtd pagesize * Added -ENOSUPPORT in cmd mapping for unsupported commands * Replace if..else with switch..case statement Change in [v4] * No change Change in [v3] * Set SPI_QPIC_SNAND to n and added COMPILE_TEST in Kconfig * Made driver name sorted in Make file * Made comment like c++ * Changed macro to functions, snandc_set_read_loc_last() and snandc_set_read_loc_first() * Added error handling in snandc_set_reg() * Changed into normal conditional statement for return snandc->ecc_stats.failed ? -EBADMSG : snandc->ecc_stats.bitflips; * Remove cast of wbuf in qpic_snand_program_execute() function * Made num_cw variable instead hardcoded value * changed if..else condition of function qpic_snand_io_op() to switch..case statement * Added __devm_spi_alloc_controller() api instead of devm_spi_alloc_master() * Disabling clock in remove path Change in [v2] * Added initial support for SPI-NAND driver Change in [v1] * Added RFC patch for design review drivers/mtd/nand/Makefile | 5 +- drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/spi-qpic-snand.c | 1634 ++++++++++++++++++++++++++ include/linux/mtd/nand-qpic-common.h | 7 + 5 files changed, 1654 insertions(+), 1 deletion(-) create mode 100644 drivers/spi/spi-qpic-snand.c diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 760a6e4efdac..1fa13e750f38 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -6,8 +6,11 @@ obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) +=3D ecc-mtk.o =20 ifeq ($(CONFIG_MTD_NAND_QCOM),y) obj-y +=3D qpic_common.o +else +ifeq ($(CONFIG_SPI_QPIC_SNAND),y) +obj-y +=3D qpic_common.o +endif endif - obj-y +=3D onenand/ obj-y +=3D raw/ obj-y +=3D spi/ diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 823797217404..053be7bbcd86 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -898,6 +898,14 @@ config SPI_QCOM_QSPI help QSPI(Quad SPI) driver for Qualcomm QSPI controller. =20 +config SPI_QPIC_SNAND + bool "QPIC SNAND controller" + depends on ARCH_QCOM || COMPILE_TEST + help + QPIC_SNAND (QPIC SPI NAND) driver for Qualcomm QPIC controller. + QPIC controller supports both parallel nand and serial nand. + This config will enable serial nand driver for QPIC controller. + config SPI_QUP tristate "Qualcomm SPI controller with QUP interface" depends on ARCH_QCOM || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index a9b1bc259b68..d9d674eb84a6 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -114,6 +114,7 @@ obj-$(CONFIG_SPI_PXA2XX) +=3D spi-pxa2xx-platform.o obj-$(CONFIG_SPI_PXA2XX_PCI) +=3D spi-pxa2xx-pci.o obj-$(CONFIG_SPI_QCOM_GENI) +=3D spi-geni-qcom.o obj-$(CONFIG_SPI_QCOM_QSPI) +=3D spi-qcom-qspi.o +obj-$(CONFIG_SPI_QPIC_SNAND) +=3D spi-qpic-snand.o obj-$(CONFIG_SPI_QUP) +=3D spi-qup.o obj-$(CONFIG_SPI_ROCKCHIP) +=3D spi-rockchip.o obj-$(CONFIG_SPI_ROCKCHIP_SFC) +=3D spi-rockchip-sfc.o diff --git a/drivers/spi/spi-qpic-snand.c b/drivers/spi/spi-qpic-snand.c new file mode 100644 index 000000000000..2a143cd15071 --- /dev/null +++ b/drivers/spi/spi-qpic-snand.c @@ -0,0 +1,1634 @@ +/* + * SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserve= d. + * + * Authors: + * Md Sadre Alam + * Sricharan R + * Varadarajan Narayanan + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NAND_FLASH_SPI_CFG 0xc0 +#define NAND_NUM_ADDR_CYCLES 0xc4 +#define NAND_BUSY_CHECK_WAIT_CNT 0xc8 +#define NAND_FLASH_FEATURES 0xf64 + +/* QSPI NAND config reg bits */ +#define LOAD_CLK_CNTR_INIT_EN BIT(28) +#define CLK_CNTR_INIT_VAL_VEC 0x924 +#define CLK_CNTR_INIT_VAL_VEC_MASK GENMASK(27, 16) +#define FEA_STATUS_DEV_ADDR 0xc0 +#define FEA_STATUS_DEV_ADDR_MASK GENMASK(15, 8) +#define SPI_CFG BIT(0) +#define SPI_NUM_ADDR 0xDA4DB +#define SPI_WAIT_CNT 0x10 +#define QPIC_QSPI_NUM_CS 1 +#define SPI_TRANSFER_MODE_x1 BIT(29) +#define SPI_TRANSFER_MODE_x4 (3 << 29) +#define SPI_WP BIT(28) +#define SPI_HOLD BIT(27) +#define QPIC_SET_FEATURE BIT(31) + +#define SPINAND_RESET 0xff +#define SPINAND_READID 0x9f +#define SPINAND_GET_FEATURE 0x0f +#define SPINAND_SET_FEATURE 0x1f +#define SPINAND_READ 0x13 +#define SPINAND_ERASE 0xd8 +#define SPINAND_WRITE_EN 0x06 +#define SPINAND_PROGRAM_EXECUTE 0x10 +#define SPINAND_PROGRAM_LOAD 0x84 + +#define ACC_FEATURE 0xe +#define BAD_BLOCK_MARKER_SIZE 0x2 +#define OOB_BUF_SIZE 128 +#define ecceng_to_qspi(eng) container_of(eng, struct qpic_spi_nand, ecc_e= ng) +struct qpic_snand_op { + u32 cmd_reg; + u32 addr1_reg; + u32 addr2_reg; +}; + +struct snandc_read_status { + __le32 snandc_flash; + __le32 snandc_buffer; + __le32 snandc_erased_cw; +}; + +/* + * ECC state struct + * @corrected: ECC corrected + * @bitflips: Max bit flip + * @failed: ECC failed + */ +struct qcom_ecc_stats { + u32 corrected; + u32 bitflips; + u32 failed; +}; + +struct qpic_ecc { + struct device *dev; + int ecc_bytes_hw; + int spare_bytes; + int bbm_size; + int ecc_mode; + int bytes; + int steps; + int step_size; + int strength; + int cw_size; + int cw_data; + u32 cfg0; + u32 cfg1; + u32 cfg0_raw; + u32 cfg1_raw; + u32 ecc_buf_cfg; + u32 ecc_bch_cfg; + u32 clrflashstatus; + u32 clrreadstatus; + bool bch_enabled; +}; + +struct qpic_spi_nand { + struct qcom_nand_controller *snandc; + struct spi_controller *ctlr; + struct mtd_info *mtd; + struct clk *iomacro_clk; + struct qpic_ecc *ecc; + struct qcom_ecc_stats ecc_stats; + struct nand_ecc_engine ecc_eng; + u8 *data_buf; + u8 *oob_buf; + u32 wlen; + __le32 addr1; + __le32 addr2; + __le32 cmd; + u32 num_cw; + bool oob_rw; + bool page_rw; + bool raw_rw; +}; + +static void qcom_spi_set_read_loc_first(struct qcom_nand_controller *snand= c, + int reg, int cw_offset, int read_size, + int is_last_read_loc) +{ + __le32 locreg_val; + u32 val =3D (((cw_offset) << READ_LOCATION_OFFSET) | + ((read_size) << READ_LOCATION_SIZE) | ((is_last_read_loc) + << READ_LOCATION_LAST)); + + locreg_val =3D cpu_to_le32(val); + + if (reg =3D=3D NAND_READ_LOCATION_0) + snandc->regs->read_location0 =3D locreg_val; + else if (reg =3D=3D NAND_READ_LOCATION_1) + snandc->regs->read_location1 =3D locreg_val; + else if (reg =3D=3D NAND_READ_LOCATION_2) + snandc->regs->read_location1 =3D locreg_val; + else if (reg =3D=3D NAND_READ_LOCATION_3) + snandc->regs->read_location3 =3D locreg_val; +} + +static void qcom_spi_set_read_loc_last(struct qcom_nand_controller *snandc, + int reg, int cw_offset, int read_size, + int is_last_read_loc) +{ + __le32 locreg_val; + u32 val =3D (((cw_offset) << READ_LOCATION_OFFSET) | + ((read_size) << READ_LOCATION_SIZE) | ((is_last_read_loc) + << READ_LOCATION_LAST)); + + locreg_val =3D cpu_to_le32(val); + + if (reg =3D=3D NAND_READ_LOCATION_LAST_CW_0) + snandc->regs->read_location_last0 =3D locreg_val; + else if (reg =3D=3D NAND_READ_LOCATION_LAST_CW_1) + snandc->regs->read_location_last1 =3D locreg_val; + else if (reg =3D=3D NAND_READ_LOCATION_LAST_CW_2) + snandc->regs->read_location_last2 =3D locreg_val; + else if (reg =3D=3D NAND_READ_LOCATION_LAST_CW_3) + snandc->regs->read_location_last3 =3D locreg_val; +} + +static struct qcom_nand_controller *nand_to_qcom_snand(struct nand_device = *nand) +{ + struct nand_ecc_engine *eng =3D nand->ecc.engine; + struct qpic_spi_nand *qspi =3D ecceng_to_qspi(eng); + + return qspi->snandc; +} + +static int qcom_spi_init(struct qcom_nand_controller *snandc) +{ + u32 snand_cfg_val =3D 0x0; + int ret; + + snand_cfg_val =3D FIELD_PREP(CLK_CNTR_INIT_VAL_VEC_MASK, CLK_CNTR_INIT_VA= L_VEC) | + FIELD_PREP(LOAD_CLK_CNTR_INIT_EN, 0) | + FIELD_PREP(FEA_STATUS_DEV_ADDR_MASK, FEA_STATUS_DEV_ADDR) | + FIELD_PREP(SPI_CFG, 0); + + snandc->regs->spi_cfg =3D cpu_to_le32(snand_cfg_val); + snandc->regs->num_addr_cycle =3D cpu_to_le32(SPI_NUM_ADDR); + snandc->regs->busy_wait_cnt =3D cpu_to_le32(SPI_WAIT_CNT); + + qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1,= 0); + + snand_cfg_val &=3D ~LOAD_CLK_CNTR_INIT_EN; + snandc->regs->spi_cfg =3D cpu_to_le32(snand_cfg_val); + + qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1,= 0); + + qcom_write_reg_dma(snandc, &snandc->regs->num_addr_cycle, NAND_NUM_ADDR_C= YCLES, 1, 0); + qcom_write_reg_dma(snandc, &snandc->regs->busy_wait_cnt, NAND_BUSY_CHECK_= WAIT_CNT, 1, + NAND_BAM_NEXT_SGL); + + ret =3D qcom_submit_descs(snandc); + if (ret) { + dev_err(snandc->dev, "failure in submitting spi init descriptor\n"); + return ret; + } + + return ret; +} + +static int qcom_spi_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *oobregion) +{ + struct nand_device *nand =3D mtd_to_nanddev(mtd); + struct qcom_nand_controller *snandc =3D nand_to_qcom_snand(nand); + struct qpic_ecc *qecc =3D snandc->qspi->ecc; + + if (section > 1) + return -ERANGE; + + oobregion->length =3D qecc->ecc_bytes_hw + qecc->spare_bytes; + oobregion->offset =3D mtd->oobsize - oobregion->length; + + return 0; +} + +static int qcom_spi_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *oobregion) +{ + struct nand_device *nand =3D mtd_to_nanddev(mtd); + struct qcom_nand_controller *snandc =3D nand_to_qcom_snand(nand); + struct qpic_ecc *qecc =3D snandc->qspi->ecc; + + if (section) + return -ERANGE; + + oobregion->length =3D qecc->steps * 4; + oobregion->offset =3D ((qecc->steps - 1) * qecc->bytes) + qecc->bbm_size; + + return 0; +} + +static const struct mtd_ooblayout_ops qcom_spi_ooblayout =3D { + .ecc =3D qcom_spi_ooblayout_ecc, + .free =3D qcom_spi_ooblayout_free, +}; + +static int qcom_spi_ecc_init_ctx_pipelined(struct nand_device *nand) +{ + struct qcom_nand_controller *snandc =3D nand_to_qcom_snand(nand); + struct nand_ecc_props *conf =3D &nand->ecc.ctx.conf; + struct mtd_info *mtd =3D nanddev_to_mtd(nand); + int cwperpage, bad_block_byte; + struct qpic_ecc *ecc_cfg; + + cwperpage =3D mtd->writesize / NANDC_STEP_SIZE; + snandc->qspi->num_cw =3D cwperpage; + + ecc_cfg =3D kzalloc(sizeof(*ecc_cfg), GFP_KERNEL); + if (!ecc_cfg) + return -ENOMEM; + snandc->qspi->oob_buf =3D kzalloc(mtd->writesize + mtd->oobsize, + GFP_KERNEL); + if (!snandc->qspi->oob_buf) + return -ENOMEM; + + memset(snandc->qspi->oob_buf, 0xff, mtd->writesize + mtd->oobsize); + + nand->ecc.ctx.priv =3D ecc_cfg; + snandc->qspi->mtd =3D mtd; + + ecc_cfg->ecc_bytes_hw =3D 7; + ecc_cfg->spare_bytes =3D 4; + ecc_cfg->bbm_size =3D 1; + ecc_cfg->bch_enabled =3D true; + ecc_cfg->bytes =3D ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes + ecc_cfg= ->bbm_size; + + ecc_cfg->steps =3D 4; + ecc_cfg->strength =3D 4; + ecc_cfg->step_size =3D 512; + ecc_cfg->cw_data =3D 516; + ecc_cfg->cw_size =3D ecc_cfg->cw_data + ecc_cfg->bytes; + bad_block_byte =3D mtd->writesize - ecc_cfg->cw_size * (cwperpage - 1) + = 1; + + mtd_set_ooblayout(mtd, &qcom_spi_ooblayout); + + ecc_cfg->cfg0 =3D FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) | + FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_data) | + FIELD_PREP(DISABLE_STATUS_AFTER_WRITE, 1) | + FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) | + FIELD_PREP(ECC_PARITY_SIZE_BYTES_RS, ecc_cfg->ecc_bytes_hw) | + FIELD_PREP(STATUS_BFR_READ, 0) | + FIELD_PREP(SET_RD_MODE_AFTER_STATUS, 1) | + FIELD_PREP(SPARE_SIZE_BYTES_MASK, ecc_cfg->spare_bytes); + + ecc_cfg->cfg1 =3D FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) | + FIELD_PREP(CS_ACTIVE_BSY, 0) | + FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, bad_block_byte) | + FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 0) | + FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) | + FIELD_PREP(WIDE_FLASH, 0) | + FIELD_PREP(ENABLE_BCH_ECC, ecc_cfg->bch_enabled); + + ecc_cfg->cfg0_raw =3D FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) | + FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) | + FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_size) | + FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0); + + ecc_cfg->cfg1_raw =3D FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) | + FIELD_PREP(CS_ACTIVE_BSY, 0) | + FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) | + FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) | + FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) | + FIELD_PREP(WIDE_FLASH, 0) | + FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1); + + ecc_cfg->ecc_bch_cfg =3D FIELD_PREP(ECC_CFG_ECC_DISABLE, !ecc_cfg->bch_en= abled) | + FIELD_PREP(ECC_SW_RESET, 0) | + FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, ecc_cfg->cw_data) | + FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) | + FIELD_PREP(ECC_MODE_MASK, 0) | + FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw= ); + + ecc_cfg->ecc_buf_cfg =3D 0x203 << NUM_STEPS; + ecc_cfg->clrflashstatus =3D FS_READY_BSY_N; + ecc_cfg->clrreadstatus =3D 0xc0; + + conf->step_size =3D ecc_cfg->step_size; + conf->strength =3D ecc_cfg->strength; + + snandc->regs->erased_cw_detect_cfg_clr =3D cpu_to_le32(CLR_ERASED_PAGE_DE= T); + snandc->regs->erased_cw_detect_cfg_set =3D cpu_to_le32(SET_ERASED_PAGE_DE= T); + + dev_dbg(snandc->dev, "ECC strength: %u bits per %u bytes\n", + ecc_cfg->strength, ecc_cfg->step_size); + + return 0; +} + +static void qcom_spi_ecc_cleanup_ctx_pipelined(struct nand_device *nand) +{ + struct qpic_ecc *ecc_cfg =3D nand_to_ecc_ctx(nand); + + kfree(ecc_cfg); +} + +static int qcom_spi_ecc_prepare_io_req_pipelined(struct nand_device *nand, + struct nand_page_io_req *req) +{ + struct qcom_nand_controller *snandc =3D nand_to_qcom_snand(nand); + struct qpic_ecc *ecc_cfg =3D nand_to_ecc_ctx(nand); + + snandc->qspi->ecc =3D ecc_cfg; + snandc->qspi->raw_rw =3D false; + snandc->qspi->oob_rw =3D false; + snandc->qspi->page_rw =3D false; + + if (req->datalen) + snandc->qspi->page_rw =3D true; + + if (req->ooblen) + snandc->qspi->oob_rw =3D true; + + if (req->mode =3D=3D MTD_OPS_RAW) + snandc->qspi->raw_rw =3D true; + + return 0; +} + +static int qcom_spi_ecc_finish_io_req_pipelined(struct nand_device *nand, + struct nand_page_io_req *req) +{ + struct qcom_nand_controller *snandc =3D nand_to_qcom_snand(nand); + struct mtd_info *mtd =3D nanddev_to_mtd(nand); + + if (req->mode =3D=3D MTD_OPS_RAW || req->type !=3D NAND_PAGE_READ) + return 0; + + if (snandc->qspi->ecc_stats.failed) + mtd->ecc_stats.failed +=3D snandc->qspi->ecc_stats.failed; + else + mtd->ecc_stats.corrected +=3D snandc->qspi->ecc_stats.corrected; + + if (snandc->qspi->ecc_stats.failed) + return -EBADMSG; + else + return snandc->qspi->ecc_stats.bitflips; +} + +static struct nand_ecc_engine_ops qcom_spi_ecc_engine_ops_pipelined =3D { + .init_ctx =3D qcom_spi_ecc_init_ctx_pipelined, + .cleanup_ctx =3D qcom_spi_ecc_cleanup_ctx_pipelined, + .prepare_io_req =3D qcom_spi_ecc_prepare_io_req_pipelined, + .finish_io_req =3D qcom_spi_ecc_finish_io_req_pipelined, +}; + +/* helper to configure location register values */ +static void qcom_spi_set_read_loc(struct qcom_nand_controller *snandc, int= cw, int reg, + int cw_offset, int read_size, int is_last_read_loc) +{ + int reg_base =3D NAND_READ_LOCATION_0; + int num_cw =3D snandc->qspi->num_cw; + + if (cw =3D=3D (num_cw - 1)) + reg_base =3D NAND_READ_LOCATION_LAST_CW_0; + + reg_base +=3D reg * 4; + + if (cw =3D=3D (num_cw - 1)) + return qcom_spi_set_read_loc_last(snandc, reg_base, cw_offset, + read_size, is_last_read_loc); + else + return qcom_spi_set_read_loc_first(snandc, reg_base, cw_offset, + read_size, is_last_read_loc); +} + +static void +qcom_spi_config_cw_read(struct qcom_nand_controller *snandc, bool use_ecc,= int cw) +{ + __le32 *reg =3D &snandc->regs->read_location0; + int num_cw =3D snandc->qspi->num_cw; + + qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_0, 4, NAND_BAM_NEXT_SG= L); + if (cw =3D=3D (num_cw - 1)) { + reg =3D &snandc->regs->read_location_last0; + qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4, + NAND_BAM_NEXT_SGL); + } + + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BA= M_NEXT_SGL); + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BA= M_NEXT_SGL); + + qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0); + qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1, + NAND_BAM_NEXT_SGL); +} + +static int qcom_spi_block_erase(struct qcom_nand_controller *snandc) +{ + struct qpic_ecc *ecc_cfg =3D snandc->qspi->ecc; + int ret; + + snandc->buf_count =3D 0; + snandc->buf_start =3D 0; + qcom_clear_read_regs(snandc); + qcom_clear_bam_transaction(snandc); + + snandc->regs->cmd =3D snandc->qspi->cmd; + snandc->regs->addr0 =3D snandc->qspi->addr1; + snandc->regs->addr1 =3D snandc->qspi->addr2; + snandc->regs->cfg0 =3D cpu_to_le32(ecc_cfg->cfg0_raw & ~(7 << CW_PER_PAGE= )); + snandc->regs->cfg1 =3D cpu_to_le32(ecc_cfg->cfg1_raw); + snandc->regs->exec =3D cpu_to_le32(1); + + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BA= M_NEXT_SGL); + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 2, NAND_B= AM_NEXT_SGL); + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BA= M_NEXT_SGL); + + ret =3D qcom_submit_descs(snandc); + if (ret) { + dev_err(snandc->dev, "failure to erase block\n"); + return ret; + } + + return 0; +} + +static void qcom_spi_config_single_cw_page_read(struct qcom_nand_controlle= r *snandc, + bool use_ecc, int cw) +{ + __le32 *reg =3D &snandc->regs->read_location0; + int num_cw =3D snandc->qspi->num_cw; + + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, + NAND_ERASED_CW_DETECT_CFG, 1, 0); + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, + NAND_ERASED_CW_DETECT_CFG, 1, + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL); + + if (cw =3D=3D (num_cw - 1)) { + reg =3D &snandc->regs->read_location_last0; + qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4, NAND_BA= M_NEXT_SGL); + } + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BA= M_NEXT_SGL); + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BA= M_NEXT_SGL); + + qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, 0); +} + +static int qcom_spi_read_last_cw(struct qcom_nand_controller *snandc, + const struct spi_mem_op *op) +{ + struct qpic_ecc *ecc_cfg =3D snandc->qspi->ecc; + struct mtd_info *mtd =3D snandc->qspi->mtd; + int size, ret =3D 0; + int col, bbpos; + u32 cfg0, cfg1, ecc_bch_cfg; + u32 num_cw =3D snandc->qspi->num_cw; + + qcom_clear_bam_transaction(snandc); + qcom_clear_read_regs(snandc); + + size =3D ecc_cfg->cw_size; + col =3D ecc_cfg->cw_size * (num_cw - 1); + + memset(snandc->data_buffer, 0xff, size); + snandc->regs->addr0 =3D (snandc->qspi->addr1 | cpu_to_le32(col)); + snandc->regs->addr1 =3D snandc->qspi->addr2; + + cfg0 =3D (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) | + 0 << CW_PER_PAGE; + cfg1 =3D ecc_cfg->cfg1_raw; + ecc_bch_cfg =3D 1 << ECC_CFG_ECC_DISABLE; + + snandc->regs->cmd =3D snandc->qspi->cmd; + snandc->regs->cfg0 =3D cpu_to_le32(cfg0); + snandc->regs->cfg1 =3D cpu_to_le32(cfg1); + snandc->regs->ecc_bch_cfg =3D cpu_to_le32(ecc_bch_cfg); + snandc->regs->clrflashstatus =3D cpu_to_le32(ecc_cfg->clrflashstatus); + snandc->regs->clrreadstatus =3D cpu_to_le32(ecc_cfg->clrreadstatus); + snandc->regs->exec =3D cpu_to_le32(1); + + qcom_spi_set_read_loc(snandc, num_cw - 1, 0, 0, ecc_cfg->cw_size, 1); + + qcom_spi_config_single_cw_page_read(snandc, false, num_cw - 1); + + qcom_read_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, size, 0); + + ret =3D qcom_submit_descs(snandc); + if (ret) { + dev_err(snandc->dev, "failed to read last cw\n"); + return ret; + } + + qcom_nandc_dev_to_mem(snandc, true); + u32 flash =3D le32_to_cpu(snandc->reg_read_buf[0]); + + if (flash & (FS_OP_ERR | FS_MPU_ERR)) + return -EIO; + + bbpos =3D mtd->writesize - ecc_cfg->cw_size * (num_cw - 1); + + if (snandc->data_buffer[bbpos] =3D=3D 0xff) + snandc->data_buffer[bbpos + 1] =3D 0xff; + if (snandc->data_buffer[bbpos] !=3D 0xff) + snandc->data_buffer[bbpos + 1] =3D snandc->data_buffer[bbpos]; + + memcpy(op->data.buf.in, snandc->data_buffer + bbpos, op->data.nbytes); + + return ret; +} + +static int qcom_spi_check_error(struct qcom_nand_controller *snandc, u8 *d= ata_buf, u8 *oob_buf) +{ + struct snandc_read_status *buf; + struct qpic_ecc *ecc_cfg =3D snandc->qspi->ecc; + int i, num_cw =3D snandc->qspi->num_cw; + bool flash_op_err =3D false, erased; + unsigned int max_bitflips =3D 0; + unsigned int uncorrectable_cws =3D 0; + + snandc->qspi->ecc_stats.failed =3D 0; + snandc->qspi->ecc_stats.corrected =3D 0; + + qcom_nandc_dev_to_mem(snandc, true); + buf =3D (struct snandc_read_status *)snandc->reg_read_buf; + + for (i =3D 0; i < num_cw; i++, buf++) { + u32 flash, buffer, erased_cw; + int data_len, oob_len; + + if (i =3D=3D (num_cw - 1)) { + data_len =3D NANDC_STEP_SIZE - ((num_cw - 1) << 2); + oob_len =3D num_cw << 2; + } else { + data_len =3D ecc_cfg->cw_data; + oob_len =3D 0; + } + + flash =3D le32_to_cpu(buf->snandc_flash); + buffer =3D le32_to_cpu(buf->snandc_buffer); + erased_cw =3D le32_to_cpu(buf->snandc_erased_cw); + + if ((flash & FS_OP_ERR) && (buffer & BS_UNCORRECTABLE_BIT)) { + if (ecc_cfg->bch_enabled) + erased =3D (erased_cw & ERASED_CW) =3D=3D ERASED_CW; + else + erased =3D false; + + if (!erased) + uncorrectable_cws |=3D BIT(i); + + } else if (flash & (FS_OP_ERR | FS_MPU_ERR)) { + flash_op_err =3D true; + } else { + unsigned int stat; + + stat =3D buffer & BS_CORRECTABLE_ERR_MSK; + snandc->qspi->ecc_stats.corrected +=3D stat; + max_bitflips =3D max(max_bitflips, stat); + } + + if (data_buf) + data_buf +=3D data_len; + if (oob_buf) + oob_buf +=3D oob_len + ecc_cfg->bytes; + } + + if (flash_op_err) + return -EIO; + + if (!uncorrectable_cws) + snandc->qspi->ecc_stats.bitflips =3D max_bitflips; + else + snandc->qspi->ecc_stats.failed++; + + return 0; +} + +static int qcom_spi_check_raw_flash_errors(struct qcom_nand_controller *sn= andc, int cw_cnt) +{ + int i; + + qcom_nandc_dev_to_mem(snandc, true); + + for (i =3D 0; i < cw_cnt; i++) { + u32 flash =3D le32_to_cpu(snandc->reg_read_buf[i]); + + if (flash & (FS_OP_ERR | FS_MPU_ERR)) + return -EIO; + } + + return 0; +} + +static int qcom_spi_read_cw_raw(struct qcom_nand_controller *snandc, u8 *d= ata_buf, + u8 *oob_buf, int cw) +{ + struct qpic_ecc *ecc_cfg =3D snandc->qspi->ecc; + struct mtd_info *mtd =3D snandc->qspi->mtd; + int data_size1, data_size2, oob_size1, oob_size2; + int ret, reg_off =3D FLASH_BUF_ACC, read_loc =3D 0; + int raw_cw =3D cw; + u32 cfg0, cfg1, ecc_bch_cfg, num_cw =3D snandc->qspi->num_cw; + int col; + + snandc->buf_count =3D 0; + snandc->buf_start =3D 0; + qcom_clear_read_regs(snandc); + qcom_clear_bam_transaction(snandc); + raw_cw =3D num_cw - 1; + + cfg0 =3D (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) | + 0 << CW_PER_PAGE; + cfg1 =3D ecc_cfg->cfg1_raw; + ecc_bch_cfg =3D ECC_CFG_ECC_DISABLE; + + col =3D ecc_cfg->cw_size * cw; + + snandc->regs->addr0 =3D (snandc->qspi->addr1 | cpu_to_le32(col)); + snandc->regs->addr1 =3D snandc->qspi->addr2; + snandc->regs->cmd =3D snandc->qspi->cmd; + snandc->regs->cfg0 =3D cpu_to_le32(cfg0); + snandc->regs->cfg1 =3D cpu_to_le32(cfg1); + snandc->regs->ecc_bch_cfg =3D cpu_to_le32(ecc_bch_cfg); + snandc->regs->clrflashstatus =3D cpu_to_le32(ecc_cfg->clrflashstatus); + snandc->regs->clrreadstatus =3D cpu_to_le32(ecc_cfg->clrreadstatus); + snandc->regs->exec =3D cpu_to_le32(1); + + qcom_spi_set_read_loc(snandc, raw_cw, 0, 0, ecc_cfg->cw_size, 1); + + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); + qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_= CFG, 1, 0); + + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, + NAND_ERASED_CW_DETECT_CFG, 1, 0); + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, + NAND_ERASED_CW_DETECT_CFG, 1, + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL); + + data_size1 =3D mtd->writesize - ecc_cfg->cw_size * (num_cw - 1); + oob_size1 =3D ecc_cfg->bbm_size; + + if (cw =3D=3D (num_cw - 1)) { + data_size2 =3D NANDC_STEP_SIZE - data_size1 - + ((num_cw - 1) * 4); + oob_size2 =3D (num_cw * 4) + ecc_cfg->ecc_bytes_hw + + ecc_cfg->spare_bytes; + } else { + data_size2 =3D ecc_cfg->cw_data - data_size1; + oob_size2 =3D ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; + } + + qcom_spi_set_read_loc(snandc, cw, 0, read_loc, data_size1, 0); + read_loc +=3D data_size1; + + qcom_spi_set_read_loc(snandc, cw, 1, read_loc, oob_size1, 0); + read_loc +=3D oob_size1; + + qcom_spi_set_read_loc(snandc, cw, 2, read_loc, data_size2, 0); + read_loc +=3D data_size2; + + qcom_spi_set_read_loc(snandc, cw, 3, read_loc, oob_size2, 1); + + qcom_spi_config_cw_read(snandc, false, raw_cw); + + qcom_read_data_dma(snandc, reg_off, data_buf, data_size1, 0); + reg_off +=3D data_size1; + + qcom_read_data_dma(snandc, reg_off, oob_buf, oob_size1, 0); + reg_off +=3D oob_size1; + + qcom_read_data_dma(snandc, reg_off, data_buf + data_size1, data_size2, 0); + reg_off +=3D data_size2; + + qcom_read_data_dma(snandc, reg_off, oob_buf + oob_size1, oob_size2, 0); + + ret =3D qcom_submit_descs(snandc); + if (ret) { + dev_err(snandc->dev, "failure to read raw cw %d\n", cw); + return ret; + } + + return qcom_spi_check_raw_flash_errors(snandc, 1); +} + +static int qcom_spi_read_page_raw(struct qcom_nand_controller *snandc, + const struct spi_mem_op *op) +{ + struct qpic_ecc *ecc_cfg =3D snandc->qspi->ecc; + u8 *data_buf =3D NULL, *oob_buf =3D NULL; + int ret, cw; + u32 num_cw =3D snandc->qspi->num_cw; + + if (snandc->qspi->page_rw) + data_buf =3D op->data.buf.in; + + oob_buf =3D snandc->qspi->oob_buf; + memset(oob_buf, 0xff, OOB_BUF_SIZE); + + for (cw =3D 0; cw < num_cw; cw++) { + ret =3D qcom_spi_read_cw_raw(snandc, data_buf, oob_buf, cw); + if (ret) + return ret; + + if (data_buf) + data_buf +=3D ecc_cfg->cw_data; + if (oob_buf) + oob_buf +=3D ecc_cfg->bytes; + } + + return 0; +} + +static int qcom_spi_read_page_ecc(struct qcom_nand_controller *snandc, + const struct spi_mem_op *op) +{ + struct qpic_ecc *ecc_cfg =3D snandc->qspi->ecc; + u8 *data_buf =3D NULL, *data_buf_start, *oob_buf =3D NULL, *oob_buf_start; + int ret, i; + u32 cfg0, cfg1, ecc_bch_cfg, num_cw =3D snandc->qspi->num_cw; + + data_buf =3D op->data.buf.in; + data_buf_start =3D data_buf; + + oob_buf =3D snandc->qspi->oob_buf; + oob_buf_start =3D oob_buf; + + snandc->buf_count =3D 0; + snandc->buf_start =3D 0; + qcom_clear_read_regs(snandc); + + cfg0 =3D (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) | + (num_cw - 1) << CW_PER_PAGE; + cfg1 =3D ecc_cfg->cfg1; + ecc_bch_cfg =3D ecc_cfg->ecc_bch_cfg; + + snandc->regs->addr0 =3D snandc->qspi->addr1; + snandc->regs->addr1 =3D snandc->qspi->addr2; + snandc->regs->cmd =3D snandc->qspi->cmd; + snandc->regs->cfg0 =3D cpu_to_le32(cfg0); + snandc->regs->cfg1 =3D cpu_to_le32(cfg1); + snandc->regs->ecc_bch_cfg =3D cpu_to_le32(ecc_bch_cfg); + snandc->regs->clrflashstatus =3D cpu_to_le32(ecc_cfg->clrflashstatus); + snandc->regs->clrreadstatus =3D cpu_to_le32(ecc_cfg->clrreadstatus); + snandc->regs->exec =3D cpu_to_le32(1); + + qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1); + + qcom_clear_bam_transaction(snandc); + + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, + NAND_ERASED_CW_DETECT_CFG, 1, 0); + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, + NAND_ERASED_CW_DETECT_CFG, 1, + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL); + + for (i =3D 0; i < num_cw; i++) { + int data_size, oob_size; + + if (i =3D=3D (num_cw - 1)) { + data_size =3D 512 - ((num_cw - 1) << 2); + oob_size =3D (num_cw << 2) + ecc_cfg->ecc_bytes_hw + + ecc_cfg->spare_bytes; + } else { + data_size =3D ecc_cfg->cw_data; + oob_size =3D ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; + } + + if (data_buf && oob_buf) { + qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 0); + qcom_spi_set_read_loc(snandc, i, 1, data_size, oob_size, 1); + } else if (data_buf) { + qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 1); + } else { + qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1); + } + + qcom_spi_config_cw_read(snandc, true, i); + + if (data_buf) + qcom_read_data_dma(snandc, FLASH_BUF_ACC, data_buf, + data_size, 0); + if (oob_buf) { + int j; + + for (j =3D 0; j < ecc_cfg->bbm_size; j++) + *oob_buf++ =3D 0xff; + + qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size, + oob_buf, oob_size, 0); + } + + if (data_buf) + data_buf +=3D data_size; + if (oob_buf) + oob_buf +=3D oob_size; + } + + ret =3D qcom_submit_descs(snandc); + if (ret) { + dev_err(snandc->dev, "failure to read page\n"); + return ret; + } + + return qcom_spi_check_error(snandc, data_buf_start, oob_buf_start); +} + +static int qcom_spi_read_page_oob(struct qcom_nand_controller *snandc, + const struct spi_mem_op *op) +{ + struct qpic_ecc *ecc_cfg =3D snandc->qspi->ecc; + u8 *data_buf =3D NULL, *data_buf_start, *oob_buf =3D NULL, *oob_buf_start; + int ret, i; + u32 cfg0, cfg1, ecc_bch_cfg, num_cw =3D snandc->qspi->num_cw; + + oob_buf =3D op->data.buf.in; + oob_buf_start =3D oob_buf; + + data_buf_start =3D data_buf; + + snandc->buf_count =3D 0; + snandc->buf_start =3D 0; + qcom_clear_read_regs(snandc); + qcom_clear_bam_transaction(snandc); + + cfg0 =3D (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) | + (num_cw - 1) << CW_PER_PAGE; + cfg1 =3D ecc_cfg->cfg1; + ecc_bch_cfg =3D ecc_cfg->ecc_bch_cfg; + + snandc->regs->addr0 =3D snandc->qspi->addr1; + snandc->regs->addr1 =3D snandc->qspi->addr2; + snandc->regs->cmd =3D snandc->qspi->cmd; + snandc->regs->cfg0 =3D cpu_to_le32(cfg0); + snandc->regs->cfg1 =3D cpu_to_le32(cfg1); + snandc->regs->ecc_bch_cfg =3D cpu_to_le32(ecc_bch_cfg); + snandc->regs->clrflashstatus =3D cpu_to_le32(ecc_cfg->clrflashstatus); + snandc->regs->clrreadstatus =3D cpu_to_le32(ecc_cfg->clrreadstatus); + snandc->regs->exec =3D cpu_to_le32(1); + + qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1); + + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, + NAND_ERASED_CW_DETECT_CFG, 1, 0); + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, + NAND_ERASED_CW_DETECT_CFG, 1, + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL); + + for (i =3D 0; i < num_cw; i++) { + int data_size, oob_size; + + if (i =3D=3D (num_cw - 1)) { + data_size =3D NANDC_STEP_SIZE - ((num_cw - 1) << 2); + oob_size =3D (num_cw << 2) + ecc_cfg->ecc_bytes_hw + + ecc_cfg->spare_bytes; + } else { + data_size =3D ecc_cfg->cw_data; + oob_size =3D ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; + } + + qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1); + + qcom_spi_config_cw_read(snandc, true, i); + + if (oob_buf) { + int j; + + for (j =3D 0; j < ecc_cfg->bbm_size; j++) + *oob_buf++ =3D 0xff; + + qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size, + oob_buf, oob_size, 0); + } + + if (oob_buf) + oob_buf +=3D oob_size; + } + + ret =3D qcom_submit_descs(snandc); + if (ret) { + dev_err(snandc->dev, "failure to read oob\n"); + return ret; + } + + return qcom_spi_check_error(snandc, data_buf_start, oob_buf_start); +} + +static int qcom_spi_read_page(struct qcom_nand_controller *snandc, + const struct spi_mem_op *op) +{ + if (snandc->qspi->page_rw && snandc->qspi->raw_rw) + return qcom_spi_read_page_raw(snandc, op); + + if (snandc->qspi->page_rw) + return qcom_spi_read_page_ecc(snandc, op); + + if (snandc->qspi->oob_rw && snandc->qspi->raw_rw) + return qcom_spi_read_last_cw(snandc, op); + + if (snandc->qspi->oob_rw) + return qcom_spi_read_page_oob(snandc, op); + + return 0; +} + +static void qcom_spi_config_page_write(struct qcom_nand_controller *snandc) +{ + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); + qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_= CFG, + 1, NAND_BAM_NEXT_SGL); +} + +static void qcom_spi_config_cw_write(struct qcom_nand_controller *snandc) +{ + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BA= M_NEXT_SGL); + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BA= M_NEXT_SGL); + qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); + + qcom_write_reg_dma(snandc, &snandc->regs->clrflashstatus, NAND_FLASH_STAT= US, 1, 0); + qcom_write_reg_dma(snandc, &snandc->regs->clrreadstatus, NAND_READ_STATUS= , 1, + NAND_BAM_NEXT_SGL); +} + +static int qcom_spi_program_raw(struct qcom_nand_controller *snandc, + const struct spi_mem_op *op) +{ + struct qpic_ecc *ecc_cfg =3D snandc->qspi->ecc; + struct mtd_info *mtd =3D snandc->qspi->mtd; + u8 *data_buf =3D NULL, *oob_buf =3D NULL; + int i, ret; + int num_cw =3D snandc->qspi->num_cw; + u32 cfg0, cfg1, ecc_bch_cfg; + + cfg0 =3D (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) | + (num_cw - 1) << CW_PER_PAGE; + cfg1 =3D ecc_cfg->cfg1_raw; + ecc_bch_cfg =3D ECC_CFG_ECC_DISABLE; + + data_buf =3D snandc->qspi->data_buf; + + oob_buf =3D snandc->qspi->oob_buf; + memset(oob_buf, 0xff, OOB_BUF_SIZE); + + snandc->buf_count =3D 0; + snandc->buf_start =3D 0; + qcom_clear_read_regs(snandc); + qcom_clear_bam_transaction(snandc); + + snandc->regs->addr0 =3D snandc->qspi->addr1; + snandc->regs->addr1 =3D snandc->qspi->addr2; + snandc->regs->cmd =3D snandc->qspi->cmd; + snandc->regs->cfg0 =3D cpu_to_le32(cfg0); + snandc->regs->cfg1 =3D cpu_to_le32(cfg1); + snandc->regs->ecc_bch_cfg =3D cpu_to_le32(ecc_bch_cfg); + snandc->regs->clrflashstatus =3D cpu_to_le32(ecc_cfg->clrflashstatus); + snandc->regs->clrreadstatus =3D cpu_to_le32(ecc_cfg->clrreadstatus); + snandc->regs->exec =3D cpu_to_le32(1); + + qcom_spi_config_page_write(snandc); + + for (i =3D 0; i < num_cw; i++) { + int data_size1, data_size2, oob_size1, oob_size2; + int reg_off =3D FLASH_BUF_ACC; + + data_size1 =3D mtd->writesize - ecc_cfg->cw_size * (num_cw - 1); + oob_size1 =3D ecc_cfg->bbm_size; + + if ((i =3D=3D (num_cw - 1))) { + data_size2 =3D NANDC_STEP_SIZE - data_size1 - + ((num_cw - 1) << 2); + oob_size2 =3D (num_cw << 2) + ecc_cfg->ecc_bytes_hw + + ecc_cfg->spare_bytes; + } else { + data_size2 =3D ecc_cfg->cw_data - data_size1; + oob_size2 =3D ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; + } + + qcom_write_data_dma(snandc, reg_off, data_buf, data_size1, + NAND_BAM_NO_EOT); + reg_off +=3D data_size1; + data_buf +=3D data_size1; + + qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size1, + NAND_BAM_NO_EOT); + oob_buf +=3D oob_size1; + reg_off +=3D oob_size1; + + qcom_write_data_dma(snandc, reg_off, data_buf, data_size2, + NAND_BAM_NO_EOT); + reg_off +=3D data_size2; + data_buf +=3D data_size2; + + qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size2, 0); + oob_buf +=3D oob_size2; + + qcom_spi_config_cw_write(snandc); + } + + ret =3D qcom_submit_descs(snandc); + if (ret) { + dev_err(snandc->dev, "failure to write raw page\n"); + return ret; + } + + return 0; +} + +static int qcom_spi_program_ecc(struct qcom_nand_controller *snandc, + const struct spi_mem_op *op) +{ + struct qpic_ecc *ecc_cfg =3D snandc->qspi->ecc; + u8 *data_buf =3D NULL, *oob_buf =3D NULL; + int i, ret; + int num_cw =3D snandc->qspi->num_cw; + u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg; + + cfg0 =3D (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) | + (num_cw - 1) << CW_PER_PAGE; + cfg1 =3D ecc_cfg->cfg1; + ecc_bch_cfg =3D ecc_cfg->ecc_bch_cfg; + ecc_buf_cfg =3D ecc_cfg->ecc_buf_cfg; + + if (snandc->qspi->data_buf) + data_buf =3D snandc->qspi->data_buf; + + oob_buf =3D snandc->qspi->oob_buf; + + snandc->buf_count =3D 0; + snandc->buf_start =3D 0; + qcom_clear_read_regs(snandc); + qcom_clear_bam_transaction(snandc); + + snandc->regs->addr0 =3D snandc->qspi->addr1; + snandc->regs->addr1 =3D snandc->qspi->addr2; + snandc->regs->cmd =3D snandc->qspi->cmd; + snandc->regs->cfg0 =3D cpu_to_le32(cfg0); + snandc->regs->cfg1 =3D cpu_to_le32(cfg1); + snandc->regs->ecc_bch_cfg =3D cpu_to_le32(ecc_bch_cfg); + snandc->regs->ecc_buf_cfg =3D cpu_to_le32(ecc_buf_cfg); + snandc->regs->exec =3D cpu_to_le32(1); + + qcom_spi_config_page_write(snandc); + + for (i =3D 0; i < num_cw; i++) { + int data_size, oob_size; + + if (i =3D=3D (num_cw - 1)) { + data_size =3D NANDC_STEP_SIZE - ((num_cw - 1) << 2); + oob_size =3D (num_cw << 2) + ecc_cfg->ecc_bytes_hw + + ecc_cfg->spare_bytes; + } else { + data_size =3D ecc_cfg->cw_data; + oob_size =3D ecc_cfg->bytes; + } + + if (data_buf) + qcom_write_data_dma(snandc, FLASH_BUF_ACC, data_buf, data_size, + i =3D=3D (num_cw - 1) ? NAND_BAM_NO_EOT : 0); + + if (i =3D=3D (num_cw - 1)) { + if (oob_buf) { + oob_buf +=3D ecc_cfg->bbm_size; + qcom_write_data_dma(snandc, FLASH_BUF_ACC + data_size, + oob_buf, oob_size, 0); + } + } + + qcom_spi_config_cw_write(snandc); + + if (data_buf) + data_buf +=3D data_size; + if (oob_buf) + oob_buf +=3D oob_size; + } + + ret =3D qcom_submit_descs(snandc); + if (ret) { + dev_err(snandc->dev, "failure to write page\n"); + return ret; + } + + return 0; +} + +static int qcom_spi_program_oob(struct qcom_nand_controller *snandc, + const struct spi_mem_op *op) +{ + struct qpic_ecc *ecc_cfg =3D snandc->qspi->ecc; + u8 *oob_buf =3D NULL; + int ret, col, data_size, oob_size; + int num_cw =3D snandc->qspi->num_cw; + u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg; + + cfg0 =3D (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) | + (num_cw - 1) << CW_PER_PAGE; + cfg1 =3D ecc_cfg->cfg1; + ecc_bch_cfg =3D ecc_cfg->ecc_bch_cfg; + ecc_buf_cfg =3D ecc_cfg->ecc_buf_cfg; + + col =3D ecc_cfg->cw_size * (num_cw - 1); + + oob_buf =3D snandc->qspi->data_buf; + + snandc->buf_count =3D 0; + snandc->buf_start =3D 0; + qcom_clear_read_regs(snandc); + qcom_clear_bam_transaction(snandc); + snandc->regs->addr0 =3D (snandc->qspi->addr1 | cpu_to_le32(col)); + snandc->regs->addr1 =3D snandc->qspi->addr2; + snandc->regs->cmd =3D snandc->qspi->cmd; + snandc->regs->cfg0 =3D cpu_to_le32(cfg0); + snandc->regs->cfg1 =3D cpu_to_le32(cfg1); + snandc->regs->ecc_bch_cfg =3D cpu_to_le32(ecc_bch_cfg); + snandc->regs->ecc_buf_cfg =3D cpu_to_le32(ecc_buf_cfg); + snandc->regs->exec =3D cpu_to_le32(1); + + /* calculate the data and oob size for the last codeword/step */ + data_size =3D NANDC_STEP_SIZE - ((num_cw - 1) << 2); + oob_size =3D snandc->qspi->mtd->oobavail; + + memset(snandc->data_buffer, 0xff, ecc_cfg->cw_data); + /* override new oob content to last codeword */ + mtd_ooblayout_get_databytes(snandc->qspi->mtd, snandc->data_buffer + data= _size, + oob_buf, 0, snandc->qspi->mtd->oobavail); + qcom_spi_config_page_write(snandc); + qcom_write_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, data_size= + oob_size, 0); + qcom_spi_config_cw_write(snandc); + + ret =3D qcom_submit_descs(snandc); + if (ret) { + dev_err(snandc->dev, "failure to write oob\n"); + return ret; + } + + return 0; +} + +static int qcom_spi_program_execute(struct qcom_nand_controller *snandc, + const struct spi_mem_op *op) +{ + if (snandc->qspi->page_rw && snandc->qspi->raw_rw) + return qcom_spi_program_raw(snandc, op); + + if (snandc->qspi->page_rw) + return qcom_spi_program_ecc(snandc, op); + + if (snandc->qspi->oob_rw) + return qcom_spi_program_oob(snandc, op); + + return 0; +} + +static u32 qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 o= pcode) +{ + u32 cmd =3D 0x0; + + switch (opcode) { + case SPINAND_RESET: + cmd =3D (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE); + break; + case SPINAND_READID: + cmd =3D (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID); + break; + case SPINAND_GET_FEATURE: + cmd =3D (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE); + break; + case SPINAND_SET_FEATURE: + cmd =3D (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE | + QPIC_SET_FEATURE); + break; + case SPINAND_READ: + if (snandc->qspi->raw_rw) { + cmd =3D (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | + SPI_WP | SPI_HOLD | OP_PAGE_READ); + } else { + cmd =3D (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | + SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC); + } + + break; + case SPINAND_ERASE: + cmd =3D OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP | + SPI_HOLD | SPI_TRANSFER_MODE_x1; + break; + case SPINAND_WRITE_EN: + cmd =3D SPINAND_WRITE_EN; + break; + case SPINAND_PROGRAM_EXECUTE: + cmd =3D (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | + SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE); + break; + case SPINAND_PROGRAM_LOAD: + cmd =3D SPINAND_PROGRAM_LOAD; + break; + default: + dev_err(snandc->dev, "Opcode not supported: %u\n", opcode); + return -EOPNOTSUPP; + } + + return cmd; +} + +static int qcom_spi_write_page(struct qcom_nand_controller *snandc, + const struct spi_mem_op *op) +{ + struct qpic_snand_op s_op =3D {}; + u32 cmd; + + cmd =3D qcom_spi_cmd_mapping(snandc, op->cmd.opcode); + if (cmd < 0) + return cmd; + + s_op.cmd_reg =3D cmd; + + if (op->cmd.opcode =3D=3D SPINAND_PROGRAM_LOAD) + snandc->qspi->data_buf =3D (u8 *)op->data.buf.out; + + return 0; +} + +static int qcom_spi_send_cmdaddr(struct qcom_nand_controller *snandc, + const struct spi_mem_op *op) +{ + struct qpic_snand_op s_op =3D {}; + u32 cmd; + int ret, opcode; + + cmd =3D qcom_spi_cmd_mapping(snandc, op->cmd.opcode); + if (cmd < 0) + return cmd; + + s_op.cmd_reg =3D cmd; + s_op.addr1_reg =3D op->addr.val; + s_op.addr2_reg =3D 0; + + opcode =3D op->cmd.opcode; + + switch (opcode) { + case SPINAND_WRITE_EN: + return 0; + case SPINAND_PROGRAM_EXECUTE: + s_op.addr1_reg =3D op->addr.val << 16; + s_op.addr2_reg =3D op->addr.val >> 16 & 0xff; + snandc->qspi->addr1 =3D cpu_to_le32(s_op.addr1_reg); + snandc->qspi->addr2 =3D cpu_to_le32(s_op.addr2_reg); + snandc->qspi->cmd =3D cpu_to_le32(cmd); + return qcom_spi_program_execute(snandc, op); + case SPINAND_READ: + s_op.addr1_reg =3D (op->addr.val << 16); + s_op.addr2_reg =3D op->addr.val >> 16 & 0xff; + snandc->qspi->addr1 =3D cpu_to_le32(s_op.addr1_reg); + snandc->qspi->addr2 =3D cpu_to_le32(s_op.addr2_reg); + snandc->qspi->cmd =3D cpu_to_le32(cmd); + return 0; + case SPINAND_ERASE: + s_op.addr2_reg =3D (op->addr.val >> 16) & 0xffff; + s_op.addr1_reg =3D op->addr.val; + snandc->qspi->addr1 =3D cpu_to_le32(s_op.addr1_reg << 16); + snandc->qspi->addr2 =3D cpu_to_le32(s_op.addr2_reg); + snandc->qspi->cmd =3D cpu_to_le32(cmd); + qcom_spi_block_erase(snandc); + return 0; + default: + break; + } + + snandc->buf_count =3D 0; + snandc->buf_start =3D 0; + qcom_clear_read_regs(snandc); + qcom_clear_bam_transaction(snandc); + + snandc->regs->cmd =3D cpu_to_le32(s_op.cmd_reg); + snandc->regs->exec =3D cpu_to_le32(1); + snandc->regs->addr0 =3D cpu_to_le32(s_op.addr1_reg); + snandc->regs->addr1 =3D cpu_to_le32(s_op.addr2_reg); + + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BA= M_NEXT_SGL); + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BA= M_NEXT_SGL); + + ret =3D qcom_submit_descs(snandc); + if (ret) + dev_err(snandc->dev, "failure in submitting cmd descriptor\n"); + + return ret; +} + +static int qcom_spi_io_op(struct qcom_nand_controller *snandc, const struc= t spi_mem_op *op) +{ + int ret, val, opcode; + bool copy =3D false, copy_ftr =3D false; + + ret =3D qcom_spi_send_cmdaddr(snandc, op); + if (ret) + return ret; + + snandc->buf_count =3D 0; + snandc->buf_start =3D 0; + qcom_clear_read_regs(snandc); + qcom_clear_bam_transaction(snandc); + opcode =3D op->cmd.opcode; + + switch (opcode) { + case SPINAND_READID: + snandc->buf_count =3D 4; + qcom_read_reg_dma(snandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL); + copy =3D true; + break; + case SPINAND_GET_FEATURE: + snandc->buf_count =3D 4; + qcom_read_reg_dma(snandc, NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL); + copy_ftr =3D true; + break; + case SPINAND_SET_FEATURE: + snandc->regs->flash_feature =3D cpu_to_le32(*(u32 *)op->data.buf.out); + qcom_write_reg_dma(snandc, &snandc->regs->flash_feature, + NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL); + break; + case SPINAND_PROGRAM_EXECUTE: + case SPINAND_WRITE_EN: + case SPINAND_RESET: + case SPINAND_ERASE: + case SPINAND_READ: + return 0; + default: + return -EOPNOTSUPP; + } + + ret =3D qcom_submit_descs(snandc); + if (ret) + dev_err(snandc->dev, "failure in submitting descriptor for:%d\n", opcode= ); + + if (copy) { + qcom_nandc_dev_to_mem(snandc, true); + memcpy(op->data.buf.in, snandc->reg_read_buf, snandc->buf_count); + } + + if (copy_ftr) { + qcom_nandc_dev_to_mem(snandc, true); + val =3D le32_to_cpu(*(__le32 *)snandc->reg_read_buf); + val >>=3D 8; + memcpy(op->data.buf.in, &val, snandc->buf_count); + } + + return ret; +} + +static bool qcom_spi_is_page_op(const struct spi_mem_op *op) +{ + if (op->addr.buswidth !=3D 1 && op->addr.buswidth !=3D 2 && op->addr.busw= idth !=3D 4) + return false; + + if (op->data.dir =3D=3D SPI_MEM_DATA_IN) { + if (op->addr.buswidth =3D=3D 4 && op->data.buswidth =3D=3D 4) + return true; + + if (op->addr.nbytes =3D=3D 2 && op->addr.buswidth =3D=3D 1) + return true; + + } else if (op->data.dir =3D=3D SPI_MEM_DATA_OUT) { + if (op->data.buswidth =3D=3D 4) + return true; + if (op->addr.nbytes =3D=3D 2 && op->addr.buswidth =3D=3D 1) + return true; + } + + return false; +} + +static bool qcom_spi_supports_op(struct spi_mem *mem, const struct spi_mem= _op *op) +{ + if (!spi_mem_default_supports_op(mem, op)) + return false; + + if (op->cmd.nbytes !=3D 1 || op->cmd.buswidth !=3D 1) + return false; + + if (qcom_spi_is_page_op(op)) + return true; + + return ((!op->addr.nbytes || op->addr.buswidth =3D=3D 1) && + (!op->dummy.nbytes || op->dummy.buswidth =3D=3D 1) && + (!op->data.nbytes || op->data.buswidth =3D=3D 1)); +} + +static int qcom_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *= op) +{ + struct qcom_nand_controller *snandc =3D spi_controller_get_devdata(mem->s= pi->controller); + + dev_dbg(snandc->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opco= de, + op->addr.val, op->addr.buswidth, op->addr.nbytes, + op->data.buswidth, op->data.nbytes); + + if (qcom_spi_is_page_op(op)) { + if (op->data.dir =3D=3D SPI_MEM_DATA_IN) + return qcom_spi_read_page(snandc, op); + if (op->data.dir =3D=3D SPI_MEM_DATA_OUT) + return qcom_spi_write_page(snandc, op); + } else { + return qcom_spi_io_op(snandc, op); + } + + return 0; +} + +static const struct spi_controller_mem_ops qcom_spi_mem_ops =3D { + .supports_op =3D qcom_spi_supports_op, + .exec_op =3D qcom_spi_exec_op, +}; + +static const struct spi_controller_mem_caps qcom_spi_mem_caps =3D { + .ecc =3D true, +}; + +static int qcom_spi_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct spi_controller *ctlr; + struct qcom_nand_controller *snandc; + struct qpic_spi_nand *qspi; + struct qpic_ecc *ecc; + struct resource *res; + const void *dev_data; + int ret; + + ecc =3D devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); + if (!ecc) + return -ENOMEM; + + qspi =3D devm_kzalloc(dev, sizeof(*qspi), GFP_KERNEL); + if (!qspi) + return -ENOMEM; + + ctlr =3D __devm_spi_alloc_controller(dev, sizeof(*snandc), false); + if (!ctlr) + return -ENOMEM; + + platform_set_drvdata(pdev, ctlr); + + snandc =3D spi_controller_get_devdata(ctlr); + qspi->snandc =3D snandc; + + snandc->dev =3D dev; + snandc->qspi =3D qspi; + snandc->qspi->ctlr =3D ctlr; + snandc->qspi->ecc =3D ecc; + + dev_data =3D of_device_get_match_data(dev); + if (!dev_data) { + dev_err(&pdev->dev, "failed to get device data\n"); + return -ENODEV; + } + + snandc->props =3D dev_data; + snandc->dev =3D &pdev->dev; + + snandc->core_clk =3D devm_clk_get(dev, "core"); + if (IS_ERR(snandc->core_clk)) + return PTR_ERR(snandc->core_clk); + + snandc->aon_clk =3D devm_clk_get(dev, "aon"); + if (IS_ERR(snandc->aon_clk)) + return PTR_ERR(snandc->aon_clk); + + snandc->qspi->iomacro_clk =3D devm_clk_get(dev, "iom"); + if (IS_ERR(snandc->qspi->iomacro_clk)) + return PTR_ERR(snandc->qspi->iomacro_clk); + + snandc->base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(snandc->base)) + return PTR_ERR(snandc->base); + + snandc->base_phys =3D res->start; + snandc->base_dma =3D dma_map_resource(dev, res->start, resource_size(res), + DMA_BIDIRECTIONAL, 0); + if (dma_mapping_error(dev, snandc->base_dma)) + return -ENXIO; + + ret =3D clk_prepare_enable(snandc->core_clk); + if (ret) + goto err_dis_core_clk; + + ret =3D clk_prepare_enable(snandc->aon_clk); + if (ret) + goto err_dis_aon_clk; + + ret =3D clk_prepare_enable(snandc->qspi->iomacro_clk); + if (ret) + goto err_dis_iom_clk; + + ret =3D qcom_nandc_alloc(snandc); + if (ret) + goto err_snand_alloc; + + ret =3D qcom_spi_init(snandc); + if (ret) + goto err_spi_init; + + /* setup ECC engine */ + snandc->qspi->ecc_eng.dev =3D &pdev->dev; + snandc->qspi->ecc_eng.integration =3D NAND_ECC_ENGINE_INTEGRATION_PIPELIN= ED; + snandc->qspi->ecc_eng.ops =3D &qcom_spi_ecc_engine_ops_pipelined; + snandc->qspi->ecc_eng.priv =3D snandc; + + ret =3D nand_ecc_register_on_host_hw_engine(&snandc->qspi->ecc_eng); + if (ret) { + dev_err(&pdev->dev, "failed to register ecc engine:%d\n", ret); + goto err_spi_init; + } + + ctlr->num_chipselect =3D QPIC_QSPI_NUM_CS; + ctlr->mem_ops =3D &qcom_spi_mem_ops; + ctlr->mem_caps =3D &qcom_spi_mem_caps; + ctlr->dev.of_node =3D pdev->dev.of_node; + ctlr->mode_bits =3D SPI_TX_DUAL | SPI_RX_DUAL | + SPI_TX_QUAD | SPI_RX_QUAD; + + ret =3D spi_register_controller(ctlr); + if (ret) { + dev_err(&pdev->dev, "spi_register_controller failed.\n"); + goto err_spi_init; + } + + return 0; + +err_spi_init: + qcom_nandc_unalloc(snandc); +err_snand_alloc: + clk_disable_unprepare(snandc->qspi->iomacro_clk); +err_dis_iom_clk: + clk_disable_unprepare(snandc->aon_clk); +err_dis_aon_clk: + clk_disable_unprepare(snandc->core_clk); +err_dis_core_clk: + dma_unmap_resource(dev, res->start, resource_size(res), + DMA_BIDIRECTIONAL, 0); + return ret; +} + +static void qcom_spi_remove(struct platform_device *pdev) +{ + struct spi_controller *ctlr =3D platform_get_drvdata(pdev); + struct qcom_nand_controller *snandc =3D spi_controller_get_devdata(ctlr); + struct resource *res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + + spi_unregister_controller(ctlr); + + qcom_nandc_unalloc(snandc); + + clk_disable_unprepare(snandc->aon_clk); + clk_disable_unprepare(snandc->core_clk); + clk_disable_unprepare(snandc->qspi->iomacro_clk); + + dma_unmap_resource(&pdev->dev, snandc->base_dma, resource_size(res), + DMA_BIDIRECTIONAL, 0); +} + +static const struct qcom_nandc_props ipq9574_snandc_props =3D { + .dev_cmd_reg_start =3D 0x7000, + .supports_bam =3D true, +}; + +static const struct of_device_id qcom_snandc_of_match[] =3D { + { + .compatible =3D "qcom,spi-qpic-snand", + .data =3D &ipq9574_snandc_props, + }, + {} +} +MODULE_DEVICE_TABLE(of, qcom_snandc_of_match); + +static struct platform_driver qcom_spi_driver =3D { + .driver =3D { + .name =3D "qcom_snand", + .of_match_table =3D qcom_snandc_of_match, + }, + .probe =3D qcom_spi_probe, + .remove =3D qcom_spi_remove, +}; +module_platform_driver(qcom_spi_driver); + +MODULE_DESCRIPTION("SPI driver for QPIC QSPI cores"); +MODULE_AUTHOR("Md Sadre Alam "); +MODULE_LICENSE("GPL"); + diff --git a/include/linux/mtd/nand-qpic-common.h b/include/linux/mtd/nand-= qpic-common.h index e79c79775eb8..7dba89654d6c 100644 --- a/include/linux/mtd/nand-qpic-common.h +++ b/include/linux/mtd/nand-qpic-common.h @@ -322,6 +322,10 @@ struct nandc_regs { __le32 read_location_last1; __le32 read_location_last2; __le32 read_location_last3; + __le32 spi_cfg; + __le32 num_addr_cycle; + __le32 busy_wait_cnt; + __le32 flash_feature; =20 __le32 erased_cw_detect_cfg_clr; __le32 erased_cw_detect_cfg_set; @@ -336,6 +340,7 @@ struct nandc_regs { * * @core_clk: controller clock * @aon_clk: another controller clock + * @iomacro_clk: io macro clock * * @regs: a contiguous chunk of memory for DMA register * writes. contains the register values to be @@ -345,6 +350,7 @@ struct nandc_regs { * initialized via DT match data * * @controller: base controller structure + * @qspi: qpic spi structure * @host_list: list containing all the chips attached to the * controller * @@ -389,6 +395,7 @@ struct qcom_nand_controller { const struct qcom_nandc_props *props; =20 struct nand_controller *controller; + struct qpic_spi_nand *qspi; struct list_head host_list; =20 union { --=20 2.34.1 From nobody Sat Nov 30 03:41:48 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F53518BBBD; Thu, 12 Sep 2024 06:16:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726121794; cv=none; b=tgc1aHdpoC6f8IvSn1GJUYvBNV9wBIpFYYgjK4aZPzhpj8s413zc+odDFhdoILAfzbCjtw5XLtlF/7t6OisUEFxBmiBLlDmPSgjdzQZyt5qSFWy0V7AEWL43SmiWX41jo5PbPiXugOejqxBQ5c4agkdNvX+btBlt5hutMWHWokI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726121794; c=relaxed/simple; bh=1qsKQ18lRJCj0t3VY6y/f+9bi9nLWLMMKn62KN7AjyU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RngNNlD6hu9HspApR9blcbmfG8kDXhJV+CnmCzBIyRXbsFnOGD4qf5LEcx3vqaGJGozDCQVY21ucQdg4lCxovI5V+sJqUR6POCTWl75RjdtZIvxOEtA5W4Ja84PJOq74PXqrGJGR5S/avtApStJTPXJ8qoX1BTKSIgDo/xOXnWk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=MLQ9BA8E; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="MLQ9BA8E" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48C2LDha006693; Thu, 12 Sep 2024 06:16:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 2SqrfzuY58oS8x2Y2XOpO1qEDu8sn6n/1vpUMZVUcf4=; b=MLQ9BA8EcFOFfO0X YwOjUT0fo+905iE1ocegxfRL1yeVPxeqaRmWmFmr7B5/fAVswr6vcJJYjP+d4ggs xD0R/rM79hSOhiihuQFfpq7BOcGD0FCcHEvFqkmsCYiV2wpXcouelQfKdomRgbhl gS4JQSGWmFaJybJG7fNqjW4kqzvNdnPaCAzK+lnKyXDzMHsZr83huwn0mq/sTkkq HoaUOLNYvbI0MKrsfmb5XJvKulIHVgKaLvaToFdK1ObKrbGRXqQaqRniz+Cmiud/ nRo5s1ogQff4xw3QBIuoAc0DudyjRtrwDZneMdQKMe2s9c3pIFsU1SPTcISJ0dQz oorbIA== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41gy6pc1nr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Sep 2024 06:16:04 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48C6G3or024238 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Sep 2024 06:16:03 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Sep 2024 23:15:58 -0700 From: Md Sadre Alam To: , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v9 7/8] arm64: dts: qcom: ipq9574: Add SPI nand support Date: Thu, 12 Sep 2024 11:45:02 +0530 Message-ID: <20240912061503.3468147-8-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240912061503.3468147-1-quic_mdalam@quicinc.com> References: <20240912061503.3468147-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 6ypX8UBGZtAMXK2VxXlIEfzYWuDgnA6Q X-Proofpoint-GUID: 6ypX8UBGZtAMXK2VxXlIEfzYWuDgnA6Q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 spamscore=0 phishscore=0 impostorscore=0 suspectscore=0 mlxscore=0 malwarescore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409120043 Content-Type: text/plain; charset="utf-8" Add SPI NAND support for ipq9574 SoC. Signed-off-by: Md Sadre Alam --- Change in [v9] * No change Change in [v8] * No change Change in [v7] * No change Change in [v6] * No change Change in [v5] * No change Change in [v4] * No change Change in [v3] * Updated gpio number as per pin control driver * Fixed alignment issue Change in [v2] * Added initial enablement for spi-nand=20 Change in [v1] * Posted as RFC patch for design review .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 43 +++++++++++++++++++ arch/arm64/boot/dts/qcom/ipq9574.dtsi | 27 ++++++++++++ 2 files changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/= boot/dts/qcom/ipq9574-rdp-common.dtsi index 91e104b0f865..6429a6b3b903 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi @@ -139,6 +139,49 @@ gpio_leds_default: gpio-leds-default-state { drive-strength =3D <8>; bias-pull-up; }; + + qpic_snand_default_state: qpic-snand-default-state { + clock-pins { + pins =3D "gpio5"; + function =3D "qspi_clk"; + drive-strength =3D <8>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio4"; + function =3D "qspi_cs"; + drive-strength =3D <8>; + bias-disable; + }; + + data-pins { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "qspi_data"; + drive-strength =3D <8>; + bias-disable; + }; + }; +}; + +&qpic_bam { + status =3D "okay"; +}; + +&qpic_nand { + pinctrl-0 =3D <&qpic_snand_default_state>; + pinctrl-names =3D "default"; + status =3D "okay"; + + flash@0 { + compatible =3D "spi-nand"; + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + nand-ecc-engine =3D <&qpic_nand>; + nand-ecc-strength =3D <4>; + nand-ecc-step-size =3D <512>; + }; }; =20 &usb_0_dwc3 { diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qc= om/ipq9574.dtsi index 08a82a5cf667..65e70b33c587 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -330,6 +330,33 @@ tcsr: syscon@1937000 { reg =3D <0x01937000 0x21000>; }; =20 + qpic_bam: dma-controller@7984000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x7984000 0x1c000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QPIC_AHB_CLK>; + clock-names =3D "bam_clk"; + #dma-cells =3D <1>; + qcom,ee =3D <0>; + status =3D "disabled"; + }; + + qpic_nand: spi@79b0000 { + compatible =3D "qcom,spi-qpic-snand"; + reg =3D <0x79b0000 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>, + <&gcc GCC_QPIC_IO_MACRO_CLK>; + clock-names =3D "core", "aon", "iom"; + dmas =3D <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names =3D "tx", "rx", "cmd"; + status =3D "disabled"; + }; + sdhc_1: mmc@7804000 { compatible =3D "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x07804000 0x1000>, --=20 2.34.1 From nobody Sat Nov 30 03:41:48 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CEE6018BBBE; Thu, 12 Sep 2024 06:16:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726121793; cv=none; b=B50VI3kPEefwqVpO40NqdBvPTHjAk4xOpQ7ONqo9esOnvhSGxIKnnNTbSCXi2WttZZCxrQTFWKvnkw8F1J2IqXk+/GlX60OpGgG5OM1efA5KSfN1PGCYrlkxm0j32NN5aiULKnDEuEOVMy9n0K65stfKNZlAsvDNgDmEo/wO3+s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726121793; c=relaxed/simple; bh=a/9lEBCBhaShxj4WFFWNwknqEnz/og5XLEUnkNmgh78=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=F6KoaZ6GlBmwqTXGjzAKezCNQwWTbU0DzHjAYHg7+5nvoOCcs0L+/Jj38EEuegEH87nTGXyUilEY/55PIGF+pSR28jT1fWD3wQZBrpchwT4ByBXj8vOOuUHsrizm8mbRm2Alg/Dd62sZlVF09fasSW6HfrMWZG2GW8wkW1eSKK8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=S+UaguIr; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="S+UaguIr" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48C2LI7L007211; Thu, 12 Sep 2024 06:16:11 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= j66Xa7Bm5CnZXbgXQmRSMIf9SWiNNByo/Q92kn4b2KQ=; b=S+UaguIreZKkfkI1 Qe4eMCEd5hh+vnJDbrhag5C7IXm/IDTLM/bGM15yTF4iKzkwAPRk/0nJaDJE1aax tu+SpPqlvp7arYFrLcofO74CFOIvNKtYN7c1FHnFsMVADESG5D1YHHWr8/saXO1B 1QbvuuU/7AfYkc3Sr+Sj4bFtNiZJGPW9KISDI/rUMsa5L7eIFerxhphXhiWOSI2v qaBkvwiv+aYDPCGXg3LNtytbOcO2ARn+87cjbJYLKtALVQrWK8AnzcZRDd1OKvxC LIYFyW0TSKocZQcKKZccnQYC49H63cZQL92y31KMSnZyNdBl81D0XDwaQ2Azt7fA IKzlAQ== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41gy5rm16w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Sep 2024 06:16:10 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48C6G9Xj004238 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Sep 2024 06:16:09 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Sep 2024 23:16:03 -0700 From: Md Sadre Alam To: , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v9 8/8] arm64: dts: qcom: ipq9574: Disable eMMC node Date: Thu, 12 Sep 2024 11:45:03 +0530 Message-ID: <20240912061503.3468147-9-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240912061503.3468147-1-quic_mdalam@quicinc.com> References: <20240912061503.3468147-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: JMxGteYv-sro9AA6ITzddkaf4PuJPGoX X-Proofpoint-ORIG-GUID: JMxGteYv-sro9AA6ITzddkaf4PuJPGoX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 clxscore=1015 malwarescore=0 bulkscore=0 lowpriorityscore=0 adultscore=0 mlxscore=0 impostorscore=0 priorityscore=1501 mlxlogscore=880 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409120043 Content-Type: text/plain; charset="utf-8" Disable eMMC node for rdp433, since rdp433 default boot mode is norplusnand Signed-off-by: Md Sadre Alam --- Change in [v9] * No change Change in [v8] * No change Change in [v7] * No Change Change in [v6] * Updated commit message Change in [v5] * No Change Change in [v4] * No change Change in [v3] * Removed co-developed by=20 Change in [v2] * Posted as initial eMMC disable patch Change in [v1] * This patch was not included in v1 arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/= dts/qcom/ipq9574-rdp433.dts index 1bb8d96c9a82..e33e7fafd695 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts @@ -24,7 +24,7 @@ &sdhc_1 { mmc-hs400-enhanced-strobe; max-frequency =3D <384000000>; bus-width =3D <8>; - status =3D "okay"; + status =3D "disabled"; }; =20 &tlmm { --=20 2.34.1