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AJvYcCU7h5D+BCA/ajJfFxRHxHQ8YXL7J7l4YBTERmNfGJX+pOYjQidtnf9CTXUSMjsb9BUemgU7Uppn9ZVS@vger.kernel.org, AJvYcCWYASWJ6fFxvWjK4lDFR1LhL7KKFl8BEBh4JKxDLcELYAnYNsYVqs88QO4zfBVR6/XYiBnopcsMMPt+CLMd@vger.kernel.org X-Gm-Message-State: AOJu0Yz/2Pk5GXeEdQKTRLVltNXKT9/3MhTOOaaGGJrkTREtCYSWYq6a 3jerGFpDaXVAL3eXNjv+gJxZpSqPKw690gFLJjnDRd9ztTuveWK5 X-Google-Smtp-Source: AGHT+IGIsypAwH2BfcUev4iLPKNgb8VkdfI4kXvmWoMdEIHBfdzIHbtUfJ9hIl78NJDzFO5X8+CtTg== X-Received: by 2002:a17:903:183:b0:205:7998:3deb with SMTP id d9443c01a7336-2074c6dcc54mr92045545ad.19.1726109537951; Wed, 11 Sep 2024 19:52:17 -0700 (PDT) Received: from luna.turtle.lan ([2601:1c2:c184:dc00::315]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7db1fbbf877sm569023a12.50.2024.09.11.19.52.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:52:17 -0700 (PDT) From: Sam Edwards X-Google-Original-From: Sam Edwards To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ondrej Jirman , Chris Morgan , Alex Zhao , Dragan Simic , FUKAUMI Naoki , Sebastian Reichel , Jing Luo , Kever Yang , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Daniel=20Kukie=C5=82a?= , Joshua Riek , Sam Edwards Subject: [PATCH 1/5] arm64: dts: rockchip: Split up RK3588's PCIe pinctrls Date: Wed, 11 Sep 2024 19:50:30 -0700 Message-ID: <20240912025034.180233-2-CFSworks@gmail.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240912025034.180233-1-CFSworks@gmail.com> References: <20240912025034.180233-1-CFSworks@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" These pinctrls manage the low-speed PCIe signals: - CLKREQ#: An output on the RK3588 (both RC or EP modes), used to request that external clock-generation circuitry provide a clock. - PERST#: An input on the RK3588 in EP mode, used to detect a reset signal from the RC. In RC mode, the hardware does not use this signal: Linux itself generates it by putting the pin in GPIO mode. - WAKE#: In EP mode, this is an output; in RC mode, this is an input. Each of these signals serves a distinct purpose, and more importantly, PERST# should not be muxed when the RK3588 is in the RC role. Bundling them together in pinctrl groups prevents proper use: indeed, almost none of the current board-specific .dts files make any use of them. (Exception: Rock 5A recently had a patch land that misuses _pins; this patch corrects that.) However, on some RK3588 boards, the PCIe 3 controller will indefinitely stall the boot if CLKREQ# is not muxed (details in the next patch). This patch unbundles the signals to allow them to be used. Signed-off-by: Sam Edwards --- .../dts/rockchip/rk3588-base-pinctrl.dtsi | 271 ++++++++++++++---- .../boot/dts/rockchip/rk3588s-rock-5a.dts | 6 +- 2 files changed, 228 insertions(+), 49 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi b/arch/a= rm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi index d1368418502a..7f874c77410c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi @@ -1612,23 +1612,43 @@ npu_pins: npu-pins { =20 pcie20x1 { /omit-if-no-ref/ - pcie20x1m0_pins: pcie20x1m0-pins { + pcie20x1m0_clkreqn: pcie20x1m0-clkreqn { rockchip,pins =3D /* pcie20x1_2_clkreqn_m0 */ - <3 RK_PC7 4 &pcfg_pull_none>, + <3 RK_PC7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20x1m0_perstn: pcie20x1m0-perstn { + rockchip,pins =3D /* pcie20x1_2_perstn_m0 */ - <3 RK_PD1 4 &pcfg_pull_none>, + <3 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20x1m0_waken: pcie20x1m0-waken { + rockchip,pins =3D /* pcie20x1_2_waken_m0 */ <3 RK_PD0 4 &pcfg_pull_none>; }; =20 /omit-if-no-ref/ - pcie20x1m1_pins: pcie20x1m1-pins { + pcie20x1m1_clkreqn: pcie20x1m1-clkreqn { rockchip,pins =3D /* pcie20x1_2_clkreqn_m1 */ - <4 RK_PB7 4 &pcfg_pull_none>, + <4 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20x1m1_perstn: pcie20x1m1-perstn { + rockchip,pins =3D /* pcie20x1_2_perstn_m1 */ - <4 RK_PC1 4 &pcfg_pull_none>, + <4 RK_PC1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20x1m1_waken: pcie20x1m1-waken { + rockchip,pins =3D /* pcie20x1_2_waken_m1 */ <4 RK_PC0 4 &pcfg_pull_none>; }; @@ -1654,52 +1674,127 @@ pcie30phy_pins: pcie30phy-pins { =20 pcie30x1 { /omit-if-no-ref/ - pcie30x1m0_pins: pcie30x1m0-pins { + pcie30x1m0_0_clkreqn: pcie30x1m0-0-clkreqn { rockchip,pins =3D /* pcie30x1_0_clkreqn_m0 */ - <0 RK_PC0 12 &pcfg_pull_none>, + <0 RK_PC0 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m0_0_perstn: pcie30x1m0-0-perstn { + rockchip,pins =3D /* pcie30x1_0_perstn_m0 */ - <0 RK_PC5 12 &pcfg_pull_none>, + <0 RK_PC5 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m0_0_waken: pcie30x1m0-0-waken { + rockchip,pins =3D /* pcie30x1_0_waken_m0 */ - <0 RK_PC4 12 &pcfg_pull_none>, + <0 RK_PC4 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m0_1_clkreqn: pcie30x1m0-1-clkreqn { + rockchip,pins =3D /* pcie30x1_1_clkreqn_m0 */ - <0 RK_PB5 12 &pcfg_pull_none>, + <0 RK_PB5 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m0_1_perstn: pcie30x1m0-1-perstn { + rockchip,pins =3D /* pcie30x1_1_perstn_m0 */ - <0 RK_PB7 12 &pcfg_pull_none>, + <0 RK_PB7 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m0_1_waken: pcie30x1m0-1-waken { + rockchip,pins =3D /* pcie30x1_1_waken_m0 */ <0 RK_PB6 12 &pcfg_pull_none>; }; =20 /omit-if-no-ref/ - pcie30x1m1_pins: pcie30x1m1-pins { + pcie30x1m1_0_clkreqn: pcie30x1m1-0-clkreqn { rockchip,pins =3D /* pcie30x1_0_clkreqn_m1 */ - <4 RK_PA3 4 &pcfg_pull_none>, + <4 RK_PA3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_0_perstn: pcie30x1m1-0-perstn { + rockchip,pins =3D /* pcie30x1_0_perstn_m1 */ - <4 RK_PA5 4 &pcfg_pull_none>, + <4 RK_PA5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_0_waken: pcie30x1m1-0-waken { + rockchip,pins =3D /* pcie30x1_0_waken_m1 */ - <4 RK_PA4 4 &pcfg_pull_none>, + <4 RK_PA4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_1_clkreqn: pcie30x1m1-1-clkreqn { + rockchip,pins =3D /* pcie30x1_1_clkreqn_m1 */ - <4 RK_PA0 4 &pcfg_pull_none>, + <4 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_1_perstn: pcie30x1m1-1-perstn { + rockchip,pins =3D /* pcie30x1_1_perstn_m1 */ - <4 RK_PA2 4 &pcfg_pull_none>, + <4 RK_PA2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_1_waken: pcie30x1m1-1-waken { + rockchip,pins =3D /* pcie30x1_1_waken_m1 */ <4 RK_PA1 4 &pcfg_pull_none>; }; =20 /omit-if-no-ref/ - pcie30x1m2_pins: pcie30x1m2-pins { + pcie30x1m2_0_clkreqn: pcie30x1m2-0-clkreqn { rockchip,pins =3D /* pcie30x1_0_clkreqn_m2 */ - <1 RK_PB5 4 &pcfg_pull_none>, + <1 RK_PB5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_0_perstn: pcie30x1m2-0-perstn { + rockchip,pins =3D /* pcie30x1_0_perstn_m2 */ - <1 RK_PB4 4 &pcfg_pull_none>, + <1 RK_PB4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_0_waken: pcie30x1m2-0-waken { + rockchip,pins =3D /* pcie30x1_0_waken_m2 */ - <1 RK_PB3 4 &pcfg_pull_none>, + <1 RK_PB3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_1_clkreqn: pcie30x1m2-1-clkreqn { + rockchip,pins =3D /* pcie30x1_1_clkreqn_m2 */ - <1 RK_PA0 4 &pcfg_pull_none>, + <1 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_1_perstn: pcie30x1m2-1-perstn { + rockchip,pins =3D /* pcie30x1_1_perstn_m2 */ - <1 RK_PA7 4 &pcfg_pull_none>, + <1 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_1_waken: pcie30x1m2-1-waken { + rockchip,pins =3D /* pcie30x1_1_waken_m2 */ <1 RK_PA1 4 &pcfg_pull_none>; }; @@ -1721,45 +1816,85 @@ pcie30x1_1_button_rstn: pcie30x1-1-button-rstn { =20 pcie30x2 { /omit-if-no-ref/ - pcie30x2m0_pins: pcie30x2m0-pins { + pcie30x2m0_clkreqn: pcie30x2m0-clkreqn { rockchip,pins =3D /* pcie30x2_clkreqn_m0 */ - <0 RK_PD1 12 &pcfg_pull_none>, + <0 RK_PD1 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m0_perstn: pcie30x2m0-perstn { + rockchip,pins =3D /* pcie30x2_perstn_m0 */ - <0 RK_PD4 12 &pcfg_pull_none>, + <0 RK_PD4 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m0_waken: pcie30x2m0-waken { + rockchip,pins =3D /* pcie30x2_waken_m0 */ <0 RK_PD2 12 &pcfg_pull_none>; }; =20 /omit-if-no-ref/ - pcie30x2m1_pins: pcie30x2m1-pins { + pcie30x2m1_clkreqn: pcie30x2m1-clkreqn { rockchip,pins =3D /* pcie30x2_clkreqn_m1 */ - <4 RK_PA6 4 &pcfg_pull_none>, + <4 RK_PA6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m1_perstn: pcie30x2m1-perstn { + rockchip,pins =3D /* pcie30x2_perstn_m1 */ - <4 RK_PB0 4 &pcfg_pull_none>, + <4 RK_PB0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m1_waken: pcie30x2m1-waken { + rockchip,pins =3D /* pcie30x2_waken_m1 */ <4 RK_PA7 4 &pcfg_pull_none>; }; =20 /omit-if-no-ref/ - pcie30x2m2_pins: pcie30x2m2-pins { + pcie30x2m2_clkreqn: pcie30x2m2-clkreqn { rockchip,pins =3D /* pcie30x2_clkreqn_m2 */ - <3 RK_PD2 4 &pcfg_pull_none>, + <3 RK_PD2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m2_perstn: pcie30x2m2-perstn { + rockchip,pins =3D /* pcie30x2_perstn_m2 */ - <3 RK_PD4 4 &pcfg_pull_none>, + <3 RK_PD4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m2_waken: pcie30x2m2-waken { + rockchip,pins =3D /* pcie30x2_waken_m2 */ <3 RK_PD3 4 &pcfg_pull_none>; }; =20 /omit-if-no-ref/ - pcie30x2m3_pins: pcie30x2m3-pins { + pcie30x2m3_clkreqn: pcie30x2m3-clkreqn { rockchip,pins =3D /* pcie30x2_clkreqn_m3 */ - <1 RK_PD7 4 &pcfg_pull_none>, + <1 RK_PD7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m3_perstn: pcie30x2m3-perstn { + rockchip,pins =3D /* pcie30x2_perstn_m3 */ - <1 RK_PB7 4 &pcfg_pull_none>, + <1 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m3_waken: pcie30x2m3-waken { + rockchip,pins =3D /* pcie30x2_waken_m3 */ <1 RK_PB6 4 &pcfg_pull_none>; }; @@ -1774,45 +1909,85 @@ pcie30x2_button_rstn: pcie30x2-button-rstn { =20 pcie30x4 { /omit-if-no-ref/ - pcie30x4m0_pins: pcie30x4m0-pins { + pcie30x4m0_clkreqn: pcie30x4m0-clkreqn { rockchip,pins =3D /* pcie30x4_clkreqn_m0 */ - <0 RK_PC6 12 &pcfg_pull_none>, + <0 RK_PC6 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m0_perstn: pcie30x4m0-perstn { + rockchip,pins =3D /* pcie30x4_perstn_m0 */ - <0 RK_PD0 12 &pcfg_pull_none>, + <0 RK_PD0 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m0_waken: pcie30x4m0-waken { + rockchip,pins =3D /* pcie30x4_waken_m0 */ <0 RK_PC7 12 &pcfg_pull_none>; }; =20 /omit-if-no-ref/ - pcie30x4m1_pins: pcie30x4m1-pins { + pcie30x4m1_clkreqn: pcie30x4m1-clkreqn { rockchip,pins =3D /* pcie30x4_clkreqn_m1 */ - <4 RK_PB4 4 &pcfg_pull_none>, + <4 RK_PB4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m1_perstn: pcie30x4m1-perstn { + rockchip,pins =3D /* pcie30x4_perstn_m1 */ - <4 RK_PB6 4 &pcfg_pull_none>, + <4 RK_PB6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m1_waken: pcie30x4m1-waken { + rockchip,pins =3D /* pcie30x4_waken_m1 */ <4 RK_PB5 4 &pcfg_pull_none>; }; =20 /omit-if-no-ref/ - pcie30x4m2_pins: pcie30x4m2-pins { + pcie30x4m2_clkreqn: pcie30x4m2-clkreqn { rockchip,pins =3D /* pcie30x4_clkreqn_m2 */ - <3 RK_PC4 4 &pcfg_pull_none>, + <3 RK_PC4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m2_perstn: pcie30x4m2-perstn { + rockchip,pins =3D /* pcie30x4_perstn_m2 */ - <3 RK_PC6 4 &pcfg_pull_none>, + <3 RK_PC6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m2_waken: pcie30x4m2-waken { + rockchip,pins =3D /* pcie30x4_waken_m2 */ <3 RK_PC5 4 &pcfg_pull_none>; }; =20 /omit-if-no-ref/ - pcie30x4m3_pins: pcie30x4m3-pins { + pcie30x4m3_clkreqn: pcie30x4m3-clkreqn { rockchip,pins =3D /* pcie30x4_clkreqn_m3 */ - <1 RK_PB0 4 &pcfg_pull_none>, + <1 RK_PB0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m3_perstn: pcie30x4m3-perstn { + rockchip,pins =3D /* pcie30x4_perstn_m3 */ - <1 RK_PB2 4 &pcfg_pull_none>, + <1 RK_PB2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m3_waken: pcie30x4m3-waken { + rockchip,pins =3D /* pcie30x4_waken_m3 */ <1 RK_PB1 4 &pcfg_pull_none>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/= boot/dts/rockchip/rk3588s-rock-5a.dts index 294b99dd50da..87fce8d9a964 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts @@ -310,7 +310,7 @@ rgmii_phy1: ethernet-phy@1 { }; =20 &pcie2x1l2 { - pinctrl-0 =3D <&pcie20x1m0_pins>; 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Wed, 11 Sep 2024 19:52:18 -0700 (PDT) From: Sam Edwards X-Google-Original-From: Sam Edwards To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ondrej Jirman , Chris Morgan , Alex Zhao , Dragan Simic , FUKAUMI Naoki , Sebastian Reichel , Jing Luo , Kever Yang , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Daniel=20Kukie=C5=82a?= , Joshua Riek , Sam Edwards , Jonathan Bennett Subject: [PATCH 2/5] arm64: dts: rockchip: Fix Turing RK1 PCIe3 hang Date: Wed, 11 Sep 2024 19:50:31 -0700 Message-ID: <20240912025034.180233-3-CFSworks@gmail.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240912025034.180233-1-CFSworks@gmail.com> References: <20240912025034.180233-1-CFSworks@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The PCIe 3 PHY in the RK3588 requires a running external reference clock for both external bus transfers and some internal PIPE operations. Without this clock, the PCIe3 controller fails to initialize and ignores DBI transactions indefinitely, which stalls the Linux boot process. On most RK3588 boards, this is evidently not an issue. But on some "SoM" designs (Turing RK1, Mixtile Core 3588E, ArmSoM AIM7, to name a few), this clock is only provided when the CLKREQ# signal is asserted. The PCIe 3 PHY generates the CLKREQ# signal when it knows it needs the reference clock for proper operation. Unfortunately, the current DT for Turing RK1 does not mux out these low-speed signals, resulting in broken boots and potentially other issues. This patch, following the previous one that split up the PCIe pinctrls, resolves this problem for Turing RK1 by explicitly muxing all of the signals needed for PCIe 2 and 3 support. Cc: Jonathan Bennett Fixes: 2806a69f3f ("arm64: dts: rockchip: Add Turing RK1 SoM support") Signed-off-by: Sam Edwards --- arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm= 64/boot/dts/rockchip/rk3588-turing-rk1.dtsi index dbaa94ca69f4..9bcb5acdea54 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi @@ -211,7 +211,7 @@ rgmii_phy: ethernet-phy@1 { &pcie2x1l1 { linux,pci-domain =3D <1>; pinctrl-names =3D "default"; - pinctrl-0 =3D <&pcie2_reset>; + pinctrl-0 =3D <&pcie2_reset>, <&pcie30x1m1_0_clkreqn>, <&pcie30x1m1_0_wak= en>; reset-gpios =3D <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; status =3D "okay"; }; @@ -223,7 +223,7 @@ &pcie30phy { &pcie3x4 { linux,pci-domain =3D <0>; pinctrl-names =3D "default"; - pinctrl-0 =3D <&pcie3_reset>; + pinctrl-0 =3D <&pcie3_reset>, <&pcie30x4m1_clkreqn>, <&pcie30x4m1_waken>; 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charset="utf-8" This patch adds thermal trip points and cooling maps to the Turing RK1 in order to enable automatic control of the external PWM fan. The fan is not active below 45C, as the heatsink alone can generally keep the chip in this temperature region at idle load. This cooling profile errs on the side of quietness, since the RK1 is commonly deployed in a Turing Pi 2 clusterboard alongside three others, with additional cooling provided at the chassis level. Helped-by: soxrok2212 Signed-off-by: Sam Edwards --- .../boot/dts/rockchip/rk3588-turing-rk1.dtsi | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm= 64/boot/dts/rockchip/rk3588-turing-rk1.dtsi index 9bcb5acdea54..f6a12fe12d45 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi @@ -208,6 +208,59 @@ rgmii_phy: ethernet-phy@1 { }; }; =20 +&package_thermal { + trips { + package_active1: trip-active1 { + temperature =3D <45000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + package_active2: trip-active2 { + temperature =3D <50000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + package_active3: trip-active3 { + temperature =3D <60000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + package_active4: trip-active4 { + temperature =3D <70000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + package_active5: trip-active5 { + temperature =3D <80000>; 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Wed, 11 Sep 2024 19:52:22 -0700 (PDT) Received: from luna.turtle.lan ([2601:1c2:c184:dc00::315]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7db1fbbf877sm569023a12.50.2024.09.11.19.52.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:52:21 -0700 (PDT) From: Sam Edwards X-Google-Original-From: Sam Edwards To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ondrej Jirman , Chris Morgan , Alex Zhao , Dragan Simic , FUKAUMI Naoki , Sebastian Reichel , Jing Luo , Kever Yang , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Daniel=20Kukie=C5=82a?= , Joshua Riek , Sam Edwards Subject: [PATCH 4/5] arm64: dts: rockchip: Enable all 3 USBs on Turing RK1 Date: Wed, 11 Sep 2024 19:50:33 -0700 Message-ID: <20240912025034.180233-5-CFSworks@gmail.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240912025034.180233-1-CFSworks@gmail.com> References: <20240912025034.180233-1-CFSworks@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Turing RK1 contains 3 different USBs: - USB0: USB 2.0, OTG - USB1: USB 3.0, host - USB2: USB 2.0, host This patch activates the necessary DT nodes to enable all 3 buses. Future work will be needed on USB0: it is not USB 3.0, but Linux creates an unused USB 3.0 root hub and the controller also requires that USBDP0 be powered up. However, it is possible to remove this dependency. By either patching the xHCI driver to ignore the enumerated USB 3.0 port or setting usb3otg0_host_num_u3_port=3D0 in the GRF to stop the controller from enumerating a USB 3.0 port in the first place, neither Linux nor the controller will expect USB 3.0 capability, and USBDP0 can then safely be removed from the `phys` property. Signed-off-by: Sam Edwards --- .../boot/dts/rockchip/rk3588-turing-rk1.dtsi | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm= 64/boot/dts/rockchip/rk3588-turing-rk1.dtsi index f6a12fe12d45..6036c4fe6727 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi @@ -666,3 +666,67 @@ &uart9 { pinctrl-0 =3D <&uart9m0_xfer>; status =3D "okay"; }; + +/* USB 0: USB 2.0 only, OTG-capable */ +&u2phy0 { + status =3D "okay"; +}; + +&u2phy0_otg { + status =3D "okay"; +}; + +&usbdp_phy0 { + /* + * TODO: On the RK1, USBDP0 drives the DisplayPort pins, and is not + * involved in this USB2-only bus. However, if the USB3 port is + * enabled in the xHCI below, the controller will expect this PHY to be + * powered up and holding RX_STATUS idle, or else it will generate an + * endless stream of CSC events whenever a device is plugged in. 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Wed, 11 Sep 2024 19:52:24 -0700 (PDT) Received: from luna.turtle.lan ([2601:1c2:c184:dc00::315]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7db1fbbf877sm569023a12.50.2024.09.11.19.52.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:52:23 -0700 (PDT) From: Sam Edwards X-Google-Original-From: Sam Edwards To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ondrej Jirman , Chris Morgan , Alex Zhao , Dragan Simic , FUKAUMI Naoki , Sebastian Reichel , Jing Luo , Kever Yang , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Daniel=20Kukie=C5=82a?= , Joshua Riek , Sam Edwards Subject: [PATCH 5/5] arm64: dts: rockchip: Enable GPU on Turing RK1 Date: Wed, 11 Sep 2024 19:50:34 -0700 Message-ID: <20240912025034.180233-6-CFSworks@gmail.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240912025034.180233-1-CFSworks@gmail.com> References: <20240912025034.180233-1-CFSworks@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the Mali GPU in the Turing RK1. This patch also sets the external GPU voltage regulator in the RK806-1 to "always-on" because it is necessary for this regulator to be active when enabling the GPU power domain or the kernel will fail with: rockchip-pm-domain fd8d8000.power-management:power-controller: \ failed to set domain 'gpu', val=3D0 rockchip-pm-domain fd8d8000.power-management:power-controller: \ failed to get ack on domain 'gpu', val=3D0x1bffff ...followed by a panic when it attempts to access unavailable QoS registers. Since there is currently no `domain-supply` or similar to express this dependency, the only way to ensure that the regulator is never off when the GPU power domain is brought up is to ensure that the regulator is never off. Signed-off-by: Sam Edwards --- Hi list, This particular patch will probably need to be revisited once something like [1] lands. I'm completely unable to get the GPU up and running without some kind of solution to the power dependency issue, but it's possible that this is because I'm just particularly unlucky in the timing department. Cheers, Sam [1]: https://lore.kernel.org/lkml/20240910180530.47194-7-sebastian.reichel@= collabora.com/T/ --- .../boot/dts/rockchip/rk3588-turing-rk1.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm= 64/boot/dts/rockchip/rk3588-turing-rk1.dtsi index 6036c4fe6727..dedfb9ede4a3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi @@ -116,6 +116,11 @@ &gmac1_rgmii_clk status =3D "okay"; }; =20 +&gpu { + mali-supply =3D <&vdd_gpu_s0>; + status =3D "okay"; +}; + &i2c0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&i2c0m2_xfer>; @@ -386,6 +391,17 @@ rk806_dvs3_null: dvs3-null-pins { =20 regulators { vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + /* + * RK3588's GPU power domain cannot be enabled + * without this regulator active, but it + * doesn't have to be on when the GPU PD is + * disabled. Because the PD binding does not + * currently allow us to express this + * relationship, we have no choice but to do + * this instead: + */ + regulator-always-on; + regulator-boot-on; regulator-min-microvolt =3D <550000>; regulator-max-microvolt =3D <950000>; --=20 2.44.2