From nobody Mon Feb 9 09:33:08 2026 Received: from smtp-fw-9102.amazon.com (smtp-fw-9102.amazon.com [207.171.184.29]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D78CE1A76C9 for ; Wed, 11 Sep 2024 14:37:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=207.171.184.29 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726065468; cv=none; b=KGo1/EX5F2RjDdzDIjx0TkzcY8QKctuzu/oagdwy3+AqPHb3H1e6k2mDg5CT/xArRFBWXeac1UaeNXo+VAhlr2cMRUlopNFwVHKfZM9QAhGoj0evTv+GfWohtegMymRV2tMEmloEU+MdT/0COZRAQAzCnusPuDculK70tquH4nM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726065468; c=relaxed/simple; bh=feRSGJHJU4EXR47b3J41bw3N15CyZRe4CKUQtrdHZqY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=FHLoS5KYGe7LHaNhH0xqd74k7FUVSGT9JbRoZcbIcCOkpKipHho4NRckcTbselMapu1NMT1qTsTplB/UFpMo4uZ0nIdxtCnRuCp2OtEw7reVEfmswm1JQWQM1DV84E6aKtM6jVvolfm2MzIC1Y/hv46ogrmwtabGJDsFMRIPUBI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amazon.de; spf=pass smtp.mailfrom=amazon.de; dkim=pass (1024-bit key) header.d=amazon.de header.i=@amazon.de header.b=fP/foVYv; arc=none smtp.client-ip=207.171.184.29 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amazon.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amazon.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amazon.de header.i=@amazon.de header.b="fP/foVYv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.de; i=@amazon.de; q=dns/txt; s=amazon201209; t=1726065467; x=1757601467; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rCn+xTWUjnpsWnBBnpI3iR0NNWrWMHIE+UutE4x6c8o=; b=fP/foVYvIedlOjkxTffZG9ffRlV5MWod3Keodu7uiEvWZFZkwI6A1tVy Wl41huZOdJk2H6huy5WaSPO23dIISv/Hukne75pgeGkm3mvQXR/PqDqLX gD5sIrdv1bBmS/Pcb3LMrB5BOEZ84FpiLE72GlV/6oJcUqEfGF5syqPJa c=; X-IronPort-AV: E=Sophos;i="6.10,220,1719878400"; d="scan'208";a="452953260" Received: from pdx4-co-svc-p1-lb2-vlan3.amazon.com (HELO smtpout.prod.us-east-1.prod.farcaster.email.amazon.dev) ([10.25.36.214]) by smtp-border-fw-9102.sea19.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2024 14:36:30 +0000 Received: from EX19MTAEUC001.ant.amazon.com [10.0.17.79:20048] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.13.80:2525] with esmtp (Farcaster) id 337e7469-1cf4-42a1-a92c-28b8d968fd53; Wed, 11 Sep 2024 14:36:28 +0000 (UTC) X-Farcaster-Flow-ID: 337e7469-1cf4-42a1-a92c-28b8d968fd53 Received: from EX19D007EUB001.ant.amazon.com (10.252.51.82) by EX19MTAEUC001.ant.amazon.com (10.252.51.155) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.1258.34; Wed, 11 Sep 2024 14:36:22 +0000 Received: from EX19MTAUEC001.ant.amazon.com (10.252.135.222) by EX19D007EUB001.ant.amazon.com (10.252.51.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.1258.35; Wed, 11 Sep 2024 14:36:21 +0000 Received: from dev-dsk-faresx-1b-27755bf1.eu-west-1.amazon.com (10.253.79.181) by mail-relay.amazon.com (10.252.135.200) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.1258.34 via Frontend Transport; Wed, 11 Sep 2024 14:36:19 +0000 From: Fares Mehanna To: CC: , Fares Mehanna , "Marc Zyngier" , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , "Will Deacon" , Andrew Morton , "Kemeng Shi" , =?UTF-8?q?Pierre-Cl=C3=A9ment=20Tosi?= , Ard Biesheuvel , Mark Rutland , Javier Martinez Canillas , "Arnd Bergmann" , Fuad Tabba , Mark Brown , Joey Gouly , Kristina Martsenko , Randy Dunlap , "Bjorn Helgaas" , Jean-Philippe Brucker , "Mike Rapoport (IBM)" , "David Hildenbrand" , Roman Kagan , "moderated list:KERNEL VIRTUAL MACHINE FOR ARM64 (KVM/arm64)" , "open list:KERNEL VIRTUAL MACHINE FOR ARM64 (KVM/arm64)" , open list , "open list:MEMORY MANAGEMENT" Subject: [RFC PATCH 3/7] arm64: KVM: Refactor C-code to access vCPU gp-registers through macros Date: Wed, 11 Sep 2024 14:34:02 +0000 Message-ID: <20240911143421.85612-4-faresx@amazon.de> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240911143421.85612-1-faresx@amazon.de> References: <20240911143421.85612-1-faresx@amazon.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unify how KVM accesses vCPU gp-regs by using two macros vcpu_gp_regs() and ctxt_gp_regs(). This is prerequisite to move the gp-regs later to be dynami= cally allocated for vCPUs. Signed-off-by: Fares Mehanna --- arch/arm64/include/asm/kvm_emulate.h | 2 +- arch/arm64/include/asm/kvm_host.h | 3 ++- arch/arm64/kvm/guest.c | 8 ++++---- arch/arm64/kvm/hyp/include/hyp/switch.h | 2 +- arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 10 +++++----- arch/arm64/kvm/hyp/include/nvhe/trap_handler.h | 2 +- 6 files changed, 14 insertions(+), 13 deletions(-) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/= kvm_emulate.h index a601a9305b10..cabfb76ca514 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -170,7 +170,7 @@ static __always_inline void vcpu_set_reg(struct kvm_vcp= u *vcpu, u8 reg_num, =20 static inline bool vcpu_is_el2_ctxt(const struct kvm_cpu_context *ctxt) { - switch (ctxt->regs.pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) { + switch (ctxt_gp_regs(ctxt)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) { case PSR_MODE_EL2h: case PSR_MODE_EL2t: return true; diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index a33f5996ca9f..31cbd62a5d06 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -946,7 +946,8 @@ struct kvm_vcpu_arch { #define vcpu_clear_on_unsupported_cpu(vcpu) \ vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU) =20 -#define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs) +#define ctxt_gp_regs(ctxt) (&(ctxt)->regs) +#define vcpu_gp_regs(v) (ctxt_gp_regs(&(v)->arch.ctxt)) =20 /* * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 11098eb7eb44..821a2b7de388 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -134,16 +134,16 @@ static void *core_reg_addr(struct kvm_vcpu *vcpu, con= st struct kvm_one_reg *reg) KVM_REG_ARM_CORE_REG(regs.regs[30]): off -=3D KVM_REG_ARM_CORE_REG(regs.regs[0]); off /=3D 2; - return &vcpu->arch.ctxt.regs.regs[off]; + return &vcpu_gp_regs(vcpu)->regs[off]; =20 case KVM_REG_ARM_CORE_REG(regs.sp): - return &vcpu->arch.ctxt.regs.sp; + return &vcpu_gp_regs(vcpu)->sp; =20 case KVM_REG_ARM_CORE_REG(regs.pc): - return &vcpu->arch.ctxt.regs.pc; + return &vcpu_gp_regs(vcpu)->pc; =20 case KVM_REG_ARM_CORE_REG(regs.pstate): - return &vcpu->arch.ctxt.regs.pstate; + return &vcpu_gp_regs(vcpu)->pstate; =20 case KVM_REG_ARM_CORE_REG(sp_el1): return __ctxt_sys_reg(&vcpu->arch.ctxt, SP_EL1); diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/i= nclude/hyp/switch.h index 37ff87d782b6..d2ed0938fc90 100644 --- a/arch/arm64/kvm/hyp/include/hyp/switch.h +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h @@ -649,7 +649,7 @@ static inline void synchronize_vcpu_pstate(struct kvm_v= cpu *vcpu, u64 *exit_code ESR_ELx_EC(read_sysreg_el2(SYS_ESR)) =3D=3D ESR_ELx_EC_PAC) write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR); =20 - vcpu->arch.ctxt.regs.pstate =3D read_sysreg_el2(SYS_SPSR); + vcpu_gp_regs(vcpu)->pstate =3D read_sysreg_el2(SYS_SPSR); } =20 /* diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hy= p/include/hyp/sysreg-sr.h index 4c0fdabaf8ae..d17033766010 100644 --- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h +++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h @@ -105,13 +105,13 @@ static inline void __sysreg_save_el1_state(struct kvm= _cpu_context *ctxt) =20 static inline void __sysreg_save_el2_return_state(struct kvm_cpu_context *= ctxt) { - ctxt->regs.pc =3D read_sysreg_el2(SYS_ELR); + ctxt_gp_regs(ctxt)->pc =3D read_sysreg_el2(SYS_ELR); /* * Guest PSTATE gets saved at guest fixup time in all * cases. We still need to handle the nVHE host side here. */ if (!has_vhe() && ctxt->__hyp_running_vcpu) - ctxt->regs.pstate =3D read_sysreg_el2(SYS_SPSR); + ctxt_gp_regs(ctxt)->pstate =3D read_sysreg_el2(SYS_SPSR); =20 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) ctxt_sys_reg(ctxt, DISR_EL1) =3D read_sysreg_s(SYS_VDISR_EL2); @@ -202,7 +202,7 @@ static inline void __sysreg_restore_el1_state(struct kv= m_cpu_context *ctxt) /* Read the VCPU state's PSTATE, but translate (v)EL2 to EL1. */ static inline u64 to_hw_pstate(const struct kvm_cpu_context *ctxt) { - u64 mode =3D ctxt->regs.pstate & (PSR_MODE_MASK | PSR_MODE32_BIT); + u64 mode =3D ctxt_gp_regs(ctxt)->pstate & (PSR_MODE_MASK | PSR_MODE32_BIT= ); =20 switch (mode) { case PSR_MODE_EL2t: @@ -213,7 +213,7 @@ static inline u64 to_hw_pstate(const struct kvm_cpu_con= text *ctxt) break; } =20 - return (ctxt->regs.pstate & ~(PSR_MODE_MASK | PSR_MODE32_BIT)) | mode; + return (ctxt_gp_regs(ctxt)->pstate & ~(PSR_MODE_MASK | PSR_MODE32_BIT)) |= mode; } =20 static inline void __sysreg_restore_el2_return_state(struct kvm_cpu_contex= t *ctxt) @@ -235,7 +235,7 @@ static inline void __sysreg_restore_el2_return_state(st= ruct kvm_cpu_context *ctx if (!(mode & PSR_MODE32_BIT) && mode >=3D PSR_MODE_EL2t) pstate =3D PSR_MODE_EL2h | PSR_IL_BIT; =20 - write_sysreg_el2(ctxt->regs.pc, SYS_ELR); + write_sysreg_el2(ctxt_gp_regs(ctxt)->pc, SYS_ELR); write_sysreg_el2(pstate, SYS_SPSR); =20 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) diff --git a/arch/arm64/kvm/hyp/include/nvhe/trap_handler.h b/arch/arm64/kv= m/hyp/include/nvhe/trap_handler.h index 45a84f0ade04..dfe5be0d70ef 100644 --- a/arch/arm64/kvm/hyp/include/nvhe/trap_handler.h +++ b/arch/arm64/kvm/hyp/include/nvhe/trap_handler.h @@ -11,7 +11,7 @@ =20 #include =20 -#define cpu_reg(ctxt, r) (ctxt)->regs.regs[r] +#define cpu_reg(ctxt, r) (ctxt_gp_regs((ctxt))->regs[r]) #define DECLARE_REG(type, name, ctxt, reg) \ type name =3D (type)cpu_reg(ctxt, (reg)) =20 --=20 2.40.1 Amazon Web Services Development Center Germany GmbH Krausenstr. 38 10117 Berlin Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss Eingetragen am Amtsgericht Charlottenburg unter HRB 257764 B Sitz: Berlin Ust-ID: DE 365 538 597