From nobody Sat Nov 30 05:39:37 2024 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 640981862BB; Wed, 11 Sep 2024 10:51:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726051891; cv=none; b=gBNwTJbqlBo0P/Il6r9p1/nafir/k/3BpX6UXdPD/puu/CW+8E/M2Fj/hXXlO20KHcf2C07CpQLdMDnxJJQHTiriOumqGOZWwQNCpCGZ16kaPJvmYC8RwSjGZVEKFhU0vsRDderwY7ndqUcE4/V4imErzz4TwnXF/pdIk0YBycw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726051891; c=relaxed/simple; bh=X4RNJ1pzOn8EvMABuKVJGxX1rq8RKgWui7K/V4VRJVQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=sMZc4FqgZle3/wteie34C1d1qdLLB2DnCnLxTDT+4X5ZuvkF44CZZ2v5+C7bZSYEZf3GMPh3HIDl8mwyiJU30uAiwGfF2uUAFvZd8TsoGcRU00RG3auG2hZbRPeT1K5XKInlvsJUSkY57GnqOXv3VTtH57xCEM/5QZ7uXGb+rrg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=nyapZwvJ; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="nyapZwvJ" Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48B76L49029417; Wed, 11 Sep 2024 12:51:04 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= q+QeicHCp2ZWykwX9Szi74CPZHnZAUYBRGjXyMFb5hk=; b=nyapZwvJdZwJqguP VlLAX08BVEgUzEzYcCVkV+3lr13N0DVZsz34LrvIYjAutc6kcSQ7i9RiQdRCmzhj VyohcdYblKG6joPl9vOOCfyd+qGS55tQ3qX1slXSoz4bLpfTkKaV0Gl1sWzTClFW IFvDoJ6Y92g3KtVP9AafhCcSHdW86lironQDOXtYbYTGot3M4Ru86eJIqEZj5/s7 Jygwf3+wb+s/Fbi8loOai9qYYEJUOQVXTUGUNR7YXiSQrBGswIVR4xUWI1NyRfiT lMVHwlQ3GXWzQq7WS0sfKLK6cUASHNqxrMgBPgDaZDilIqflO3VCeVHqUEWscFsR ofmN4w== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 41h1sge3dr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 11 Sep 2024 12:51:04 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id D5C9B40072; Wed, 11 Sep 2024 12:49:44 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 8DE0F25C591; Wed, 11 Sep 2024 12:47:00 +0200 (CEST) Received: from localhost (10.129.178.212) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Wed, 11 Sep 2024 12:47:00 +0200 From: Christian Bruel To: , , , , , , , CC: , , , , , , Christian Bruel Subject: [PATCH v8 1/5] dt-bindings: phy: Add STM32MP25 COMBOPHY bindings Date: Wed, 11 Sep 2024 12:46:42 +0200 Message-ID: <20240911104646.2980821-2-christian.bruel@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240911104646.2980821-1-christian.bruel@foss.st.com> References: <20240911104646.2980821-1-christian.bruel@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Type: text/plain; charset="utf-8" Document the bindings for STM32 COMBOPHY interface, used to support the PCIe and USB3 stm32mp25 drivers. Following entries can be used to tune caracterisation parameters - st,output-micro-ohms and st,output-vswing-microvolt bindings entries to tune the impedance and voltage swing using discrete simulation results - st,rx-equalizer register to set the internal rx equalizer filter value. Reviewed-by: Rob Herring (Arm) Signed-off-by: Christian Bruel --- .../bindings/phy/st,stm32mp25-combophy.yaml | 119 ++++++++++++++++++ 1 file changed, 119 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/st,stm32mp25-comb= ophy.yaml diff --git a/Documentation/devicetree/bindings/phy/st,stm32mp25-combophy.ya= ml b/Documentation/devicetree/bindings/phy/st,stm32mp25-combophy.yaml new file mode 100644 index 000000000000..a2e82c0bb56b --- /dev/null +++ b/Documentation/devicetree/bindings/phy/st,stm32mp25-combophy.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/st,stm32mp25-combophy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32MP25 USB3/PCIe COMBOPHY + +maintainers: + - Christian Bruel + +description: + Single lane PHY shared (exclusive) between the USB3 and PCIe controllers. + Supports 5Gbit/s for USB3 and PCIe gen2 or 2.5Gbit/s for PCIe gen1. + +properties: + compatible: + const: st,stm32mp25-combophy + + reg: + maxItems: 1 + + "#phy-cells": + const: 1 + + clocks: + minItems: 2 + items: + - description: apb Bus clock mandatory to access registers. + - description: ker Internal RCC reference clock for USB3 or PCIe + - description: pad Optional on board clock input for PCIe only. Typi= cally an + external 100Mhz oscillator wired on dedicated CLKIN p= ad. Used as reference + clock input instead of the ker + + clock-names: + minItems: 2 + items: + - const: apb + - const: ker + - const: pad + + resets: + maxItems: 1 + + reset-names: + const: phy + + power-domains: + maxItems: 1 + + wakeup-source: true + + interrupts: + maxItems: 1 + description: interrupt used for wakeup + + access-controllers: + maxItems: 1 + description: Phandle to the rifsc device to check access right. + + st,ssc-on: + $ref: /schemas/types.yaml#/definitions/flag + description: + A property whose presence indicates that the Spread Spectrum Clockin= g is active. + + st,rx-equalizer: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + default: 2 + description: + A 3 bit value to tune the RX fixed equalizer setting for optimal eye= compliance + + st,output-micro-ohms: + minimum: 3999000 + maximum: 6090000 + default: 4968000 + description: + A value property to tune the Single Ended Output Impedance, simulati= ons results + at 25C for a VDDP=3D0.8V. The hardware accepts discrete values in th= is range. + + st,output-vswing-microvolt: + minimum: 442000 + maximum: 803000 + default: 803000 + description: + A value property in microvolt to tune the Single Ended Output Voltag= e Swing to change the + Vlo, Vhi for a VDDP =3D 0.8V. The hardware accepts discrete values i= n this range. + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + phy@480c0000 { + compatible =3D "st,stm32mp25-combophy"; + reg =3D <0x480c0000 0x1000>; + #phy-cells =3D <1>; + clocks =3D <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>; + clock-names =3D "apb", "ker"; + resets =3D <&rcc USB3PCIEPHY_R>; + reset-names =3D "phy"; + access-controllers =3D <&rifsc 67>; + power-domains =3D <&CLUSTER_PD>; + wakeup-source; + interrupts-extended =3D <&exti1 45 IRQ_TYPE_EDGE_FALLING>; + }; --=20 2.34.1 From nobody Sat Nov 30 05:39:37 2024 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63FB4185B67; Wed, 11 Sep 2024 10:51:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726051893; cv=none; b=rYeafcRP8bDym+MXBzk3a7R03R9GYdFf+4zUrWGBYuRt9sO0Cp0cJWbTu3k2dPSve0lREaNBtIQq157lBV8AOPMigu3T6bn9UnJJMV21uPLKfMHthN+bt00DBxiw6xKIiuwK3Z2Z08BzMfXJmSk+pPCMTqEqi3AvdK6xXxFSYZY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726051893; c=relaxed/simple; bh=/h1+WvsawfFuXwepO0c6I7VSB/D867PvBJhJw22281M=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bjxlUOm6fUDnhY26t1AC0P2HU46ojMJkIxWikKd5ucauMhYVfvJzTrsquhrl4XeT5omZzQX/4t4acg/lE6iFXaMWet9mP4oymYVExfbLP7aZ+jyOToXJFlcyCSPWzd1QtUZjugr0Lu0Y1u3CDTzgRTu5D4UmBR8Q4UtXAE16jX8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=PsampD79; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="PsampD79" Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48B7I3xp008648; Wed, 11 Sep 2024 12:51:04 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= 14nV4yo74BeJ/Eta4KcByX7PADB/y+FTg4sU010XzGM=; b=PsampD79MFUKrMsK XA2KhX0PLa6+ludabVLzmi4JPWdjvHe1bRXVCBYbmqKb8u1m/kC7Jtz4grnQKibW 04CAyGBe8yja3ZN1cEcj3KhAGBCvfV1ZPen+ykp6OE41babdJYbpJeZLRgg6egjM 0hKqqNtO5hIccoAmx+wvr/R58Wn1SSnTo0liC8eJfuN2XQ5Rq2tcH471Wj1tKkfZ /yIexrGt9AmjwpgnS1iNV8HpYRss1S5y0SgWeerlIcX+xbmPD0E8noSmXfOMNv92 owwYYvJiyI/BDUroBwOZWXzYqwBKX5kS1kBnuU3CvhzpGH5LVY0x3vViRA+aQoKx NM4wNQ== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 41h1sge3dq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 11 Sep 2024 12:51:04 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id D5C3A40071; Wed, 11 Sep 2024 12:49:44 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D6D3625C924; Wed, 11 Sep 2024 12:47:01 +0200 (CEST) Received: from localhost (10.129.178.212) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Wed, 11 Sep 2024 12:47:01 +0200 From: Christian Bruel To: , , , , , , , CC: , , , , , , Christian Bruel Subject: [PATCH v8 2/5] phy: stm32: Add support for STM32MP25 COMBOPHY. Date: Wed, 11 Sep 2024 12:46:43 +0200 Message-ID: <20240911104646.2980821-3-christian.bruel@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240911104646.2980821-1-christian.bruel@foss.st.com> References: <20240911104646.2980821-1-christian.bruel@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Type: text/plain; charset="utf-8" Addition of the COMBOPHY driver found on STM32MP25 platforms This single lane PHY is shared (exclusive) between the USB3 and PCIE controllers. Supports 5Gbit/s for PCIE gen2 or 2.5Gbit/s for PCIE gen1. Supports wakeup-source capability to wakeup system using remote-wakeup capable USB device Signed-off-by: Christian Bruel --- drivers/phy/st/Kconfig | 11 + drivers/phy/st/Makefile | 1 + drivers/phy/st/phy-stm32-combophy.c | 596 ++++++++++++++++++++++++++++ 3 files changed, 608 insertions(+) create mode 100644 drivers/phy/st/phy-stm32-combophy.c diff --git a/drivers/phy/st/Kconfig b/drivers/phy/st/Kconfig index 3fc3d0781fb8..304614b6dabf 100644 --- a/drivers/phy/st/Kconfig +++ b/drivers/phy/st/Kconfig @@ -33,6 +33,17 @@ config PHY_STIH407_USB Enable this support to enable the picoPHY device used by USB2 and USB3 controllers on STMicroelectronics STiH407 SoC families. =20 +config PHY_STM32_COMBOPHY + tristate "STMicroelectronics COMBOPHY driver for STM32MP25" + depends on ARCH_STM32 || COMPILE_TEST + select GENERIC_PHY + help + Enable this to support the COMBOPHY device used by USB3 or PCIe + controllers on STMicroelectronics STM32MP25 SoC. + This driver controls the COMBOPHY block to generate the PCIe 100Mhz + reference clock from either the external clock generator or HSE + internal SoC clock source. + config PHY_STM32_USBPHYC tristate "STMicroelectronics STM32 USB HS PHY Controller driver" depends on ARCH_STM32 || COMPILE_TEST diff --git a/drivers/phy/st/Makefile b/drivers/phy/st/Makefile index c862dd937b64..cb80e954ea9f 100644 --- a/drivers/phy/st/Makefile +++ b/drivers/phy/st/Makefile @@ -3,4 +3,5 @@ obj-$(CONFIG_PHY_MIPHY28LP) +=3D phy-miphy28lp.o obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) +=3D phy-spear1310-miphy.o obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) +=3D phy-spear1340-miphy.o obj-$(CONFIG_PHY_STIH407_USB) +=3D phy-stih407-usb.o +obj-$(CONFIG_PHY_STM32_COMBOPHY) +=3D phy-stm32-combophy.o obj-$(CONFIG_PHY_STM32_USBPHYC) +=3D phy-stm32-usbphyc.o diff --git a/drivers/phy/st/phy-stm32-combophy.c b/drivers/phy/st/phy-stm32= -combophy.c new file mode 100644 index 000000000000..37ae6b28c7fa --- /dev/null +++ b/drivers/phy/st/phy-stm32-combophy.c @@ -0,0 +1,596 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * STMicroelectronics COMBOPHY STM32MP25 Controller driver. + * + * Copyright (C) 2024 STMicroelectronics + * Author: Christian Bruel + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define SYSCFG_COMBOPHY_CR1 0x4c00 +#define SYSCFG_COMBOPHY_CR2 0x4c04 +#define SYSCFG_COMBOPHY_CR4 0x4c0c +#define SYSCFG_COMBOPHY_CR5 0x4c10 +#define SYSCFG_COMBOPHY_SR 0x4c14 +#define SYSCFG_PCIEPRGCR 0x6080 + +/* SYSCFG PCIEPRGCR */ +#define STM32MP25_PCIEPRGCR_EN BIT(0) +#define STM32MP25_PCIEPRG_IMPCTRL_OHM GENMASK(3, 1) +#define STM32MP25_PCIEPRG_IMPCTRL_VSWING GENMASK(5, 4) + +/* SYSCFG SYSCFG_COMBOPHY_SR */ +#define STM32MP25_PIPE0_PHYSTATUS BIT(1) + +/* SYSCFG CR1 */ +#define SYSCFG_COMBOPHY_CR1_REFUSEPAD BIT(0) +#define SYSCFG_COMBOPHY_CR1_MPLLMULT GENMASK(7, 1) +#define SYSCFG_COMBOPHY_CR1_REFCLKSEL GENMASK(16, 8) +#define SYSCFG_COMBOPHY_CR1_REFCLKDIV2 BIT(17) +#define SYSCFG_COMBOPHY_CR1_REFSSPEN BIT(18) +#define SYSCFG_COMBOPHY_CR1_SSCEN BIT(19) + +/* SYSCFG CR4 */ +#define SYSCFG_COMBOPHY_CR4_RX0_EQ GENMASK(2, 0) + +#define MPLLMULT_19_2 (0x02u << 1) +#define MPLLMULT_20 (0x7du << 1) +#define MPLLMULT_24 (0x68u << 1) +#define MPLLMULT_25 (0x64u << 1) +#define MPLLMULT_26 (0x60u << 1) +#define MPLLMULT_38_4 (0x41u << 1) +#define MPLLMULT_48 (0x6cu << 1) +#define MPLLMULT_50 (0x32u << 1) +#define MPLLMULT_52 (0x30u << 1) +#define MPLLMULT_100 (0x19u << 1) + +#define REFCLKSEL_0 0 +#define REFCLKSEL_1 (0x108u << 8) + +#define REFCLDIV_0 0 + +/* SYSCFG CR2 */ +#define SYSCFG_COMBOPHY_CR2_MODESEL GENMASK(1, 0) +#define SYSCFG_COMBOPHY_CR2_ISO_DIS BIT(15) + +#define COMBOPHY_MODESEL_PCIE 0 +#define COMBOPHY_MODESEL_USB 3 + +/* SYSCFG CR5 */ +#define SYSCFG_COMBOPHY_CR5_COMMON_CLOCKS BIT(12) + +#define COMBOPHY_SUP_ANA_MPLL_LOOP_CTL 0xc0 +#define COMBOPHY_PROP_CNTRL GENMASK(7, 4) + +/* Required apb/ker clocks first, optional pad last. */ +static const char * const combophy_clks[] =3D {"apb", "ker", "pad"}; +#define APB_CLK 0 +#define KER_CLK 1 +#define PAD_CLK 2 + +struct stm32_combophy { + struct phy *phy; + struct regmap *regmap; + struct device *dev; + void __iomem *base; + struct reset_control *phy_reset; + struct clk_bulk_data clks[ARRAY_SIZE(combophy_clks)]; + int num_clks; + bool have_pad_clk; + unsigned int type; + bool is_init; + int irq_wakeup; +}; + +struct clk_impedance { + u32 microohm; + u32 vswing[4]; +}; + +/* + * lookup table to hold the settings needed for a ref clock frequency + * impedance, the offset is used to set the IMP_CTL and DE_EMP bit of the + * PRG_IMP_CTRL register. Use ordered discrete values in the table + */ +static const struct clk_impedance imp_lookup[] =3D { + { 6090000, { 442000, 564000, 684000, 802000 } }, + { 5662000, { 528000, 621000, 712000, 803000 } }, + { 5292000, { 491000, 596000, 700000, 802000 } }, + { 4968000, { 558000, 640000, 722000, 803000 } }, + { 4684000, { 468000, 581000, 692000, 802000 } }, + { 4429000, { 554000, 613000, 717000, 803000 } }, + { 4204000, { 511000, 609000, 706000, 802000 } }, + { 3999000, { 571000, 648000, 726000, 803000 } } +}; + +static int stm32_impedance_tune(struct stm32_combophy *combophy) +{ + u8 imp_size =3D ARRAY_SIZE(imp_lookup); + u8 vswing_size =3D ARRAY_SIZE(imp_lookup[0].vswing); + u8 imp_of, vswing_of; + u32 max_imp =3D imp_lookup[0].microohm; + u32 min_imp =3D imp_lookup[imp_size - 1].microohm; + u32 max_vswing =3D imp_lookup[imp_size - 1].vswing[vswing_size - 1]; + u32 min_vswing =3D imp_lookup[0].vswing[0]; + u32 val; + + if (!of_property_read_u32(combophy->dev->of_node, "st,output-micro-ohms",= &val)) { + if (val < min_imp || val > max_imp) { + dev_err(combophy->dev, "Invalid value %u for output ohm\n", val); + return -EINVAL; + } + + for (imp_of =3D 0; imp_of < ARRAY_SIZE(imp_lookup); imp_of++) + if (imp_lookup[imp_of].microohm <=3D val) + break; + + dev_dbg(combophy->dev, "Set %u micro-ohms output impedance\n", + imp_lookup[imp_of].microohm); + + regmap_update_bits(combophy->regmap, SYSCFG_PCIEPRGCR, + STM32MP25_PCIEPRG_IMPCTRL_OHM, + FIELD_PREP(STM32MP25_PCIEPRG_IMPCTRL_OHM, imp_of)); + } else { + regmap_read(combophy->regmap, SYSCFG_PCIEPRGCR, &val); + imp_of =3D FIELD_GET(STM32MP25_PCIEPRG_IMPCTRL_OHM, val); + } + + if (!of_property_read_u32(combophy->dev->of_node, "st,output-vswing-micro= volt", &val)) { + if (val < min_vswing || val > max_vswing) { + dev_err(combophy->dev, "Invalid value %u for output vswing\n", val); + return -EINVAL; + } + + for (vswing_of =3D 0; vswing_of < ARRAY_SIZE(imp_lookup[imp_of].vswing);= vswing_of++) + if (imp_lookup[imp_of].vswing[vswing_of] >=3D val) + break; + + dev_dbg(combophy->dev, "Set %u microvolt swing\n", + imp_lookup[imp_of].vswing[vswing_of]); + + regmap_update_bits(combophy->regmap, SYSCFG_PCIEPRGCR, + STM32MP25_PCIEPRG_IMPCTRL_VSWING, + FIELD_PREP(STM32MP25_PCIEPRG_IMPCTRL_VSWING, vswing_of)); + } + + return 0; +} + +static int stm32_combophy_pll_init(struct stm32_combophy *combophy) +{ + int ret; + u32 refclksel, pllmult, propcntrl, val; + u32 clk_rate; + struct clk *clk; + u32 cr1_val =3D 0, cr1_mask =3D 0; + + if (combophy->have_pad_clk) + clk =3D combophy->clks[PAD_CLK].clk; + else + clk =3D combophy->clks[KER_CLK].clk; + + clk_rate =3D clk_get_rate(clk); + + dev_dbg(combophy->dev, "%s pll init rate %d\n", + combophy->have_pad_clk ? "External" : "Ker", clk_rate); + + if (combophy->type !=3D PHY_TYPE_PCIE) { + cr1_mask |=3D SYSCFG_COMBOPHY_CR1_REFSSPEN; + cr1_val |=3D SYSCFG_COMBOPHY_CR1_REFSSPEN; + } + + if (of_property_present(combophy->dev->of_node, "st,ssc-on")) { + dev_dbg(combophy->dev, "Enabling clock with SSC\n"); + cr1_mask |=3D SYSCFG_COMBOPHY_CR1_SSCEN; + cr1_val |=3D SYSCFG_COMBOPHY_CR1_SSCEN; + } + + switch (clk_rate) { + case 100000000: + pllmult =3D MPLLMULT_100; + refclksel =3D REFCLKSEL_0; + propcntrl =3D 0x8u << 4; + break; + case 19200000: + pllmult =3D MPLLMULT_19_2; + refclksel =3D REFCLKSEL_1; + propcntrl =3D 0x8u << 4; + break; + case 25000000: + pllmult =3D MPLLMULT_25; + refclksel =3D REFCLKSEL_0; + propcntrl =3D 0xeu << 4; + break; + case 24000000: + pllmult =3D MPLLMULT_24; + refclksel =3D REFCLKSEL_1; + propcntrl =3D 0xeu << 4; + break; + case 20000000: + pllmult =3D MPLLMULT_20; + refclksel =3D REFCLKSEL_0; + propcntrl =3D 0xeu << 4; + break; + default: + dev_err(combophy->dev, "Invalid rate 0x%x\n", clk_rate); + return -EINVAL; + }; + + cr1_mask |=3D SYSCFG_COMBOPHY_CR1_REFCLKDIV2; + cr1_val |=3D REFCLDIV_0; + + cr1_mask |=3D SYSCFG_COMBOPHY_CR1_REFCLKSEL; + cr1_val |=3D refclksel; + + cr1_mask |=3D SYSCFG_COMBOPHY_CR1_MPLLMULT; + cr1_val |=3D pllmult; + + /* + * vddcombophy is interconnected with vddcore. Isolation bit should be un= set + * before using the ComboPHY. + */ + regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR2, + SYSCFG_COMBOPHY_CR2_ISO_DIS, SYSCFG_COMBOPHY_CR2_ISO_DIS); + + reset_control_assert(combophy->phy_reset); + + if (combophy->type =3D=3D PHY_TYPE_PCIE) { + ret =3D stm32_impedance_tune(combophy); + if (ret) + goto out_iso; + + cr1_mask |=3D SYSCFG_COMBOPHY_CR1_REFUSEPAD; + cr1_val |=3D combophy->have_pad_clk ? SYSCFG_COMBOPHY_CR1_REFUSEPAD : 0; + } + + if (!of_property_read_u32(combophy->dev->of_node, "st,rx-equalizer", &val= )) { + dev_dbg(combophy->dev, "Set RX equalizer %u\n", val); + if (val > SYSCFG_COMBOPHY_CR4_RX0_EQ) { + dev_err(combophy->dev, "Invalid value %u for rx0 equalizer\n", val); + ret =3D -EINVAL; + goto out_iso; + } + + regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR4, + SYSCFG_COMBOPHY_CR4_RX0_EQ, val); + } + + regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR1, cr1_mask, cr1_v= al); + + /* + * Force elasticity buffer to be tuned for the reference clock as + * the separated clock model is not supported + */ + regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR5, + SYSCFG_COMBOPHY_CR5_COMMON_CLOCKS, SYSCFG_COMBOPHY_CR5_COMMON_CLOCKS= ); + + reset_control_deassert(combophy->phy_reset); + + ret =3D regmap_read_poll_timeout(combophy->regmap, SYSCFG_COMBOPHY_SR, va= l, + !(val & STM32MP25_PIPE0_PHYSTATUS), + 10, 1000); + if (ret) { + dev_err(combophy->dev, "timeout, cannot lock PLL\n"); + if (combophy->type =3D=3D PHY_TYPE_PCIE && !combophy->have_pad_clk) + regmap_update_bits(combophy->regmap, SYSCFG_PCIEPRGCR, + STM32MP25_PCIEPRGCR_EN, 0); + + if (combophy->type !=3D PHY_TYPE_PCIE) + regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR1, + SYSCFG_COMBOPHY_CR1_REFSSPEN, 0); + + goto out; + } + + + if (combophy->type =3D=3D PHY_TYPE_PCIE) { + if (!combophy->have_pad_clk) + regmap_update_bits(combophy->regmap, SYSCFG_PCIEPRGCR, + STM32MP25_PCIEPRGCR_EN, STM32MP25_PCIEPRGCR_EN); + + val =3D readl_relaxed(combophy->base + COMBOPHY_SUP_ANA_MPLL_LOOP_CTL); + val &=3D ~COMBOPHY_PROP_CNTRL; + val |=3D propcntrl; + writel_relaxed(val, combophy->base + COMBOPHY_SUP_ANA_MPLL_LOOP_CTL); + } + + return 0; + +out_iso: + reset_control_deassert(combophy->phy_reset); + +out: + regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR2, + SYSCFG_COMBOPHY_CR2_ISO_DIS, 0); + + return ret; +} + +static struct phy *stm32_combophy_xlate(struct device *dev, + const struct of_phandle_args *args) +{ + struct stm32_combophy *combophy =3D dev_get_drvdata(dev); + unsigned int type; + + if (args->args_count !=3D 1) { + dev_err(dev, "invalid number of cells in 'phy' property\n"); + return ERR_PTR(-EINVAL); + } + + type =3D args->args[0]; + if (type !=3D PHY_TYPE_USB3 && type !=3D PHY_TYPE_PCIE) { + dev_err(dev, "unsupported device type: %d\n", type); + return ERR_PTR(-EINVAL); + } + + if (combophy->have_pad_clk && type !=3D PHY_TYPE_PCIE) { + dev_err(dev, "Invalid use of clk_pad for USB3 mode\n"); + return ERR_PTR(-EINVAL); + } + + combophy->type =3D type; + + return combophy->phy; +} + +static int stm32_combophy_set_mode(struct stm32_combophy *combophy) +{ + int type =3D combophy->type; + u32 val; + + switch (type) { + case PHY_TYPE_PCIE: + dev_dbg(combophy->dev, "setting PCIe ComboPHY\n"); + val =3D COMBOPHY_MODESEL_PCIE; + break; + case PHY_TYPE_USB3: + dev_dbg(combophy->dev, "setting USB3 ComboPHY\n"); + val =3D COMBOPHY_MODESEL_USB; + break; + default: + dev_err(combophy->dev, "Invalid PHY mode %d\n", type); + return -EINVAL; + } + + return regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR2, + SYSCFG_COMBOPHY_CR2_MODESEL, val); +} + +static int stm32_combophy_suspend_noirq(struct device *dev) +{ + struct stm32_combophy *combophy =3D dev_get_drvdata(dev); + + /* + * Clocks should be turned off since it is not needed for + * wakeup capability. In case usb-remote wakeup is not enabled, + * combo-phy is already turned off by HCD driver using exit callback + */ + if (combophy->is_init) { + clk_bulk_disable_unprepare(combophy->num_clks, combophy->clks); + + /* since wakeup is enabled for ctrl */ + enable_irq_wake(combophy->irq_wakeup); + } + + return 0; +} + +static int stm32_combophy_resume_noirq(struct device *dev) +{ + struct stm32_combophy *combophy =3D dev_get_drvdata(dev); + int ret; + + /* + * If clocks was turned off by suspend call for wakeup then needs + * to be turned back ON in resume. In case usb-remote wakeup is not + * enabled, clocks already turned ON by HCD driver using init callback + */ + if (combophy->is_init) { + /* since wakeup was enabled for ctrl */ + disable_irq_wake(combophy->irq_wakeup); + + ret =3D clk_bulk_prepare_enable(combophy->num_clks, combophy->clks); + if (ret) { + dev_err(dev, "can't enable clocks (%d)\n", ret); + return ret; + } + } + + return 0; +} + +static int stm32_combophy_exit(struct phy *phy) +{ + struct stm32_combophy *combophy =3D phy_get_drvdata(phy); + struct device *dev =3D combophy->dev; + + combophy->is_init =3D false; + + if (combophy->type =3D=3D PHY_TYPE_PCIE && !combophy->have_pad_clk) + regmap_update_bits(combophy->regmap, SYSCFG_PCIEPRGCR, + STM32MP25_PCIEPRGCR_EN, 0); + + if (combophy->type !=3D PHY_TYPE_PCIE) + regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR1, + SYSCFG_COMBOPHY_CR1_REFSSPEN, 0); + + regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR2, + SYSCFG_COMBOPHY_CR2_ISO_DIS, 0); + + clk_bulk_disable_unprepare(combophy->num_clks, combophy->clks); + + pm_runtime_put_noidle(dev); + + return 0; +} + +static int stm32_combophy_init(struct phy *phy) +{ + struct stm32_combophy *combophy =3D phy_get_drvdata(phy); + struct device *dev =3D combophy->dev; + int ret; + + pm_runtime_get_noresume(dev); + + ret =3D clk_bulk_prepare_enable(combophy->num_clks, combophy->clks); + if (ret) { + dev_err(dev, "can't enable clocks (%d)\n", ret); + pm_runtime_put_noidle(dev); + return ret; + } + + ret =3D stm32_combophy_set_mode(combophy); + if (ret) { + dev_err(dev, "combophy mode not set\n"); + clk_bulk_disable_unprepare(combophy->num_clks, combophy->clks); + pm_runtime_put_noidle(dev); + return ret; + } + + ret =3D stm32_combophy_pll_init(combophy); + if (ret) { + clk_bulk_disable_unprepare(combophy->num_clks, combophy->clks); + pm_runtime_put_noidle(dev); + return ret; + } + + pm_runtime_disable(dev); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + + combophy->is_init =3D true; + + return ret; +} + +static const struct phy_ops stm32_combophy_phy_data =3D { + .init =3D stm32_combophy_init, + .exit =3D stm32_combophy_exit, + .owner =3D THIS_MODULE +}; + +static irqreturn_t stm32_combophy_irq_wakeup_handler(int irq, void *dev_id) +{ + return IRQ_HANDLED; +} + +static int stm32_combophy_get_clocks(struct stm32_combophy *combophy) +{ + int i, ret; + + for (i =3D 0; i < ARRAY_SIZE(combophy_clks); i++) + combophy->clks[i].id =3D combophy_clks[i]; + + combophy->num_clks =3D ARRAY_SIZE(combophy_clks) - 1; + + ret =3D devm_clk_bulk_get(combophy->dev, combophy->num_clks, combophy->cl= ks); + if (ret) + return ret; + + ret =3D devm_clk_bulk_get_optional(combophy->dev, 1, combophy->clks + com= bophy->num_clks); + if (ret) + return ret; + + if (combophy->clks[combophy->num_clks].clk !=3D NULL) { + combophy->have_pad_clk =3D true; + combophy->num_clks++; + } + + return 0; +} + +static int stm32_combophy_probe(struct platform_device *pdev) +{ + struct stm32_combophy *combophy; + struct device *dev =3D &pdev->dev; + struct phy_provider *phy_provider; + int ret, irq; + + combophy =3D devm_kzalloc(dev, sizeof(*combophy), GFP_KERNEL); + if (!combophy) + return -ENOMEM; + + combophy->dev =3D dev; + + dev_set_drvdata(dev, combophy); + + combophy->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(combophy->base)) + return PTR_ERR(combophy->base); + + if (stm32_combophy_get_clocks(combophy)) + return ret; + + combophy->phy_reset =3D devm_reset_control_get_exclusive(dev, "phy"); + if (IS_ERR(combophy->phy_reset)) + return dev_err_probe(dev, PTR_ERR(combophy->phy_reset), + "Failed to get PHY reset\n"); + + combophy->regmap =3D syscon_regmap_lookup_by_compatible("st,stm32mp25-sys= cfg"); + if (IS_ERR(combophy->regmap)) + return dev_err_probe(dev, PTR_ERR(combophy->regmap), + "No syscfg specified\n"); + + combophy->phy =3D devm_phy_create(dev, NULL, &stm32_combophy_phy_data); + if (IS_ERR(combophy->phy)) + return dev_err_probe(dev, PTR_ERR(combophy->phy), + "failed to create PCIe/USB3 ComboPHY\n"); + + if (device_property_read_bool(dev, "wakeup-source")) { + irq =3D platform_get_irq(pdev, 0); + if (irq < 0) + return dev_err_probe(dev, irq, "failed to get IRQ\n"); + combophy->irq_wakeup =3D irq; + + ret =3D devm_request_threaded_irq(dev, combophy->irq_wakeup, NULL, + stm32_combophy_irq_wakeup_handler, IRQF_ONESHOT, + NULL, NULL); + if (ret) + return dev_err_probe(dev, ret, "unable to request wake IRQ %d\n", + combophy->irq_wakeup); + } + + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable pm runtime\n"); + + phy_set_drvdata(combophy->phy, combophy); + + phy_provider =3D devm_of_phy_provider_register(dev, stm32_combophy_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct dev_pm_ops stm32_combophy_pm_ops =3D { + NOIRQ_SYSTEM_SLEEP_PM_OPS(stm32_combophy_suspend_noirq, + stm32_combophy_resume_noirq) +}; + +static const struct of_device_id stm32_combophy_of_match[] =3D { + { .compatible =3D "st,stm32mp25-combophy", }, + { }, +}; +MODULE_DEVICE_TABLE(of, stm32_combophy_of_match); + +static struct platform_driver stm32_combophy_driver =3D { + .probe =3D stm32_combophy_probe, + .driver =3D { + .name =3D "stm32-combophy", + .of_match_table =3D stm32_combophy_of_match, + .pm =3D pm_sleep_ptr(&stm32_combophy_pm_ops) + } +}; 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charset="utf-8" Add myself as STM32MP25 COMBOPHY maintainer Signed-off-by: Christian Bruel --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a70b7c9c3533..73fd76dab699 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21908,6 +21908,12 @@ F: drivers/*/stm32-*timer* F: drivers/pwm/pwm-stm32* F: include/linux/*/stm32-*tim* =20 +STM32MP25 USB3/PCIE COMBOPHY DRIVER +M: Christian Bruel +S: Maintained +F: Documentation/devicetree/bindings/phy/st,stm32mp25-combophy.yaml +F: drivers/phy/st/phy-stm32-combophy.c + STMMAC ETHERNET DRIVER M: Alexandre Torgue M: Jose Abreu --=20 2.34.1 From nobody Sat Nov 30 05:39:37 2024 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 640531862AE; Wed, 11 Sep 2024 10:51:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Add support for COMBOPHY which is used either by the USB3 and PCIe controller. USB3 or PCIe mode is done with phy_set_mode(). PCIe internal reference clock can be generated from the internal clock source or optionnaly from an external 100Mhz pad. Signed-off-by: Christian Bruel --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 1167cf63d7e8..b596afec1b6e 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include =20 / { #address-cells =3D <2>; @@ -518,6 +519,21 @@ i2c8: i2c@46040000 { status =3D "disabled"; }; =20 + combophy: phy@480c0000 { + compatible =3D "st,stm32mp25-combophy"; + reg =3D <0x480c0000 0x1000>; + #phy-cells =3D <1>; + clocks =3D <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>; + clock-names =3D "apb", "ker"; + resets =3D <&rcc USB3PCIEPHY_R>; + reset-names =3D "phy"; + access-controllers =3D <&rifsc 67>; + power-domains =3D <&CLUSTER_PD>; + wakeup-source; + interrupts-extended =3D <&exti1 45 IRQ_TYPE_EDGE_FALLING>; + status =3D "disabled"; + }; + sdmmc1: mmc@48220000 { compatible =3D "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 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Wed, 11 Sep 2024 12:51:49 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 43E7F40044; Wed, 11 Sep 2024 12:50:32 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 982E5266D3A; Wed, 11 Sep 2024 12:48:05 +0200 (CEST) Received: from localhost (10.129.178.212) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Wed, 11 Sep 2024 12:48:05 +0200 From: Christian Bruel To: , , , , , , , CC: , , , , , , Christian Bruel Subject: [PATCH v8 5/5] arm64: dts: st: Enable COMBOPHY on the stm32mp257f-ev1 board Date: Wed, 11 Sep 2024 12:46:46 +0200 Message-ID: <20240911104646.2980821-6-christian.bruel@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240911104646.2980821-1-christian.bruel@foss.st.com> References: <20240911104646.2980821-1-christian.bruel@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Type: text/plain; charset="utf-8" Enable the COMBOPHY with external pad clock on stm32mp257f-ev1 board, to be used for the PCIe clock provider. Signed-off-by: Christian Bruel --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/d= ts/st/stm32mp257f-ev1.dts index 214191a8322b..bcf84d533cb2 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -27,6 +27,14 @@ chosen { stdout-path =3D "serial0:115200n8"; }; =20 + clocks { + pad_clk: pad-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <100000000>; + }; + }; + memory@80000000 { device_type =3D "memory"; reg =3D <0x0 0x80000000 0x1 0x0>; @@ -50,6 +58,12 @@ &arm_wdt { status =3D "okay"; }; =20 +&combophy { + clocks =3D <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>, <&pad_cl= k>; + clock-names =3D "apb", "ker", "pad"; + status =3D "okay"; +}; + ðernet2 { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <ð2_rgmii_pins_a>; --=20 2.34.1