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Wed, 11 Sep 2024 05:39:00 -0500 From: Manikanta Guntupalli To: , , , , , CC: , , , , Manikanta Guntupalli Subject: [PATCH V2 1/3] i2c: cadence: Relocate cdns_i2c_runtime_suspend and cdns_i2c_runtime_resume to facilitate atomic mode Date: Wed, 11 Sep 2024 16:08:50 +0530 Message-ID: <20240911103852.162234-2-manikanta.guntupalli@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240911103852.162234-1-manikanta.guntupalli@amd.com> References: <20240911103852.162234-1-manikanta.guntupalli@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002324:EE_|BY1PR12MB8448:EE_ X-MS-Office365-Filtering-Correlation-Id: 67b6a601-8a8f-4477-f21c-08dcd24df591 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2024 10:39:05.2502 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 67b6a601-8a8f-4477-f21c-08dcd24df591 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002324.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR12MB8448 Content-Type: text/plain; charset="utf-8" Relocate cdns_i2c_runtime_suspend, cdns_i2c_runtime_resume and cdns_i2c_init functions to avoid prototype statement in atomic mode changes. Signed-off-by: Manikanta Guntupalli Reviewed-by: Andi Shyti --- Changes for V2: Added review signature. --- drivers/i2c/busses/i2c-cadence.c | 120 +++++++++++++++---------------- 1 file changed, 60 insertions(+), 60 deletions(-) diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cade= nce.c index 87b9ba95b2e1..d3f6ca2cb4d7 100644 --- a/drivers/i2c/busses/i2c-cadence.c +++ b/drivers/i2c/busses/i2c-cadence.c @@ -228,6 +228,66 @@ struct cdns_platform_data { #define to_cdns_i2c(_nb) container_of(_nb, struct cdns_i2c, \ clk_rate_change_nb) =20 +/** + * cdns_i2c_init - Controller initialisation + * @id: Device private data structure + * + * Initialise the i2c controller. + * + */ +static void cdns_i2c_init(struct cdns_i2c *id) +{ + cdns_i2c_writereg(id->ctrl_reg, CDNS_I2C_CR_OFFSET); + /* + * Cadence I2C controller has a bug wherein it generates + * invalid read transaction after HW timeout in master receiver mode. + * HW timeout is not used by this driver and the interrupt is disabled. + * But the feature itself cannot be disabled. Hence maximum value + * is written to this register to reduce the chances of error. + */ + cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET); +} + +/** + * cdns_i2c_runtime_suspend - Runtime suspend method for the driver + * @dev: Address of the platform_device structure + * + * Put the driver into low power mode. + * + * Return: 0 always + */ +static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev) +{ + struct cdns_i2c *xi2c =3D dev_get_drvdata(dev); + + clk_disable(xi2c->clk); + + return 0; +} + +/** + * cdns_i2c_runtime_resume - Runtime resume + * @dev: Address of the platform_device structure + * + * Runtime resume callback. + * + * Return: 0 on success and error value on error + */ +static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev) +{ + struct cdns_i2c *xi2c =3D dev_get_drvdata(dev); + int ret; + + ret =3D clk_enable(xi2c->clk); + if (ret) { + dev_err(dev, "Cannot enable clock.\n"); + return ret; + } + cdns_i2c_init(xi2c); + + return 0; +} + /** * cdns_i2c_clear_bus_hold - Clear bus hold bit * @id: Pointer to driver data struct @@ -1158,23 +1218,6 @@ static int cdns_i2c_clk_notifier_cb(struct notifier_= block *nb, unsigned long } } =20 -/** - * cdns_i2c_runtime_suspend - Runtime suspend method for the driver - * @dev: Address of the platform_device structure - * - * Put the driver into low power mode. - * - * Return: 0 always - */ -static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev) -{ - struct cdns_i2c *xi2c =3D dev_get_drvdata(dev); - - clk_disable(xi2c->clk); - - return 0; -} - static int __maybe_unused cdns_i2c_suspend(struct device *dev) { struct cdns_i2c *xi2c =3D dev_get_drvdata(dev); @@ -1187,49 +1230,6 @@ static int __maybe_unused cdns_i2c_suspend(struct de= vice *dev) return 0; } =20 -/** - * cdns_i2c_init - Controller initialisation - * @id: Device private data structure - * - * Initialise the i2c controller. - * - */ -static void cdns_i2c_init(struct cdns_i2c *id) -{ - cdns_i2c_writereg(id->ctrl_reg, CDNS_I2C_CR_OFFSET); - /* - * Cadence I2C controller has a bug wherein it generates - * invalid read transaction after HW timeout in master receiver mode. - * HW timeout is not used by this driver and the interrupt is disabled. - * But the feature itself cannot be disabled. Hence maximum value - * is written to this register to reduce the chances of error. - */ - cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET); -} - -/** - * cdns_i2c_runtime_resume - Runtime resume - * @dev: Address of the platform_device structure - * - * Runtime resume callback. - * - * Return: 0 on success and error value on error - */ -static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev) -{ - struct cdns_i2c *xi2c =3D dev_get_drvdata(dev); - int ret; - - ret =3D clk_enable(xi2c->clk); - if (ret) { - dev_err(dev, "Cannot enable clock.\n"); - return ret; - } - cdns_i2c_init(xi2c); - - return 0; -} - static int __maybe_unused cdns_i2c_resume(struct device *dev) { struct cdns_i2c *xi2c =3D dev_get_drvdata(dev); --=20 2.25.1 From nobody Sat Nov 30 05:42:58 2024 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2087.outbound.protection.outlook.com [40.107.236.87]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB388184530; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2024 10:39:10.7827 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1fd177c0-60d2-4fad-8410-08dcd24df8e0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002326.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5903 Content-Type: text/plain; charset="utf-8" The cdns_i2c_master_xfer function has been refactored to separate the common code. This change facilitates better support for atomic mode operations by isolating the shared logic. Signed-off-by: Manikanta Guntupalli Reviewed-by: Andi Shyti --- Changes for V2: Added review signature. --- drivers/i2c/busses/i2c-cadence.c | 100 ++++++++++++++++--------------- 1 file changed, 53 insertions(+), 47 deletions(-) diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cade= nce.c index d3f6ca2cb4d7..e689448d229f 100644 --- a/drivers/i2c/busses/i2c-cadence.c +++ b/drivers/i2c/busses/i2c-cadence.c @@ -866,46 +866,14 @@ static int cdns_i2c_process_msg(struct cdns_i2c *id, = struct i2c_msg *msg, return 0; } =20 -/** - * cdns_i2c_master_xfer - The main i2c transfer function - * @adap: pointer to the i2c adapter driver instance - * @msgs: pointer to the i2c message structure - * @num: the number of messages to transfer - * - * Initiates the send/recv activity based on the transfer message received. - * - * Return: number of msgs processed on success, negative error otherwise - */ -static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *= msgs, - int num) +static int cdns_i2c_master_common_xfer(struct i2c_adapter *adap, + struct i2c_msg *msgs, + int num) { int ret, count; u32 reg; struct cdns_i2c *id =3D adap->algo_data; bool hold_quirk; -#if IS_ENABLED(CONFIG_I2C_SLAVE) - bool change_role =3D false; -#endif - - ret =3D pm_runtime_resume_and_get(id->dev); - if (ret < 0) - return ret; - -#if IS_ENABLED(CONFIG_I2C_SLAVE) - /* Check i2c operating mode and switch if possible */ - if (id->dev_mode =3D=3D CDNS_I2C_MODE_SLAVE) { - if (id->slave_state !=3D CDNS_I2C_SLAVE_STATE_IDLE) { - ret =3D -EAGAIN; - goto out; - } - - /* Set mode to master */ - cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id); - - /* Mark flag to change role once xfer is completed */ - change_role =3D true; - } -#endif =20 /* Check if the bus is free */ =20 @@ -917,7 +885,7 @@ static int cdns_i2c_master_xfer(struct i2c_adapter *ada= p, struct i2c_msg *msgs, ret =3D -EAGAIN; if (id->adap.bus_recovery_info) i2c_recover_bus(adap); - goto out; + return ret; } =20 hold_quirk =3D !!(id->quirks & CDNS_I2C_BROKEN_HOLD_BIT); @@ -937,8 +905,7 @@ static int cdns_i2c_master_xfer(struct i2c_adapter *ada= p, struct i2c_msg *msgs, if (msgs[count].flags & I2C_M_RD) { dev_warn(adap->dev.parent, "Can't do repeated start after a receive message\n"); - ret =3D -EOPNOTSUPP; - goto out; + return -EOPNOTSUPP; } } id->bus_hold_flag =3D 1; @@ -956,26 +923,65 @@ static int cdns_i2c_master_xfer(struct i2c_adapter *a= dap, struct i2c_msg *msgs, =20 ret =3D cdns_i2c_process_msg(id, msgs, adap); if (ret) - goto out; + return ret; =20 /* Report the other error interrupts to application */ if (id->err_status) { cdns_i2c_master_reset(adap); =20 - if (id->err_status & CDNS_I2C_IXR_NACK) { - ret =3D -ENXIO; - goto out; - } - ret =3D -EIO; - goto out; + if (id->err_status & CDNS_I2C_IXR_NACK) + return -ENXIO; + + return -EIO; } } + return 0; +} =20 - ret =3D num; +/** + * cdns_i2c_master_xfer - The main i2c transfer function + * @adap: pointer to the i2c adapter driver instance + * @msgs: pointer to the i2c message structure + * @num: the number of messages to transfer + * + * Initiates the send/recv activity based on the transfer message received. + * + * Return: number of msgs processed on success, negative error otherwise + */ +static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *= msgs, + int num) +{ + int ret; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2024 10:39:16.0351 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 501ef58d-c553-44a5-94e1-08dcd24dfbff X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002321.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6361 Content-Type: text/plain; charset="utf-8" Rework the read and write code paths in the driver to support operation in atomic contexts in master mode. This change does not apply to slave mode because there is no way to handle interruptions in that context. Adjust the message timeout to include some extra time. For non-atomic contexts, 500 ms is added to the timeout. For atomic contexts, 2000 ms is added because transfers happen in polled mode, requiring more time to account for the polling overhead. Similar changes have been implemented in other drivers, including: commit 3a5ee18d2a32 ("i2c: imx: implement master_xfer_atomic callback") commit 445094c8a9fb ("i2c: exynos5: add support for atomic transfers") commit ede2299f7101 ("i2c: tegra: Support atomic transfers") commit fe402bd09049 ("i2c: meson: implement the master_xfer_atomic callback") Signed-off-by: Manikanta Guntupalli --- Changes for V2: Simplify the return statement of cdns_i2c_error_check(). Update description. Remove unnecessary typecast. Update if-else to reduce a level of indentation. Expand *id->p_recv_buf++ to have clear operation precedence. Move variables to inside while block in cdns_i2c_mrecv_atomic() and cdns_i2c_msend_rem_atomic(). --- drivers/i2c/busses/i2c-cadence.c | 207 ++++++++++++++++++++++++++++--- 1 file changed, 192 insertions(+), 15 deletions(-) diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cade= nce.c index e689448d229f..ee2f32cd54ce 100644 --- a/drivers/i2c/busses/i2c-cadence.c +++ b/drivers/i2c/busses/i2c-cadence.c @@ -129,6 +129,7 @@ =20 #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0) #define CDNS_I2C_POLL_US 100000 +#define CDNS_I2C_POLL_US_ATOMIC 10 #define CDNS_I2C_TIMEOUT_US 500000 =20 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset) @@ -189,6 +190,8 @@ enum cdns_i2c_slave_state { * @slave_state: I2C Slave state(idle/read/write). * @fifo_depth: The depth of the transfer FIFO * @transfer_size: The maximum number of bytes in one transfer + * @atomic: Mode of transfer + * @err_status_atomic: Error status in atomic mode */ struct cdns_i2c { struct device *dev; @@ -219,6 +222,8 @@ struct cdns_i2c { #endif u32 fifo_depth; unsigned int transfer_size; + bool atomic; + int err_status_atomic; }; =20 struct cdns_platform_data { @@ -256,7 +261,7 @@ static void cdns_i2c_init(struct cdns_i2c *id) * * Return: 0 always */ -static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev) +static int cdns_i2c_runtime_suspend(struct device *dev) { struct cdns_i2c *xi2c =3D dev_get_drvdata(dev); =20 @@ -273,7 +278,7 @@ static int __maybe_unused cdns_i2c_runtime_suspend(stru= ct device *dev) * * Return: 0 on success and error value on error */ -static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev) +static int cdns_i2c_runtime_resume(struct device *dev) { struct cdns_i2c *xi2c =3D dev_get_drvdata(dev); int ret; @@ -621,6 +626,89 @@ static irqreturn_t cdns_i2c_isr(int irq, void *ptr) return cdns_i2c_master_isr(ptr); } =20 +static bool cdns_i2c_error_check(struct cdns_i2c *id) +{ + unsigned int isr_status; + + id->err_status =3D 0; + + isr_status =3D cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); + cdns_i2c_writereg(isr_status & CDNS_I2C_IXR_ERR_INTR_MASK, CDNS_I2C_ISR_O= FFSET); + + id->err_status =3D isr_status & CDNS_I2C_IXR_ERR_INTR_MASK; + + return !!id->err_status; +} + +static void cdns_i2c_mrecv_atomic(struct cdns_i2c *id) +{ + while (id->recv_count > 0) { + bool updatetx; + + /* + * Check if transfer size register needs to be updated again for a + * large data receive operation. + */ + updatetx =3D id->recv_count > id->curr_recv_count; + + while (id->curr_recv_count > 0) { + if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_RXDV) { + *id->p_recv_buf =3D cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET); + id->p_recv_buf++; + id->recv_count--; + id->curr_recv_count--; + + /* + * Clear the hold bit that was set for FIFO control, + * if the remaining RX data is less than or equal to + * the FIFO depth, unless a repeated start is selected. + */ + if (id->recv_count <=3D id->fifo_depth && !id->bus_hold_flag) + cdns_i2c_clear_bus_hold(id); + } + if (cdns_i2c_error_check(id)) + return; + if (cdns_is_holdquirk(id, updatetx)) + break; + } + + /* + * The controller sends NACK to the slave/target when transfer size + * register reaches zero without considering the HOLD bit. + * This workaround is implemented for large data transfers to + * maintain transfer size non-zero while performing a large + * receive operation. + */ + if (cdns_is_holdquirk(id, updatetx)) { + /* wait while fifo is full */ + while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) !=3D + (id->curr_recv_count - id->fifo_depth)) + ; + + /* + * Check number of bytes to be received against maximum + * transfer size and update register accordingly. + */ + if ((id->recv_count - id->fifo_depth) > + id->transfer_size) { + cdns_i2c_writereg(id->transfer_size, + CDNS_I2C_XFER_SIZE_OFFSET); + id->curr_recv_count =3D id->transfer_size + + id->fifo_depth; + } else { + cdns_i2c_writereg(id->recv_count - + id->fifo_depth, + CDNS_I2C_XFER_SIZE_OFFSET); + id->curr_recv_count =3D id->recv_count; + } + } + } + + /* Clear hold (if not repeated start) */ + if (!id->recv_count && !id->bus_hold_flag) + cdns_i2c_clear_bus_hold(id); +} + /** * cdns_i2c_mrecv - Prepare and start a master receive operation * @id: pointer to the i2c device structure @@ -715,7 +803,34 @@ static void cdns_i2c_mrecv(struct cdns_i2c *id) cdns_i2c_writereg(addr, CDNS_I2C_ADDR_OFFSET); } =20 - cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET); + if (!id->atomic) + cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET); + else + cdns_i2c_mrecv_atomic(id); +} + +static void cdns_i2c_msend_rem_atomic(struct cdns_i2c *id) +{ + while (id->send_count) { + unsigned int avail_bytes; + unsigned int bytes_to_send; + + avail_bytes =3D id->fifo_depth - cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFF= SET); + if (id->send_count > avail_bytes) + bytes_to_send =3D avail_bytes; + else + bytes_to_send =3D id->send_count; + + while (bytes_to_send--) { + cdns_i2c_writereg((*id->p_send_buf++), CDNS_I2C_DATA_OFFSET); + id->send_count--; + } + if (cdns_i2c_error_check(id)) + return; + } + + if (!id->send_count && !id->bus_hold_flag) + cdns_i2c_clear_bus_hold(id); } =20 /** @@ -778,7 +893,10 @@ static void cdns_i2c_msend(struct cdns_i2c *id) cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK, CDNS_I2C_ADDR_OFFSET); =20 - cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET); + if (!id->atomic) + cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET); + else if (id->send_count > 0) + cdns_i2c_msend_rem_atomic(id); } =20 /** @@ -818,7 +936,8 @@ static int cdns_i2c_process_msg(struct cdns_i2c *id, st= ruct i2c_msg *msg, =20 id->p_msg =3D msg; id->err_status =3D 0; - reinit_completion(&id->xfer_done); + if (!id->atomic) + reinit_completion(&id->xfer_done); =20 /* Check for the TEN Bit mode on each msg */ reg =3D cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); @@ -840,14 +959,31 @@ static int cdns_i2c_process_msg(struct cdns_i2c *id, = struct i2c_msg *msg, =20 /* Minimal time to execute this message */ msg_timeout =3D msecs_to_jiffies((1000 * msg->len * BITS_PER_BYTE) / id->= i2c_clk); - /* Plus some wiggle room */ - msg_timeout +=3D msecs_to_jiffies(500); + + /* + * Plus some wiggle room. + * For non-atomic contexts, 500 ms is added to the timeout. + * For atomic contexts, 2000 ms is added because transfers happen in poll= ed + * mode, requiring more time to account for the polling overhead. + */ + if (!id->atomic) + msg_timeout +=3D msecs_to_jiffies(500); + else + msg_timeout +=3D msecs_to_jiffies(2000); =20 if (msg_timeout < adap->timeout) msg_timeout =3D adap->timeout; =20 - /* Wait for the signal of completion */ - time_left =3D wait_for_completion_timeout(&id->xfer_done, msg_timeout); + if (!id->atomic) { + /* Wait for the signal of completion */ + time_left =3D wait_for_completion_timeout(&id->xfer_done, msg_timeout); + } else { + /* 0 is success, -ETIMEDOUT is error */ + time_left =3D !readl_poll_timeout_atomic(id->membase + CDNS_I2C_ISR_OFFS= ET, + reg, (reg & CDNS_I2C_IXR_COMP), + CDNS_I2C_POLL_US_ATOMIC, msg_timeout); + } + if (time_left =3D=3D 0) { cdns_i2c_master_reset(adap); return -ETIMEDOUT; @@ -876,11 +1012,16 @@ static int cdns_i2c_master_common_xfer(struct i2c_ad= apter *adap, bool hold_quirk; =20 /* Check if the bus is free */ - - ret =3D readl_relaxed_poll_timeout(id->membase + CDNS_I2C_SR_OFFSET, - reg, - !(reg & CDNS_I2C_SR_BA), - CDNS_I2C_POLL_US, CDNS_I2C_TIMEOUT_US); + if (!id->atomic) + ret =3D readl_relaxed_poll_timeout(id->membase + CDNS_I2C_SR_OFFSET, + reg, + !(reg & CDNS_I2C_SR_BA), + CDNS_I2C_POLL_US, CDNS_I2C_TIMEOUT_US); + else + ret =3D readl_poll_timeout_atomic(id->membase + CDNS_I2C_SR_OFFSET, + reg, + !(reg & CDNS_I2C_SR_BA), + CDNS_I2C_POLL_US_ATOMIC, CDNS_I2C_TIMEOUT_US); if (ret) { ret =3D -EAGAIN; if (id->adap.bus_recovery_info) @@ -926,7 +1067,7 @@ static int cdns_i2c_master_common_xfer(struct i2c_adap= ter *adap, return ret; =20 /* Report the other error interrupts to application */ - if (id->err_status) { + if (id->err_status || id->err_status_atomic) { cdns_i2c_master_reset(adap); =20 if (id->err_status & CDNS_I2C_IXR_NACK) @@ -992,6 +1133,41 @@ static int cdns_i2c_master_xfer(struct i2c_adapter *a= dap, struct i2c_msg *msgs, return ret; } =20 +/** + * cdns_i2c_master_xfer_atomic - The i2c transfer function in atomic mode + * @adap: pointer to the i2c adapter driver instance + * @msgs: pointer to the i2c message structure + * @num: the number of messages to transfer + * + * Return: number of msgs processed on success, negative error otherwise + */ +static int cdns_i2c_master_xfer_atomic(struct i2c_adapter *adap, struct i2= c_msg *msgs, + int num) +{ + int ret; + struct cdns_i2c *id =3D adap->algo_data; + + ret =3D cdns_i2c_runtime_resume(id->dev); + if (ret) + return ret; + + if (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT) { + dev_warn(id->adap.dev.parent, + "Atomic xfer not supported for version 1.0\n"); + return 0; + } + + id->atomic =3D true; + ret =3D cdns_i2c_master_common_xfer(adap, msgs, num); + if (!ret) + ret =3D num; + + id->atomic =3D false; + cdns_i2c_runtime_suspend(id->dev); + + return ret; +} + /** * cdns_i2c_func - Returns the supported features of the I2C driver * @adap: pointer to the i2c adapter structure @@ -1056,6 +1232,7 @@ static int cdns_unreg_slave(struct i2c_client *slave) =20 static const struct i2c_algorithm cdns_i2c_algo =3D { .master_xfer =3D cdns_i2c_master_xfer, + .master_xfer_atomic =3D cdns_i2c_master_xfer_atomic, .functionality =3D cdns_i2c_func, #if IS_ENABLED(CONFIG_I2C_SLAVE) .reg_slave =3D cdns_reg_slave, --=20 2.25.1