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charset="utf-8" Add compatible string for the supported eDP PHY on sa8775p platform. Signed-off-by: Soutrik Mukhopadhyay --- Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Docu= mentation/devicetree/bindings/phy/qcom,edp-phy.yaml index 4e15d90d08b0..293fb6a9b1c3 100644 --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml @@ -17,6 +17,7 @@ description: properties: compatible: enum: + - qcom,sa8775p-edp-phy - qcom,sc7280-edp-phy - qcom,sc8180x-edp-phy - qcom,sc8280xp-dp-phy --=20 2.17.1 From nobody Sat Nov 30 06:45:29 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59F17153820; Wed, 11 Sep 2024 10:08:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; 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charset="utf-8" In order to support different HW versions, introduce aux_cfg array to move v4 specific aux configuration settings. Signed-off-by: Soutrik Mukhopadhyay --- drivers/phy/qualcomm/phy-qcom-edp.c | 34 +++++++++++++++++------------ 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index da2b32fb5b45..0f860a807d1b 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -90,6 +90,7 @@ struct phy_ver_ops { =20 struct qcom_edp_phy_cfg { bool is_edp; + u8 *aux_cfg; const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg; const struct phy_ver_ops *ver_ops; }; @@ -186,11 +187,14 @@ static const struct qcom_edp_swing_pre_emph_cfg edp_p= hy_swing_pre_emph_cfg =3D { .pre_emphasis_hbr3_hbr2 =3D &edp_pre_emp_hbr2_hbr3, }; =20 +static u8 edp_phy_aux_cfg_v4[10] =3D { + 0x00, 0x13, 0x24, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03 +}; + static int qcom_edp_phy_init(struct phy *phy) { struct qcom_edp *edp =3D phy_get_drvdata(phy); int ret; - u8 cfg8; =20 ret =3D regulator_bulk_enable(ARRAY_SIZE(edp->supplies), edp->supplies); if (ret) @@ -222,22 +226,20 @@ static int qcom_edp_phy_init(struct phy *phy) * even needed. */ if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp) - cfg8 =3D 0xb7; - else - cfg8 =3D 0x37; + edp->cfg->aux_cfg[8] =3D 0xb7; =20 writel(0xfc, edp->edp + DP_PHY_MODE); =20 - writel(0x00, edp->edp + DP_PHY_AUX_CFG0); - writel(0x13, edp->edp + DP_PHY_AUX_CFG1); - writel(0x24, edp->edp + DP_PHY_AUX_CFG2); - writel(0x00, edp->edp + DP_PHY_AUX_CFG3); - writel(0x0a, edp->edp + DP_PHY_AUX_CFG4); - writel(0x26, edp->edp + DP_PHY_AUX_CFG5); - writel(0x0a, edp->edp + DP_PHY_AUX_CFG6); - writel(0x03, edp->edp + DP_PHY_AUX_CFG7); - writel(cfg8, edp->edp + DP_PHY_AUX_CFG8); - writel(0x03, edp->edp + DP_PHY_AUX_CFG9); + writel(edp->cfg->aux_cfg[0], edp->edp + DP_PHY_AUX_CFG0); + writel(edp->cfg->aux_cfg[1], edp->edp + DP_PHY_AUX_CFG1); + writel(edp->cfg->aux_cfg[2], edp->edp + DP_PHY_AUX_CFG2); + writel(edp->cfg->aux_cfg[3], edp->edp + DP_PHY_AUX_CFG3); + writel(edp->cfg->aux_cfg[4], edp->edp + DP_PHY_AUX_CFG4); + writel(edp->cfg->aux_cfg[5], edp->edp + DP_PHY_AUX_CFG5); + writel(edp->cfg->aux_cfg[6], edp->edp + DP_PHY_AUX_CFG6); + writel(edp->cfg->aux_cfg[7], edp->edp + DP_PHY_AUX_CFG7); + writel(edp->cfg->aux_cfg[8], edp->edp + DP_PHY_AUX_CFG8); + writel(edp->cfg->aux_cfg[9], edp->edp + DP_PHY_AUX_CFG9); =20 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | @@ -519,16 +521,19 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v4 = =3D { }; =20 static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg =3D { + .aux_cfg =3D edp_phy_aux_cfg_v4, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg =3D { + .aux_cfg =3D edp_phy_aux_cfg_v4, .swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg =3D { .is_edp =3D true, + .aux_cfg =3D edp_phy_aux_cfg_v4, .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v4, }; 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Wed, 11 Sep 2024 10:08:21 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 41h168s1sy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Wed, 11 Sep 2024 10:08:21 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 48BA8Kt6019409; Wed, 11 Sep 2024 10:08:20 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-mukhopad-hyd.qualcomm.com [10.147.244.250]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 48BA8Ks8019402; Wed, 11 Sep 2024 10:08:20 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 3978529) id 96D625000AF; Wed, 11 Sep 2024 15:38:18 +0530 (+0530) From: Soutrik Mukhopadhyay To: vkoul@kernel.org, kishon@kernel.org, konradybcio@kernel.org, andersson@kernel.org, simona@ffwll.ch, dmitry.baryshkov@linaro.org, abel.vesa@linaro.org, robdclark@gmail.com, quic_abhinavk@quicinc.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, daniel@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_khsieh@quicinc.com, konrad.dybcio@linaro.org, quic_parellan@quicinc.com, quic_bjorande@quicinc.com Cc: Soutrik Mukhopadhyay , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, quic_riteshk@quicinc.com, quic_vproddut@quicinc.com Subject: [PATCH 3/5] phy: qcom: edp: Add support for eDP PHY on SA8775P Date: Wed, 11 Sep 2024 15:38:11 +0530 Message-Id: <20240911100813.338-4-quic_mukhopad@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240911100813.338-1-quic_mukhopad@quicinc.com> References: <20240911100813.338-1-quic_mukhopad@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ETaJKGyh4Eye1kQSYJV9UiBzciYNV8jp X-Proofpoint-GUID: ETaJKGyh4Eye1kQSYJV9UiBzciYNV8jp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 spamscore=0 phishscore=0 impostorscore=0 suspectscore=0 mlxscore=0 malwarescore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409110075 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for eDP PHY v5 found on the Qualcomm SA8775P platform. Signed-off-by: Soutrik Mukhopadhyay --- drivers/phy/qualcomm/phy-qcom-edp.c | 47 +++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index 0f860a807d1b..34a47cd2919d 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -191,6 +191,45 @@ static u8 edp_phy_aux_cfg_v4[10] =3D { 0x00, 0x13, 0x24, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03 }; =20 +static const u8 edp_swing_hbr_rbr_v5[4][4] =3D { + { 0x07, 0x0f, 0x16, 0x1f }, + { 0x0d, 0x16, 0x1e, 0xff }, + { 0x11, 0x1b, 0xff, 0xff }, + { 0x16, 0xff, 0xff, 0xff } +}; + +static const u8 edp_pre_emp_hbr_rbr_v5[4][4] =3D { + { 0x05, 0x11, 0x17, 0x1d }, + { 0x05, 0x11, 0x18, 0xff }, + { 0x06, 0x11, 0xff, 0xff }, + { 0x00, 0xff, 0xff, 0xff } +}; + +static const u8 edp_swing_hbr2_hbr3_v5[4][4] =3D { + { 0x0b, 0x11, 0x17, 0x1c }, + { 0x10, 0x19, 0x1f, 0xff }, + { 0x19, 0x1f, 0xff, 0xff }, + { 0x1f, 0xff, 0xff, 0xff } +}; + +static const u8 edp_pre_emp_hbr2_hbr3_v5[4][4] =3D { + { 0x0c, 0x15, 0x19, 0x1e }, + { 0x0b, 0x15, 0x19, 0xff }, + { 0x0e, 0x14, 0xff, 0xff }, + { 0x0d, 0xff, 0xff, 0xff } +}; + +static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg= _v5 =3D { + .swing_hbr_rbr =3D &edp_swing_hbr_rbr_v5, + .swing_hbr3_hbr2 =3D &edp_swing_hbr2_hbr3_v5, + .pre_emphasis_hbr_rbr =3D &edp_pre_emp_hbr_rbr_v5, + .pre_emphasis_hbr3_hbr2 =3D &edp_pre_emp_hbr2_hbr3_v5, +}; + +static u8 edp_phy_aux_cfg_v5[10] =3D { + 0x00, 0x13, 0xa4, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03 +}; + static int qcom_edp_phy_init(struct phy *phy) { struct qcom_edp *edp =3D phy_get_drvdata(phy); @@ -520,6 +559,13 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v4 = =3D { .com_configure_ssc =3D qcom_edp_com_configure_ssc_v4, }; =20 +static const struct qcom_edp_phy_cfg sa8775p_dp_phy_cfg =3D { + .is_edp =3D false, + .aux_cfg =3D edp_phy_aux_cfg_v5, + .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg_v5, + .ver_ops =3D &qcom_edp_phy_ops_v4, +}; + static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, .ver_ops =3D &qcom_edp_phy_ops_v4, @@ -1114,6 +1160,7 @@ static int qcom_edp_phy_probe(struct platform_device = *pdev) } =20 static const struct of_device_id qcom_edp_phy_match_table[] =3D { + { .compatible =3D "qcom,sa8775p-edp-phy", .data =3D &sa8775p_dp_phy_cfg, = }, { .compatible =3D "qcom,sc7280-edp-phy", .data =3D &sc7280_dp_phy_cfg, }, { .compatible =3D "qcom,sc8180x-edp-phy", .data =3D &sc7280_dp_phy_cfg, }, { .compatible =3D "qcom,sc8280xp-dp-phy", .data =3D &sc8280xp_dp_phy_cfg,= }, --=20 2.17.1 From nobody Sat Nov 30 06:45:29 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8C021714C0; Wed, 11 Sep 2024 10:08:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; 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charset="utf-8" Add compatible string for the DisplayPort controller found on the Qualcomm SA8775P platform. Signed-off-by: Soutrik Mukhopadhyay --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 97993feda193..a212f335d5ff 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -17,6 +17,7 @@ properties: compatible: oneOf: - enum: + - qcom,sa8775p-dp - qcom,sc7180-dp - qcom,sc7280-dp - qcom,sc7280-edp --=20 2.17.1 From nobody Sat Nov 30 06:45:29 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59FB11714C0; Wed, 11 Sep 2024 10:08:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; 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charset="utf-8" The Qualcomm SA8775P platform comes with a DisplayPort controller with a different base offset than the previous SoCs, add support for this in the DisplayPort driver. Signed-off-by: Soutrik Mukhopadhyay --- drivers/gpu/drm/msm/dp/dp_display.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index e1228fb093ee..e4954fd99eb0 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -118,6 +118,12 @@ struct msm_dp_desc { bool wide_bus_supported; }; =20 +static const struct msm_dp_desc sa8775p_dp_descs[] =3D { + { .io_start =3D 0xaf54000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_support= ed =3D true }, + { .io_start =3D 0xaf5c000, .id =3D MSM_DP_CONTROLLER_1, .wide_bus_support= ed =3D true }, + {} +}; + static const struct msm_dp_desc sc7180_dp_descs[] =3D { { .io_start =3D 0x0ae90000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true }, {} @@ -162,6 +168,7 @@ static const struct msm_dp_desc x1e80100_dp_descs[] =3D= { }; =20 static const struct of_device_id dp_dt_match[] =3D { + { .compatible =3D "qcom,sa8775p-dp", .data =3D &sa8775p_dp_descs }, { .compatible =3D "qcom,sc7180-dp", .data =3D &sc7180_dp_descs }, { .compatible =3D "qcom,sc7280-dp", .data =3D &sc7280_dp_descs }, { .compatible =3D "qcom,sc7280-edp", .data =3D &sc7280_dp_descs }, --=20 2.17.1