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[175.159.121.22]) by smtp.googlemail.com with ESMTPSA id d2e1a72fcca58-71909095177sm2530125b3a.112.2024.09.11.01.48.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 01:48:26 -0700 (PDT) From: Nick Chan To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J . Wysocki" , Viresh Kumar , Linus Walleij , Wim Van Sebroeck , Guenter Roeck , Catalin Marinas , Will Deacon , Lorenzo Pieralisi , Mark Kettenis , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org Cc: Konrad Dybcio , Ivaylo Ivanov , Nick Chan Subject: [PATCH 20/22] arm64: dts: apple: Add A11 devices Date: Wed, 11 Sep 2024 16:41:10 +0800 Message-ID: <20240911084353.28888-22-towinchenmi@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240911084353.28888-2-towinchenmi@gmail.com> References: <20240911084353.28888-2-towinchenmi@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Konrad Dybcio Add DTS files for the A11 SoC and the following devices based on it: - iPhone 8 - iPhone 8 Plus - iPhone X On A11, Apple has introduced independent performance and efficiency core clusters, so indicate it in the device tree as well. Signed-off-by: Konrad Dybcio [Nick: SMP and m1n1 support, disabled SMC pinctrl] Co-developed-by: Nick Chan Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/Makefile | 6 + arch/arm64/boot/dts/apple/t8015-8.dtsi | 12 + arch/arm64/boot/dts/apple/t8015-8plus.dtsi | 9 + arch/arm64/boot/dts/apple/t8015-d20.dts | 14 ++ arch/arm64/boot/dts/apple/t8015-d201.dts | 14 ++ arch/arm64/boot/dts/apple/t8015-d21.dts | 14 ++ arch/arm64/boot/dts/apple/t8015-d211.dts | 14 ++ arch/arm64/boot/dts/apple/t8015-d22.dts | 14 ++ arch/arm64/boot/dts/apple/t8015-d221.dts | 14 ++ arch/arm64/boot/dts/apple/t8015-x.dtsi | 15 ++ arch/arm64/boot/dts/apple/t8015.dtsi | 269 +++++++++++++++++++++ 11 files changed, 395 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t8015-8.dtsi create mode 100644 arch/arm64/boot/dts/apple/t8015-8plus.dtsi create mode 100644 arch/arm64/boot/dts/apple/t8015-d20.dts create mode 100644 arch/arm64/boot/dts/apple/t8015-d201.dts create mode 100644 arch/arm64/boot/dts/apple/t8015-d21.dts create mode 100644 arch/arm64/boot/dts/apple/t8015-d211.dts create mode 100644 arch/arm64/boot/dts/apple/t8015-d22.dts create mode 100644 arch/arm64/boot/dts/apple/t8015-d221.dts create mode 100644 arch/arm64/boot/dts/apple/t8015-x.dtsi create mode 100644 arch/arm64/boot/dts/apple/t8015.dtsi diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple= /Makefile index be66624aa6e0..e125c0d6b479 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -45,6 +45,12 @@ dtb-$(CONFIG_ARCH_APPLE) +=3D t8011-j120.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t8011-j121.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t8011-j207.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t8011-j208.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8015-d201.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8015-d20.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8015-d211.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8015-d21.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8015-d221.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8015-d22.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t8103-j274.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t8103-j293.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t8103-j313.dtb diff --git a/arch/arm64/boot/dts/apple/t8015-8.dtsi b/arch/arm64/boot/dts/a= pple/t8015-8.dtsi new file mode 100644 index 000000000000..b3cd96d343ed --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8015-8.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone 8 common device tree + * + * Copyright (c) 2022, Konrad Dybcio + */ + +#include "t8015.dtsi" + +&serial0 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8015-8plus.dtsi b/arch/arm64/boot/d= ts/apple/t8015-8plus.dtsi new file mode 100644 index 000000000000..ea291a95f028 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8015-8plus.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone 8 Plus common device tree + * + * Copyright (c) 2022, Konrad Dybcio + */ + +/* The 8 Plus has minor differences like 1 more camera, 1 GiB of RAM more = and a bigger display. */ +#include "t8015-8.dtsi" diff --git a/arch/arm64/boot/dts/apple/t8015-d20.dts b/arch/arm64/boot/dts/= apple/t8015-d20.dts new file mode 100644 index 000000000000..35d79e2ceebc --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8015-d20.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone 8 (Global), D20 iPhone10,1 (A1863/A1906/A1907) + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include "t8015-8.dtsi" + +/ { + compatible =3D "apple,d20", "apple,t8015", "apple,arm-platform"; + model =3D "Apple iPhone 8 (Global)"; +}; diff --git a/arch/arm64/boot/dts/apple/t8015-d201.dts b/arch/arm64/boot/dts= /apple/t8015-d201.dts new file mode 100644 index 000000000000..31e0947fee70 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8015-d201.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone 8 (GSM), D20 iPhone10,4 (A1905) + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include "t8015-8.dtsi" + +/ { + compatible =3D "apple,d201", "apple,t8015", "apple,arm-platform"; + model =3D "Apple iPhone 8 (GSM)"; +}; diff --git a/arch/arm64/boot/dts/apple/t8015-d21.dts b/arch/arm64/boot/dts/= apple/t8015-d21.dts new file mode 100644 index 000000000000..a902ba7f1133 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8015-d21.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone 8 Plus (Global), D21 iPhone10,2 (A1864/A1897/A1898) + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include "t8015-8plus.dtsi" + +/ { + compatible =3D "apple,d21", "apple,t8015", "apple,arm-platform"; + model =3D "Apple iPhone 8 Plus (Global)"; +}; diff --git a/arch/arm64/boot/dts/apple/t8015-d211.dts b/arch/arm64/boot/dts= /apple/t8015-d211.dts new file mode 100644 index 000000000000..3b3f886c0c09 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8015-d211.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone 8 Plus (GSM), D211 iPhone10,5 (A1899) + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include "t8015-8plus.dtsi" + +/ { + compatible =3D "apple,d211", "apple,t8015", "apple,arm-platform"; + model =3D "Apple iPhone 8 Plus (GSM)"; +}; diff --git a/arch/arm64/boot/dts/apple/t8015-d22.dts b/arch/arm64/boot/dts/= apple/t8015-d22.dts new file mode 100644 index 000000000000..5a7a6092c2d0 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8015-d22.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone X (Global), D22, iPhone10,3 (A1865) + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include "t8015-x.dtsi" + +/ { + compatible =3D "apple,d22", "apple,t8015", "apple,arm-platform"; + model =3D "Apple iPhone X (Global)"; +}; diff --git a/arch/arm64/boot/dts/apple/t8015-d221.dts b/arch/arm64/boot/dts= /apple/t8015-d221.dts new file mode 100644 index 000000000000..dd920c945bd6 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8015-d221.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone X (GSM), D221, iPhone10,6 (A1901) + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include "t8015-x.dtsi" + +/ { + compatible =3D "apple,d221", "apple,t8015", "apple,arm-platform"; + model =3D "Apple iPhone X (GSM)"; +}; diff --git a/arch/arm64/boot/dts/apple/t8015-x.dtsi b/arch/arm64/boot/dts/a= pple/t8015-x.dtsi new file mode 100644 index 000000000000..655cd89848a3 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8015-x.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone X common device tree + * + * Copyright (c) 2022, Konrad Dybcio + */ + +#include "t8015.dtsi" + +/ { +}; + +&serial0 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8015.dtsi b/arch/arm64/boot/dts/app= le/t8015.dtsi new file mode 100644 index 000000000000..aa0e948c9ed8 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8015.dtsi @@ -0,0 +1,269 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T8015 "A11" SoC + * + * Copyright (c) 2022, Konrad Dybcio + * Based on Asahi Linux's M1 (t8103.dtsi) and Corellium's A10 efforts. + */ + +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&aic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + serial0 =3D &serial0; + }; + + chosen { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + stdout-path =3D "serial0"; + + framebuffer0: framebuffer@0 { + compatible =3D "apple,simple-framebuffer", "simple-framebuffer"; + reg =3D <0 0 0 0>; /* To be filled by loader */ + /* Format properties will be added by loader */ + status =3D "disabled"; + }; + }; + + clkref: clock-ref { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + clock-output-names =3D "clkref"; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu_e0>; + }; + core1 { + cpu =3D <&cpu_e1>; + }; + core2 { + cpu =3D <&cpu_e2>; + }; + core3 { + cpu =3D <&cpu_e3>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu_p0>; + }; + core1 { + cpu =3D <&cpu_p1>; + }; + }; + }; + + cpu_e0: cpu@0 { + compatible =3D "apple,mistral"; + reg =3D <0x0 0x0>; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + enable-method =3D "spin-table"; + device_type =3D "cpu"; + }; + + cpu_e1: cpu@1 { + compatible =3D "apple,mistral"; + reg =3D <0x0 0x1>; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + enable-method =3D "spin-table"; + device_type =3D "cpu"; + }; + + cpu_e2: cpu@2 { + compatible =3D "apple,mistral"; + reg =3D <0x0 0x2>; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + enable-method =3D "spin-table"; + device_type =3D "cpu"; + }; + + cpu_e3: cpu@3 { + compatible =3D "apple,mistral"; + reg =3D <0x0 0x3>; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + enable-method =3D "spin-table"; + device_type =3D "cpu"; + }; + + cpu_p0: cpu@10004 { + compatible =3D "apple,monsoon"; + reg =3D <0x0 0x10004>; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + enable-method =3D "spin-table"; + device_type =3D "cpu"; + }; + + cpu_p1: cpu@10005 { + compatible =3D "apple,monsoon"; + reg =3D <0x0 0x10005>; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + enable-method =3D "spin-table"; + device_type =3D "cpu"; + }; + }; + + memory@800000000 { + device_type =3D "memory"; + /* To be filled in by the bootloader (based on XNU BootArgs). */ + reg =3D <0x8 0 0 0>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* + * The bootloader reserves a region for the (varying-address, depending + * on what FW your device runs AND model) framebuffer under this node. + */ + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + nonposted-mmio; + ranges; + + serial0: serial@22e600000 { + compatible =3D "apple,s5l-uart"; + reg =3D <0x2 0x2e600000 0x0 0x4000>; + reg-io-width =3D <4>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + /* Use the bootloader-enabled clocks for now. */ + clocks =3D <&clkref>, <&clkref>; + clock-names =3D "uart", "clk_uart_baud0"; + status =3D "disabled"; + }; + + aic: interrupt-controller@232100000 { + compatible =3D "apple,t8015-aic", "apple,aic"; + reg =3D <0x2 0x32100000 0x0 0x8000>; + #interrupt-cells =3D <3>; + interrupt-controller; + }; + + pinctrl_ap: pinctrl@233100000 { + compatible =3D "apple,t8015-pinctrl", "apple,pinctrl"; + reg =3D <0x2 0x33100000 0x0 0x1000>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl_ap 0 0 223>; + apple,npins =3D <223>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + , + , + , + ; + }; + + pinctrl_aop: pinctrl@2340f0000 { + compatible =3D "apple,t8015-pinctrl", "apple,pinctrl"; + reg =3D <0x2 0x340f0000 0x0 0x4000>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl_aop 0 0 49>; + apple,npins =3D <49>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + , + , + , + ; + }; + + pinctrl_nub: pinctrl@2351f0000 { + compatible =3D "apple,t8015-pinctrl", "apple,pinctrl"; + reg =3D <0x2 0x351f0000 0x0 0x4000>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl_nub 0 0 8>; + apple,npins =3D <8>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + ; + }; + + wdt: watchdog@2352b0000 { + compatible =3D "apple,t8015-wdt", "apple,wdt"; + reg =3D <0x2 0x352b0000 0x0 0x4000>; + clocks =3D <&clkref>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + }; + + pinctrl_smc: pinctrl@236024000 { + compatible =3D "apple,t8015-pinctrl", "apple,pinctrl"; + reg =3D <0x2 0x36024000 0x0 0x4000>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl_smc 0 0 6>; + apple,npins =3D <6>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + , + , + , + ; + /* + * SMC is not yet supported and accessing this pinctrl while SMC is + * off results in a hang. (To be enabled by SMC-aware loader) + */ + status =3D "disabled"; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&aic>; + interrupt-names =3D "phys", "virt"; + /* Note that A11 doesn't actually have a hypervisor (EL2 is not implemen= ted). */ + interrupts =3D , + ; + }; +}; --=20 2.46.0