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[175.159.121.22]) by smtp.googlemail.com with ESMTPSA id d2e1a72fcca58-71909095177sm2530125b3a.112.2024.09.11.01.48.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 01:48:07 -0700 (PDT) From: Nick Chan To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J . Wysocki" , Viresh Kumar , Linus Walleij , Wim Van Sebroeck , Guenter Roeck , Catalin Marinas , Will Deacon , Lorenzo Pieralisi , Mark Kettenis , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org Cc: Konrad Dybcio , Ivaylo Ivanov , Nick Chan Subject: [PATCH 16/22] arm64: dts: apple: Add A9 devices Date: Wed, 11 Sep 2024 16:41:06 +0800 Message-ID: <20240911084353.28888-18-towinchenmi@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240911084353.28888-2-towinchenmi@gmail.com> References: <20240911084353.28888-2-towinchenmi@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Konrad Dybcio Add DTS files for the A9 SoC and the following devices based on it: - iPhone 6S - iPhone 6S Plus - iPhone SE (2016) - iPad 5 Signed-off-by: Konrad Dybcio [Nick: SMP, m1n1 and AOP pinctrl support] Co-developed-by: Nick Chan Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/Makefile | 10 ++ arch/arm64/boot/dts/apple/s8000-j71s.dts | 15 ++ arch/arm64/boot/dts/apple/s8000-j72s.dts | 15 ++ arch/arm64/boot/dts/apple/s8000-n66.dts | 15 ++ arch/arm64/boot/dts/apple/s8000-n69u.dts | 15 ++ arch/arm64/boot/dts/apple/s8000-n71.dts | 15 ++ arch/arm64/boot/dts/apple/s8000.dtsi | 179 +++++++++++++++++++++ arch/arm64/boot/dts/apple/s8003-j71t.dts | 15 ++ arch/arm64/boot/dts/apple/s8003-j72t.dts | 15 ++ arch/arm64/boot/dts/apple/s8003-n66m.dts | 15 ++ arch/arm64/boot/dts/apple/s8003-n69.dts | 15 ++ arch/arm64/boot/dts/apple/s8003-n71m.dts | 15 ++ arch/arm64/boot/dts/apple/s8003.dtsi | 19 +++ arch/arm64/boot/dts/apple/s800x-6s.dtsi | 50 ++++++ arch/arm64/boot/dts/apple/s800x-ipad5.dtsi | 44 +++++ arch/arm64/boot/dts/apple/s800x-se.dtsi | 50 ++++++ 16 files changed, 502 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/s8000-j71s.dts create mode 100644 arch/arm64/boot/dts/apple/s8000-j72s.dts create mode 100644 arch/arm64/boot/dts/apple/s8000-n66.dts create mode 100644 arch/arm64/boot/dts/apple/s8000-n69u.dts create mode 100644 arch/arm64/boot/dts/apple/s8000-n71.dts create mode 100644 arch/arm64/boot/dts/apple/s8000.dtsi create mode 100644 arch/arm64/boot/dts/apple/s8003-j71t.dts create mode 100644 arch/arm64/boot/dts/apple/s8003-j72t.dts create mode 100644 arch/arm64/boot/dts/apple/s8003-n66m.dts create mode 100644 arch/arm64/boot/dts/apple/s8003-n69.dts create mode 100644 arch/arm64/boot/dts/apple/s8003-n71m.dts create mode 100644 arch/arm64/boot/dts/apple/s8003.dtsi create mode 100644 arch/arm64/boot/dts/apple/s800x-6s.dtsi create mode 100644 arch/arm64/boot/dts/apple/s800x-ipad5.dtsi create mode 100644 arch/arm64/boot/dts/apple/s800x-se.dtsi diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple= /Makefile index adda522ea490..cbb7e409b7e3 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -18,6 +18,16 @@ dtb-$(CONFIG_ARCH_APPLE) +=3D t7000-n56.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t7000-n61.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t7001-j81.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t7001-j82.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D s8000-j71s.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D s8000-j72s.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D s8000-n66.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D s8000-n69u.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D s8000-n71.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D s8003-j71t.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D s8003-j72t.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D s8003-n66m.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D s8003-n69.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D s8003-n71m.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t8103-j274.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t8103-j293.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t8103-j313.dtb diff --git a/arch/arm64/boot/dts/apple/s8000-j71s.dts b/arch/arm64/boot/dts= /apple/s8000-j71s.dts new file mode 100644 index 000000000000..b5a2dfa1121e --- /dev/null +++ b/arch/arm64/boot/dts/apple/s8000-j71s.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPad 5 (Wi-Fi) (Samsung), J71s, iPad6,11 (A1822) + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include "s8000.dtsi" +#include "s800x-ipad5.dtsi" + +/ { + compatible =3D "apple,j71s", "apple,s8000", "apple,arm-platform"; + model =3D "Apple iPad 5 (Wi-Fi) (Samsung)"; +}; diff --git a/arch/arm64/boot/dts/apple/s8000-j72s.dts b/arch/arm64/boot/dts= /apple/s8000-j72s.dts new file mode 100644 index 000000000000..8f3dea5adb09 --- /dev/null +++ b/arch/arm64/boot/dts/apple/s8000-j72s.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPad 5 (Cellular) (Samsung), J72s, iPad6,12 (A1823) + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include "s8000.dtsi" +#include "s800x-ipad5.dtsi" + +/ { + compatible =3D "apple,j72s", "apple,s8000", "apple,arm-platform"; + model =3D "Apple iPad 5 (Cellular) (Samsung)"; +}; diff --git a/arch/arm64/boot/dts/apple/s8000-n66.dts b/arch/arm64/boot/dts/= apple/s8000-n66.dts new file mode 100644 index 000000000000..834bf702b009 --- /dev/null +++ b/arch/arm64/boot/dts/apple/s8000-n66.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone 6S Plus (Samsung), N66, iPhone8,2 (A1634/A1687/A1690/A1699) + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include "s8000.dtsi" +#include "s800x-6s.dtsi" + +/ { + compatible =3D "apple,n66", "apple,s8000", "apple,arm-platform"; + model =3D "Apple iPhone 6S Plus (Samsung)"; +}; diff --git a/arch/arm64/boot/dts/apple/s8000-n69u.dts b/arch/arm64/boot/dts= /apple/s8000-n69u.dts new file mode 100644 index 000000000000..e63bc2e7f7c1 --- /dev/null +++ b/arch/arm64/boot/dts/apple/s8000-n69u.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone SE (Samsung), N69u, iPhone8,4 (A1662/A1723/A1724) + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include "s8000.dtsi" +#include "s800x-se.dtsi" + +/ { + compatible =3D "apple,n69u", "apple,s8000", "apple,arm-platform"; + model =3D "Apple iPhone SE (Samsung)"; +}; diff --git a/arch/arm64/boot/dts/apple/s8000-n71.dts b/arch/arm64/boot/dts/= apple/s8000-n71.dts new file mode 100644 index 000000000000..784d29c55374 --- /dev/null +++ b/arch/arm64/boot/dts/apple/s8000-n71.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone 6S (Samsung), N71, iPhone8,1 (A1633/A1688/A1691/A1700) + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include "s8000.dtsi" +#include "s800x-6s.dtsi" + +/ { + compatible =3D "apple,n71", "apple,s8000", "apple,arm-platform"; + model =3D "Apple iPhone 6S (Samsung)"; +}; diff --git a/arch/arm64/boot/dts/apple/s8000.dtsi b/arch/arm64/boot/dts/app= le/s8000.dtsi new file mode 100644 index 000000000000..19629ae8af2b --- /dev/null +++ b/arch/arm64/boot/dts/apple/s8000.dtsi @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple S8000 "A9 (Samsung)" SoC + * + * Copyright (c) 2022, Konrad Dybcio + * Based on Asahi Linux's M1 (t8103.dtsi) and Corellium's A10 efforts. + */ + +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&aic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + serial0 =3D &serial0; + }; + + chosen { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + stdout-path =3D "serial0"; + + framebuffer0: framebuffer@0 { + compatible =3D "apple,simple-framebuffer", "simple-framebuffer"; + reg =3D <0 0 0 0>; /* To be filled by loader */ + /* Format properties will be added by loader */ + status =3D "disabled"; + }; + }; + + clkref: clock-ref { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + clock-output-names =3D "clkref"; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "apple,twister"; + reg =3D <0x0 0x0>; + cpu-release-addr =3D <0 0>; /* To be filled in by loader */ + enable-method =3D "spin-table"; + device_type =3D "cpu"; + }; + + cpu1: cpu@1 { + compatible =3D "apple,twister"; + reg =3D <0x0 0x1>; + cpu-release-addr =3D <0 0>; /* To be filled in by loader */ + enable-method =3D "spin-table"; + device_type =3D "cpu"; + }; + }; + + memory@800000000 { + device_type =3D "memory"; + /* To be filled in by the bootloader (based on XNU BootArgs). */ + reg =3D <0x8 0 0 0>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* + * The bootloader reserves a region for the (varying-address, depending + * on what FW your device runs AND model) framebuffer under this node. + */ + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + nonposted-mmio; + ranges; + + serial0: serial@20a0c0000 { + compatible =3D "apple,s5l-uart"; + reg =3D <0x2 0x0a0c0000 0x0 0x4000>; + reg-io-width =3D <4>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + /* Use the bootloader-enabled clocks for now. */ + clocks =3D <&clkref>, <&clkref>; + clock-names =3D "uart", "clk_uart_baud0"; + status =3D "disabled"; + }; + + aic: interrupt-controller@20e100000 { + compatible =3D "apple,s8000-aic", "apple,aic"; + reg =3D <0x2 0x0e100000 0x0 0x100000>; + #interrupt-cells =3D <3>; + interrupt-controller; + }; + + pinctrl_ap: pinctrl@20f100000 { + compatible =3D "apple,s8000-pinctrl", "apple,pinctrl"; + reg =3D <0x2 0x0f100000 0x0 0x100000>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl_ap 0 0 208>; + apple,npins =3D <208>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + , + , + , + ; + }; + + pinctrl_aop: pinctrl@2100f0000 { + compatible =3D "apple,s8000-pinctrl", "apple,pinctrl"; + reg =3D <0x2 0x100f0000 0x0 0x100000>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl_aop 0 0 42>; + apple,npins =3D <42>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + , + , + , + ; + }; + + wdt: watchdog@2102b0000 { + compatible =3D "apple,s8000-wdt", "apple,wdt"; + reg =3D <0x2 0x102b0000 0x0 0x4000>; + clocks =3D <&clkref>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&aic>; + interrupt-names =3D "phys", "virt"; + /* Note that A9 doesn't actually have a hypervisor (EL2 is not implement= ed). */ + interrupts =3D , + ; + }; +}; + +/* + * The A9 was made by two separate fabs on two different process + * nodes: Samsung made the S8000 (APL0898) on 14nm and TSMC made + * the S8003 (APL1022) on 16nm. While they are seemingly the same, + * they do have distinct part numbers and devices using them have + * distinct model names. There are currently no known differences + * between these as far as Linux is concerned, but let's keep things + * structured properly to make it easier to alter the behaviour of + * one of the chips if need be. + */ diff --git a/arch/arm64/boot/dts/apple/s8003-j71t.dts b/arch/arm64/boot/dts= /apple/s8003-j71t.dts new file mode 100644 index 000000000000..0d906ae80b07 --- /dev/null +++ b/arch/arm64/boot/dts/apple/s8003-j71t.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPad 5 (Wi-Fi) (TSMC), J71t, iPad6,11 (A1822) + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include "s8003.dtsi" +#include "s800x-ipad5.dtsi" + +/ { + compatible =3D "apple,j71t", "apple,s8003", "apple,arm-platform"; + model =3D "Apple iPad 5 (Wi-Fi) (TSMC)"; +}; diff --git a/arch/arm64/boot/dts/apple/s8003-j72t.dts b/arch/arm64/boot/dts= /apple/s8003-j72t.dts new file mode 100644 index 000000000000..0cd7d88e9dfb --- /dev/null +++ b/arch/arm64/boot/dts/apple/s8003-j72t.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPad 5 (Cellular) (TSMC), J72t, iPad6,12 (A1823) + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include "s8003.dtsi" +#include "s800x-ipad5.dtsi" + +/ { + compatible =3D "apple,j72t", "apple,s8003", "apple,arm-platform"; + model =3D "Apple iPad 5 (Cellular) (TSMC)"; +}; diff --git a/arch/arm64/boot/dts/apple/s8003-n66m.dts b/arch/arm64/boot/dts= /apple/s8003-n66m.dts new file mode 100644 index 000000000000..99eee8531da3 --- /dev/null +++ b/arch/arm64/boot/dts/apple/s8003-n66m.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone 6S Plus (TSMC), N66m, iPhone8,2 (A1634/A1687/A1690/A1699) + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include "s8003.dtsi" +#include "s800x-6s.dtsi" + +/ { + compatible =3D "apple,n66m", "apple,s8003", "apple,arm-platform"; + model =3D "Apple iPhone 6S Plus (TSMC)"; +}; diff --git a/arch/arm64/boot/dts/apple/s8003-n69.dts b/arch/arm64/boot/dts/= apple/s8003-n69.dts new file mode 100644 index 000000000000..8eed879b155e --- /dev/null +++ b/arch/arm64/boot/dts/apple/s8003-n69.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone SE (TSMC), N69, iPhone8,4 (A1662/A1723/A1724) + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include "s8003.dtsi" +#include "s800x-se.dtsi" + +/ { + compatible =3D "apple,n69", "apple,s8003", "apple,arm-platform"; + model =3D "Apple iPhone SE (TSMC)"; +}; diff --git a/arch/arm64/boot/dts/apple/s8003-n71m.dts b/arch/arm64/boot/dts= /apple/s8003-n71m.dts new file mode 100644 index 000000000000..b841fe4433d1 --- /dev/null +++ b/arch/arm64/boot/dts/apple/s8003-n71m.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone 6S (TSMC), N71m, iPhone8,1 (A1633/A1688/A1691/A1700) + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include "s8003.dtsi" +#include "s800x-6s.dtsi" + +/ { + compatible =3D "apple,n71m", "apple,s8003", "apple,arm-platform"; + model =3D "Apple iPhone 6S (TSMC)"; +}; diff --git a/arch/arm64/boot/dts/apple/s8003.dtsi b/arch/arm64/boot/dts/app= le/s8003.dtsi new file mode 100644 index 000000000000..52094a634678 --- /dev/null +++ b/arch/arm64/boot/dts/apple/s8003.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple S8003 "A9 (TSMC)" SoC + * + * Copyright (c) 2022, Konrad Dybcio + */ + +#include "s8000.dtsi" + +/* + * The A9 was made by two separate fabs on two different process + * nodes: Samsung made the S8000 (APL0898) on 14nm and TSMC made + * the S8003 (APL1022) on 16nm. While they are seemingly the same, + * they do have distinct part numbers and devices using them have + * distinct model names. There are currently no known differences + * between these as far as Linux is concerned, but let's keep things + * structured properly to make it easier to alter the behaviour of + * one of the chips if need be. + */ diff --git a/arch/arm64/boot/dts/apple/s800x-6s.dtsi b/arch/arm64/boot/dts/= apple/s800x-6s.dtsi new file mode 100644 index 000000000000..7b217fca8aff --- /dev/null +++ b/arch/arm64/boot/dts/apple/s800x-6s.dtsi @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone 6S / 6S Plus common device tree + * + * Copyright (c) 2022, Konrad Dybcio + */ + +#include + +/ { + gpio-keys { + compatible =3D "gpio-keys"; + + button-home { + label =3D "Home Button"; + gpios =3D <&pinctrl_ap 96 GPIO_ACTIVE_LOW>; + linux,code =3D ; + wakeup-source; + }; + + button-power { + label =3D "Power Button"; + gpios =3D <&pinctrl_ap 97 GPIO_ACTIVE_LOW>; + linux,code =3D ; + wakeup-source; + }; + + button-voldown { + label =3D "Volume Down"; + gpios =3D <&pinctrl_ap 67 GPIO_ACTIVE_LOW>; + linux,code =3D ; + }; + + button-volup { + label =3D "Volume Up"; + gpios =3D <&pinctrl_ap 66 GPIO_ACTIVE_LOW>; + linux,code =3D ; + }; + + switch-mute { + label =3D "Mute Switch"; + gpios =3D <&pinctrl_ap 149 GPIO_ACTIVE_LOW>; + linux,code =3D ; + }; + }; +}; + +&serial0 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/s800x-ipad5.dtsi b/arch/arm64/boot/d= ts/apple/s800x-ipad5.dtsi new file mode 100644 index 000000000000..1a921e9d77c3 --- /dev/null +++ b/arch/arm64/boot/dts/apple/s800x-ipad5.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPad 5 common device tree + * + * Copyright (c) 2022, Konrad Dybcio + */ + +#include + +/ { + gpio-keys { + compatible =3D "gpio-keys"; + + button-home { + label =3D "Home Button"; + gpios =3D <&pinctrl_ap 96 GPIO_ACTIVE_LOW>; + linux,code =3D ; + wakeup-source; + }; + + button-power { + label =3D "Power Button"; + gpios =3D <&pinctrl_ap 97 GPIO_ACTIVE_LOW>; + linux,code =3D ; + wakeup-source; + }; + + button-voldown { + label =3D "Volume Down"; + gpios =3D <&pinctrl_ap 143 GPIO_ACTIVE_LOW>; + linux,code =3D ; + }; + + button-volup { + label =3D "Volume Up"; + gpios =3D <&pinctrl_ap 144 GPIO_ACTIVE_LOW>; + linux,code =3D ; + }; + }; +}; + +&serial0 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/s800x-se.dtsi b/arch/arm64/boot/dts/= apple/s800x-se.dtsi new file mode 100644 index 000000000000..c2b9ad90e88f --- /dev/null +++ b/arch/arm64/boot/dts/apple/s800x-se.dtsi @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone SE common device tree + * + * Copyright (c) 2022, Konrad Dybcio + */ + +#include + +/ { + gpio-keys { + compatible =3D "gpio-keys"; + + button-home { + label =3D "Home Button"; + gpios =3D <&pinctrl_ap 96 GPIO_ACTIVE_LOW>; + linux,code =3D ; + wakeup-source; + }; + + button-power { + label =3D "Power Button"; + gpios =3D <&pinctrl_ap 97 GPIO_ACTIVE_LOW>; + linux,code =3D ; + wakeup-source; + }; + + button-voldown { + label =3D "Volume Down"; + gpios =3D <&pinctrl_ap 67 GPIO_ACTIVE_LOW>; + linux,code =3D ; + }; + + button-volup { + label =3D "Volume Up"; + gpios =3D <&pinctrl_ap 66 GPIO_ACTIVE_LOW>; + linux,code =3D ; + }; + + switch-mute { + label =3D "Mute Switch"; + gpios =3D <&pinctrl_ap 149 GPIO_ACTIVE_LOW>; + linux,code =3D ; + }; + }; +}; + +&serial0 { + status =3D "okay"; +}; --=20 2.46.0