From nobody Sat Nov 30 05:39:17 2024 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D929313B2A8; Wed, 11 Sep 2024 08:16:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726042593; cv=none; b=VN8/jE2iMvxsSBz8TuB/QlOHlBH/CVtLJWrABA7+FuCMOPB5jV5xNoViiqBDkC0dto0MDjxclu2ZDeONLhYoVrhC3hl7AG8JlF1KIHAdY1gonQFWwKlU9EwxAfs9TFMd5RFOnU0CvDHctNzCFk+lcTaq7+NpejiF9Nrg2fg4Oxs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726042593; c=relaxed/simple; bh=yKve1fsm/ychA9JwMB63iUzfIxVBd/T0mvAO7lupqys=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PhAApDCn3VmQZz+uVg+QEBCsJk6IXouG5ikEhF1wblZ2CtsT56xTpa1oG2MXTmK3nRARGIu5UMVRIJzjdoKO8bhdNwrEvbqRpIYBAdkHqyaqzGcDKzJvxxVNbhErZgPd49/Xw7x2bN1+xuyZFXaykeIU5+/Dcwp0q7Wdv4mnckY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=DBOrYGOI; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="DBOrYGOI" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 48B8G87s030651; Wed, 11 Sep 2024 03:16:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1726042568; bh=Bv86eq1d9mNTXWt3fmOkezHCxS58pQ3bRwVyETde2sI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=DBOrYGOIT1OBoLPvV6GabMtzKWXHkLH3LNXf9j40t6Gp473Qr/seLQ982AfpFSPGf eILAJaQmKTWxfcFSYFDXIw5B1lEqkfxDvq9nTXZDixYMT7vYkkEaBhNGUbxYUO53z3 CB8saN6USPlaptIJO+k9TCt3ozdcww7uF8LAbhtg= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 48B8G8P7019730 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 11 Sep 2024 03:16:08 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 11 Sep 2024 03:16:07 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 11 Sep 2024 03:16:07 -0500 Received: from lelv0854.itg.ti.com (lelv0854.itg.ti.com [10.181.64.140]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48B8G740043434; Wed, 11 Sep 2024 03:16:07 -0500 Received: from localhost (danish-tpc.dhcp.ti.com [10.24.69.25]) by lelv0854.itg.ti.com (8.14.7/8.14.7) with ESMTP id 48B8G6ve032122; Wed, 11 Sep 2024 03:16:07 -0500 From: MD Danish Anwar To: , , , , , , , , , , , , , , CC: , , , , Vignesh Raghavendra , Roger Quadros , Subject: [PATCH net-next v6 1/5] net: ti: icss-iep: Move icss_iep structure Date: Wed, 11 Sep 2024 13:45:59 +0530 Message-ID: <20240911081603.2521729-2-danishanwar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240911081603.2521729-1-danishanwar@ti.com> References: <20240911081603.2521729-1-danishanwar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Move icss_iep structure definition and to icss_iep.h file so that the structure members can be used / accessed by all icssg driver files. Reviewed-by: Simon Horman Reviewed-by: Jacob Keller Reviewed-by: Roger Quadros Signed-off-by: MD Danish Anwar --- drivers/net/ethernet/ti/icssg/icss_iep.c | 72 ----------------------- drivers/net/ethernet/ti/icssg/icss_iep.h | 73 +++++++++++++++++++++++- 2 files changed, 72 insertions(+), 73 deletions(-) diff --git a/drivers/net/ethernet/ti/icssg/icss_iep.c b/drivers/net/etherne= t/ti/icssg/icss_iep.c index 75c294ce6fb6..5d6d1cf78e93 100644 --- a/drivers/net/ethernet/ti/icssg/icss_iep.c +++ b/drivers/net/ethernet/ti/icssg/icss_iep.c @@ -53,78 +53,6 @@ #define IEP_CAP_CFG_CAPNR_1ST_EVENT_EN(n) BIT(LATCH_INDEX(n)) #define IEP_CAP_CFG_CAP_ASYNC_EN(n) BIT(LATCH_INDEX(n) + 10) =20 -enum { - ICSS_IEP_GLOBAL_CFG_REG, - ICSS_IEP_GLOBAL_STATUS_REG, - ICSS_IEP_COMPEN_REG, - ICSS_IEP_SLOW_COMPEN_REG, - ICSS_IEP_COUNT_REG0, - ICSS_IEP_COUNT_REG1, - ICSS_IEP_CAPTURE_CFG_REG, - ICSS_IEP_CAPTURE_STAT_REG, - - ICSS_IEP_CAP6_RISE_REG0, - ICSS_IEP_CAP6_RISE_REG1, - - ICSS_IEP_CAP7_RISE_REG0, - ICSS_IEP_CAP7_RISE_REG1, - - ICSS_IEP_CMP_CFG_REG, - ICSS_IEP_CMP_STAT_REG, - ICSS_IEP_CMP0_REG0, - ICSS_IEP_CMP0_REG1, - ICSS_IEP_CMP1_REG0, - ICSS_IEP_CMP1_REG1, - - ICSS_IEP_CMP8_REG0, - ICSS_IEP_CMP8_REG1, - ICSS_IEP_SYNC_CTRL_REG, - ICSS_IEP_SYNC0_STAT_REG, - ICSS_IEP_SYNC1_STAT_REG, - ICSS_IEP_SYNC_PWIDTH_REG, - ICSS_IEP_SYNC0_PERIOD_REG, - ICSS_IEP_SYNC1_DELAY_REG, - ICSS_IEP_SYNC_START_REG, - ICSS_IEP_MAX_REGS, -}; - -/** - * struct icss_iep_plat_data - Plat data to handle SoC variants - * @config: Regmap configuration data - * @reg_offs: register offsets to capture offset differences across SoCs - * @flags: Flags to represent IEP properties - */ -struct icss_iep_plat_data { - const struct regmap_config *config; - u32 reg_offs[ICSS_IEP_MAX_REGS]; - u32 flags; -}; - -struct icss_iep { - struct device *dev; - void __iomem *base; - const struct icss_iep_plat_data *plat_data; - struct regmap *map; - struct device_node *client_np; - unsigned long refclk_freq; - int clk_tick_time; /* one refclk tick time in ns */ - struct ptp_clock_info ptp_info; - struct ptp_clock *ptp_clock; - struct mutex ptp_clk_mutex; /* PHC access serializer */ - u32 def_inc; - s16 slow_cmp_inc; - u32 slow_cmp_count; - const struct icss_iep_clockops *ops; - void *clockops_data; - u32 cycle_time_ns; - u32 perout_enabled; - bool pps_enabled; - int cap_cmp_irq; - u64 period; - u32 latch_enable; - struct work_struct work; -}; - /** * icss_iep_get_count_hi() - Get the upper 32 bit IEP counter * @iep: Pointer to structure representing IEP. diff --git a/drivers/net/ethernet/ti/icssg/icss_iep.h b/drivers/net/etherne= t/ti/icssg/icss_iep.h index 803a4b714893..0bdca0155abd 100644 --- a/drivers/net/ethernet/ti/icssg/icss_iep.h +++ b/drivers/net/ethernet/ti/icssg/icss_iep.h @@ -12,7 +12,78 @@ #include #include =20 -struct icss_iep; +enum { + ICSS_IEP_GLOBAL_CFG_REG, + ICSS_IEP_GLOBAL_STATUS_REG, + ICSS_IEP_COMPEN_REG, + ICSS_IEP_SLOW_COMPEN_REG, + ICSS_IEP_COUNT_REG0, + ICSS_IEP_COUNT_REG1, + ICSS_IEP_CAPTURE_CFG_REG, + ICSS_IEP_CAPTURE_STAT_REG, + + ICSS_IEP_CAP6_RISE_REG0, + ICSS_IEP_CAP6_RISE_REG1, + + ICSS_IEP_CAP7_RISE_REG0, + ICSS_IEP_CAP7_RISE_REG1, + + ICSS_IEP_CMP_CFG_REG, + ICSS_IEP_CMP_STAT_REG, + ICSS_IEP_CMP0_REG0, + ICSS_IEP_CMP0_REG1, + ICSS_IEP_CMP1_REG0, + ICSS_IEP_CMP1_REG1, + + ICSS_IEP_CMP8_REG0, + ICSS_IEP_CMP8_REG1, + ICSS_IEP_SYNC_CTRL_REG, + ICSS_IEP_SYNC0_STAT_REG, + ICSS_IEP_SYNC1_STAT_REG, + ICSS_IEP_SYNC_PWIDTH_REG, + ICSS_IEP_SYNC0_PERIOD_REG, + ICSS_IEP_SYNC1_DELAY_REG, + ICSS_IEP_SYNC_START_REG, + ICSS_IEP_MAX_REGS, +}; + +/** + * struct icss_iep_plat_data - Plat data to handle SoC variants + * @config: Regmap configuration data + * @reg_offs: register offsets to capture offset differences across SoCs + * @flags: Flags to represent IEP properties + */ +struct icss_iep_plat_data { + const struct regmap_config *config; + u32 reg_offs[ICSS_IEP_MAX_REGS]; + u32 flags; +}; + +struct icss_iep { + struct device *dev; + void __iomem *base; + const struct icss_iep_plat_data *plat_data; + struct regmap *map; + struct device_node *client_np; + unsigned long refclk_freq; + int clk_tick_time; /* one refclk tick time in ns */ + struct ptp_clock_info ptp_info; + struct ptp_clock *ptp_clock; + struct mutex ptp_clk_mutex; /* PHC access serializer */ + u32 def_inc; + s16 slow_cmp_inc; + u32 slow_cmp_count; + const struct icss_iep_clockops *ops; + void *clockops_data; + u32 cycle_time_ns; + u32 perout_enabled; + bool pps_enabled; + int cap_cmp_irq; + u64 period; + u32 latch_enable; + struct work_struct work; +}; + extern const struct icss_iep_clockops prueth_iep_clockops; =20 /* Firmware specific clock operations */ --=20 2.34.1 From nobody Sat Nov 30 05:39:17 2024 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 679D014EC56; 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charset="utf-8" The def_inc is stored in icss_iep structure. Currently default increment (ns per clock tick) is hardcoded to 4 (Clock frequency being 250 MHz). Change this to use the iep->def_inc variable as the iep structure is now accessible to the driver files. Reviewed-by: Roger Quadros Signed-off-by: MD Danish Anwar --- drivers/net/ethernet/ti/icssg/icssg_prueth.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/ti/icssg/icssg_prueth.c b/drivers/net/eth= ernet/ti/icssg/icssg_prueth.c index 6644203d6bb7..5343d8754edd 100644 --- a/drivers/net/ethernet/ti/icssg/icssg_prueth.c +++ b/drivers/net/ethernet/ti/icssg/icssg_prueth.c @@ -365,7 +365,8 @@ static void prueth_iep_settime(void *clockops_data, u64= ns) sc_desc.cyclecounter0_set =3D cyclecount & GENMASK(31, 0); sc_desc.cyclecounter1_set =3D (cyclecount & GENMASK(63, 32)) >> 32; sc_desc.iepcount_set =3D ns % cycletime; - sc_desc.CMP0_current =3D cycletime - 4; //Count from 0 to (cycle time)-4 + /* Count from 0 to (cycle time) - emac->iep->def_inc */ + sc_desc.CMP0_current =3D cycletime - emac->iep->def_inc; =20 memcpy_toio(sc_descp, &sc_desc, sizeof(sc_desc)); =20 --=20 2.34.1 From nobody Sat Nov 30 05:39:17 2024 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FAD0155738; Wed, 11 Sep 2024 08:16:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726042597; cv=none; b=oWtt0gjVV25niCyG8Gj4/Jr670VvsGhA8XLKfnBABZDzm6RArmHPk/0nUNndDUqyhueDG0K0nBD9YYtA4dDC0Xsn+J4VWPOup1FtckgiaGXIcyWTkULqMYNHas2iK98OHeojw+0FYPF/buQnLX0q7V/hLC/aSRbLuVPua5wddRc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726042597; c=relaxed/simple; bh=5PVC8MmTUbpKF6nkyD+CD0/8TD1nkFetaGVQMs+C2rU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jMfj1rHZw9l4CCHZRtHdU12BBDP8TjNYHwIebibTGu8KoNW5TQTGEUbAFhM55vvUwkInBGbs1x9kSMzLCreKoVqp5fdIwkLdECSQSE8tjvz8tXBTaZZ+GMwI/AezI2BVcBeT26Rk3V7KaH7f9XdBVQIBzocSRxpmCvw2XTsjoAg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=KSW5Ah9O; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="KSW5Ah9O" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 48B8GBVe118244; Wed, 11 Sep 2024 03:16:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1726042571; bh=o7A5D20LM93+6zrhzEVAjPpi9zIBnLznhgTvwwbRzVY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=KSW5Ah9OqlgiYRk/VKiutzfMfWm2H4Lj/6ZGDGDYQJIVWPWxBqHVDQnjrNaT1bPKf XDyo1oPIk/zUyK8F+ZCVDBeZioxaTsDrtNKcTWuxI3kDMpkt0PwSEXpMrsGIVqOVWS Z4EBdH4m9Ej+3MTEB+5QtryRWPK0k7XCZXjGjeSI= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48B8GBZX092161; Wed, 11 Sep 2024 03:16:11 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 11 Sep 2024 03:16:11 -0500 Received: from fllvsmtp7.itg.ti.com (10.64.40.31) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 11 Sep 2024 03:16:11 -0500 Received: from lelv0854.itg.ti.com (lelv0854.itg.ti.com [10.181.64.140]) by fllvsmtp7.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48B8GBEJ066362; Wed, 11 Sep 2024 03:16:11 -0500 Received: from localhost (danish-tpc.dhcp.ti.com [10.24.69.25]) by lelv0854.itg.ti.com (8.14.7/8.14.7) with ESMTP id 48B8GAPq032135; Wed, 11 Sep 2024 03:16:11 -0500 From: MD Danish Anwar To: , , , , , , , , , , , , , , CC: , , , , Vignesh Raghavendra , Roger Quadros , Subject: [PATCH net-next v6 3/5] net: ti: icssg-prueth: Add support for HSR frame forward offload Date: Wed, 11 Sep 2024 13:46:01 +0530 Message-ID: <20240911081603.2521729-4-danishanwar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240911081603.2521729-1-danishanwar@ti.com> References: <20240911081603.2521729-1-danishanwar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Add support for offloading HSR port-to-port frame forward to hardware. When the slave interfaces are added to the HSR interface, the PRU cores will be stopped and ICSSG HSR firmwares will be loaded to them. Similarly, when HSR interface is deleted, the PRU cores will be restarted and the last used firmwares will be reloaded. PRUeth interfaces will be back to the last used mode. This commit also renames some APIs that are common between switch and hsr mode with '_fw_offload' suffix. Signed-off-by: MD Danish Anwar Reviewed-by: Roger Quadros --- .../net/ethernet/ti/icssg/icssg_classifier.c | 1 + drivers/net/ethernet/ti/icssg/icssg_config.c | 18 +-- drivers/net/ethernet/ti/icssg/icssg_prueth.c | 106 +++++++++++++++++- drivers/net/ethernet/ti/icssg/icssg_prueth.h | 6 + 4 files changed, 119 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/ti/icssg/icssg_classifier.c b/drivers/net= /ethernet/ti/icssg/icssg_classifier.c index 9ec504d976d6..833ca86d0b71 100644 --- a/drivers/net/ethernet/ti/icssg/icssg_classifier.c +++ b/drivers/net/ethernet/ti/icssg/icssg_classifier.c @@ -290,6 +290,7 @@ void icssg_class_set_host_mac_addr(struct regmap *miig_= rt, const u8 *mac) mac[2] << 16 | mac[3] << 24)); regmap_write(miig_rt, MAC_INTERFACE_1, (u32)(mac[4] | mac[5] << 8)); } +EXPORT_SYMBOL_GPL(icssg_class_set_host_mac_addr); =20 void icssg_class_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac) { diff --git a/drivers/net/ethernet/ti/icssg/icssg_config.c b/drivers/net/eth= ernet/ti/icssg/icssg_config.c index dae52a83a378..7b2e6c192ff3 100644 --- a/drivers/net/ethernet/ti/icssg/icssg_config.c +++ b/drivers/net/ethernet/ti/icssg/icssg_config.c @@ -107,7 +107,7 @@ static const struct map hwq_map[2][ICSSG_NUM_OTHER_QUEU= ES] =3D { }, }; =20 -static void icssg_config_mii_init_switch(struct prueth_emac *emac) +static void icssg_config_mii_init_fw_offload(struct prueth_emac *emac) { struct prueth *prueth =3D emac->prueth; int mii =3D prueth_emac_slice(emac); @@ -278,7 +278,7 @@ static int emac_r30_is_done(struct prueth_emac *emac) return 1; } =20 -static int prueth_switch_buffer_setup(struct prueth_emac *emac) +static int prueth_fw_offload_buffer_setup(struct prueth_emac *emac) { struct icssg_buffer_pool_cfg __iomem *bpool_cfg; struct icssg_rxq_ctx __iomem *rxq_ctx; @@ -424,7 +424,7 @@ static void icssg_init_emac_mode(struct prueth *prueth) icssg_class_set_host_mac_addr(prueth->miig_rt, mac); } =20 -static void icssg_init_switch_mode(struct prueth *prueth) +static void icssg_init_fw_offload_mode(struct prueth *prueth) { u32 addr =3D prueth->shram.pa + EMAC_ICSSG_SWITCH_DEFAULT_VLAN_TABLE_OFFS= ET; int i; @@ -455,8 +455,8 @@ int icssg_config(struct prueth *prueth, struct prueth_e= mac *emac, int slice) struct icssg_flow_cfg __iomem *flow_cfg; int ret; =20 - if (prueth->is_switch_mode) - icssg_init_switch_mode(prueth); + if (prueth->is_switch_mode || prueth->is_hsr_offload_mode) + icssg_init_fw_offload_mode(prueth); else icssg_init_emac_mode(prueth); =20 @@ -472,8 +472,8 @@ int icssg_config(struct prueth *prueth, struct prueth_e= mac *emac, int slice) regmap_update_bits(prueth->miig_rt, ICSSG_CFG_OFFSET, ICSSG_CFG_DEFAULT, ICSSG_CFG_DEFAULT); icssg_miig_set_interface_mode(prueth->miig_rt, slice, emac->phy_if); - if (prueth->is_switch_mode) - icssg_config_mii_init_switch(emac); + if (prueth->is_switch_mode || prueth->is_hsr_offload_mode) + icssg_config_mii_init_fw_offload(emac); else icssg_config_mii_init(emac); icssg_config_ipg(emac); @@ -498,8 +498,8 @@ int icssg_config(struct prueth *prueth, struct prueth_e= mac *emac, int slice) writeb(0, config + SPL_PKT_DEFAULT_PRIORITY); writeb(0, config + QUEUE_NUM_UNTAGGED); =20 - if (prueth->is_switch_mode) - ret =3D prueth_switch_buffer_setup(emac); + if (prueth->is_switch_mode || prueth->is_hsr_offload_mode) + ret =3D prueth_fw_offload_buffer_setup(emac); else ret =3D prueth_emac_buffer_setup(emac); if (ret) diff --git a/drivers/net/ethernet/ti/icssg/icssg_prueth.c b/drivers/net/eth= ernet/ti/icssg/icssg_prueth.c index 5343d8754edd..b38a4a6072c4 100644 --- a/drivers/net/ethernet/ti/icssg/icssg_prueth.c +++ b/drivers/net/ethernet/ti/icssg/icssg_prueth.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -40,6 +41,8 @@ #define DEFAULT_PORT_MASK 1 #define DEFAULT_UNTAG_MASK 1 =20 +#define NETIF_PRUETH_HSR_OFFLOAD_FEATURES NETIF_F_HW_HSR_FWD + /* CTRLMMR_ICSSG_RGMII_CTRL register bits */ #define ICSSG_CTRL_RGMII_ID_MODE BIT(24) =20 @@ -118,6 +121,19 @@ static irqreturn_t prueth_tx_ts_irq(int irq, void *dev= _id) return IRQ_HANDLED; } =20 +static struct icssg_firmwares icssg_hsr_firmwares[] =3D { + { + .pru =3D "ti-pruss/am65x-sr2-pru0-pruhsr-fw.elf", + .rtu =3D "ti-pruss/am65x-sr2-rtu0-pruhsr-fw.elf", + .txpru =3D "ti-pruss/am65x-sr2-txpru0-pruhsr-fw.elf", + }, + { + .pru =3D "ti-pruss/am65x-sr2-pru1-pruhsr-fw.elf", + .rtu =3D "ti-pruss/am65x-sr2-rtu1-pruhsr-fw.elf", + .txpru =3D "ti-pruss/am65x-sr2-txpru1-pruhsr-fw.elf", + } +}; + static struct icssg_firmwares icssg_switch_firmwares[] =3D { { .pru =3D "ti-pruss/am65x-sr2-pru0-prusw-fw.elf", @@ -152,6 +168,8 @@ static int prueth_emac_start(struct prueth *prueth, str= uct prueth_emac *emac) =20 if (prueth->is_switch_mode) firmwares =3D icssg_switch_firmwares; + else if (prueth->is_hsr_offload_mode) + firmwares =3D icssg_hsr_firmwares; else firmwares =3D icssg_emac_firmwares; =20 @@ -865,6 +883,7 @@ static int prueth_netdev_init(struct prueth *prueth, ndev->ethtool_ops =3D &icssg_ethtool_ops; ndev->hw_features =3D NETIF_F_SG; ndev->features =3D ndev->hw_features; + ndev->hw_features |=3D NETIF_PRUETH_HSR_OFFLOAD_FEATURES; =20 netif_napi_add(ndev, &emac->napi_rx, icssg_napi_rx_poll); hrtimer_init(&emac->rx_hrtimer, CLOCK_MONOTONIC, @@ -953,7 +972,7 @@ static void prueth_emac_restart(struct prueth *prueth) netif_device_attach(emac1->ndev); } =20 -static void icssg_enable_switch_mode(struct prueth *prueth) +static void icssg_change_mode(struct prueth *prueth) { struct prueth_emac *emac; int mac; @@ -973,8 +992,13 @@ static void icssg_enable_switch_mode(struct prueth *pr= ueth) BIT(emac->port_id) | DEFAULT_PORT_MASK, BIT(emac->port_id) | DEFAULT_UNTAG_MASK, true); + if (prueth->is_hsr_offload_mode) + icssg_vtbl_modify(emac, DEFAULT_VID, + DEFAULT_PORT_MASK, + DEFAULT_UNTAG_MASK, true); icssg_set_pvid(prueth, emac->port_vlan, emac->port_id); - icssg_set_port_state(emac, ICSSG_EMAC_PORT_VLAN_AWARE_ENABLE); + if (prueth->is_switch_mode) + icssg_set_port_state(emac, ICSSG_EMAC_PORT_VLAN_AWARE_ENABLE); } } } @@ -1012,7 +1036,7 @@ static int prueth_netdevice_port_link(struct net_devi= ce *ndev, prueth->is_switch_mode =3D true; prueth->default_vlan =3D 1; emac->port_vlan =3D prueth->default_vlan; - icssg_enable_switch_mode(prueth); + icssg_change_mode(prueth); } } =20 @@ -1040,6 +1064,61 @@ static void prueth_netdevice_port_unlink(struct net_= device *ndev) prueth->hw_bridge_dev =3D NULL; } =20 +static int prueth_hsr_port_link(struct net_device *ndev) +{ + struct prueth_emac *emac =3D netdev_priv(ndev); + struct prueth *prueth =3D emac->prueth; + struct prueth_emac *emac0; + struct prueth_emac *emac1; + + emac0 =3D prueth->emac[PRUETH_MAC0]; + emac1 =3D prueth->emac[PRUETH_MAC1]; + + if (prueth->is_switch_mode) + return -EOPNOTSUPP; + + prueth->hsr_members |=3D BIT(emac->port_id); + if (!prueth->is_hsr_offload_mode) { + if (prueth->hsr_members & BIT(PRUETH_PORT_MII0) && + prueth->hsr_members & BIT(PRUETH_PORT_MII1)) { + if (!(emac0->ndev->features & + NETIF_PRUETH_HSR_OFFLOAD_FEATURES) && + !(emac1->ndev->features & + NETIF_PRUETH_HSR_OFFLOAD_FEATURES)) + return -EOPNOTSUPP; + prueth->is_hsr_offload_mode =3D true; + prueth->default_vlan =3D 1; + emac0->port_vlan =3D prueth->default_vlan; + emac1->port_vlan =3D prueth->default_vlan; + icssg_change_mode(prueth); + netdev_dbg(ndev, "Enabling HSR offload mode\n"); + } + } + + return 0; +} + +static void prueth_hsr_port_unlink(struct net_device *ndev) +{ + struct prueth_emac *emac =3D netdev_priv(ndev); + struct prueth *prueth =3D emac->prueth; + struct prueth_emac *emac0; + struct prueth_emac *emac1; + + emac0 =3D prueth->emac[PRUETH_MAC0]; + emac1 =3D prueth->emac[PRUETH_MAC1]; + + prueth->hsr_members &=3D ~BIT(emac->port_id); + if (prueth->is_hsr_offload_mode) { + prueth->is_hsr_offload_mode =3D false; + emac0->port_vlan =3D 0; + emac1->port_vlan =3D 0; + prueth->hsr_dev =3D NULL; + prueth_emac_restart(prueth); + netdev_dbg(ndev, "Disabling HSR Offload mode\n"); + } +} + /* netdev notifier */ static int prueth_netdevice_event(struct notifier_block *unused, unsigned long event, void *ptr) @@ -1047,6 +1126,8 @@ static int prueth_netdevice_event(struct notifier_blo= ck *unused, struct netlink_ext_ack *extack =3D netdev_notifier_info_to_extack(ptr); struct net_device *ndev =3D netdev_notifier_info_to_dev(ptr); struct netdev_notifier_changeupper_info *info; + struct prueth_emac *emac =3D netdev_priv(ndev); + struct prueth *prueth =3D emac->prueth; int ret =3D NOTIFY_DONE; =20 if (ndev->netdev_ops !=3D &emac_netdev_ops) @@ -1056,6 +1137,25 @@ static int prueth_netdevice_event(struct notifier_bl= ock *unused, case NETDEV_CHANGEUPPER: info =3D ptr; =20 + if ((ndev->features & NETIF_PRUETH_HSR_OFFLOAD_FEATURES) && + is_hsr_master(info->upper_dev)) { + if (info->linking) { + if (!prueth->hsr_dev) { + prueth->hsr_dev =3D info->upper_dev; + icssg_class_set_host_mac_addr(prueth->miig_rt, + prueth->hsr_dev->dev_addr); + } else { + if (prueth->hsr_dev !=3D info->upper_dev) { + netdev_dbg(ndev, "Both interfaces must be linked to same upper devic= e\n"); + return -EOPNOTSUPP; + } + } + prueth_hsr_port_link(ndev); + } else { + prueth_hsr_port_unlink(ndev); + } + } + if (netif_is_bridge_master(info->upper_dev)) { if (info->linking) ret =3D prueth_netdevice_port_link(ndev, info->upper_dev, extack); diff --git a/drivers/net/ethernet/ti/icssg/icssg_prueth.h b/drivers/net/eth= ernet/ti/icssg/icssg_prueth.h index 786bd1ba34ab..a4b025fae797 100644 --- a/drivers/net/ethernet/ti/icssg/icssg_prueth.h +++ b/drivers/net/ethernet/ti/icssg/icssg_prueth.h @@ -243,11 +243,14 @@ struct icssg_firmwares { * @iep1: pointer to IEP1 device * @vlan_tbl: VLAN-FID table pointer * @hw_bridge_dev: pointer to HW bridge net device + * @hsr_dev: pointer to the HSR net device * @br_members: bitmask of bridge member ports + * @hsr_members: bitmask of hsr member ports * @prueth_netdevice_nb: netdevice notifier block * @prueth_switchdev_nb: switchdev notifier block * @prueth_switchdev_bl_nb: switchdev blocking notifier block * @is_switch_mode: flag to indicate if device is in Switch mode + * @is_hsr_offload_mode: flag to indicate if device is in hsr offload mode * @is_switchmode_supported: indicates platform support for switch mode * @switch_id: ID for mapping switch ports to bridge * @default_vlan: Default VLAN for host @@ -279,11 +282,14 @@ struct prueth { struct prueth_vlan_tbl *vlan_tbl; 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Wed, 11 Sep 2024 03:16:13 -0500 Received: from lelv0854.itg.ti.com (lelv0854.itg.ti.com [10.181.64.140]) by fllvsmtp8.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48B8GDoE119138; Wed, 11 Sep 2024 03:16:13 -0500 Received: from localhost (danish-tpc.dhcp.ti.com [10.24.69.25]) by lelv0854.itg.ti.com (8.14.7/8.14.7) with ESMTP id 48B8GCRf032142; Wed, 11 Sep 2024 03:16:13 -0500 From: MD Danish Anwar To: , , , , , , , , , , , , , , CC: , , , , Vignesh Raghavendra , Roger Quadros , Subject: [PATCH net-next v6 4/5] net: ti: icssg-prueth: Enable HSR Tx duplication, Tx Tag and Rx Tag offload Date: Wed, 11 Sep 2024 13:46:02 +0530 Message-ID: <20240911081603.2521729-5-danishanwar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240911081603.2521729-1-danishanwar@ti.com> References: <20240911081603.2521729-1-danishanwar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Ravi Gunasekaran The HSR stack allows to offload its Tx packet duplication functionality to the hardware. Enable this offloading feature for ICSSG driver. Add support to offload HSR Tx Tag Insertion and Rx Tag Removal and duplicate discard. hsr tag insertion offload and hsr dup offload are tightly coupled in firmware implementation. Both these features need to be enabled / disabled together. Duplicate discard is done as part of RX tag removal and it is done by the firmware. When driver sends the r30 command ICSSG_EMAC_HSR_RX_OFFLOAD_ENABLE, firmware does RX tag removal as well as duplicate discard. Signed-off-by: Ravi Gunasekaran Signed-off-by: MD Danish Anwar --- drivers/net/ethernet/ti/icssg/icssg_common.c | 18 ++++++++-- drivers/net/ethernet/ti/icssg/icssg_config.c | 4 ++- drivers/net/ethernet/ti/icssg/icssg_config.h | 2 ++ drivers/net/ethernet/ti/icssg/icssg_prueth.c | 36 +++++++++++++++++++- drivers/net/ethernet/ti/icssg/icssg_prueth.h | 3 ++ 5 files changed, 58 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/ti/icssg/icssg_common.c b/drivers/net/eth= ernet/ti/icssg/icssg_common.c index b9d8a93d1680..fdebeb2f84e0 100644 --- a/drivers/net/ethernet/ti/icssg/icssg_common.c +++ b/drivers/net/ethernet/ti/icssg/icssg_common.c @@ -660,14 +660,15 @@ enum netdev_tx icssg_ndo_start_xmit(struct sk_buff *s= kb, struct net_device *ndev { struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; struct prueth_emac *emac =3D netdev_priv(ndev); + struct prueth *prueth =3D emac->prueth; struct netdev_queue *netif_txq; struct prueth_tx_chn *tx_chn; dma_addr_t desc_dma, buf_dma; + u32 pkt_len, dst_tag_id; int i, ret =3D 0, q_idx; bool in_tx_ts =3D 0; int tx_ts_cookie; void **swdata; - u32 pkt_len; u32 *epib; =20 pkt_len =3D skb_headlen(skb); @@ -712,9 +713,20 @@ enum netdev_tx icssg_ndo_start_xmit(struct sk_buff *sk= b, struct net_device *ndev =20 /* set dst tag to indicate internal qid at the firmware which is at * bit8..bit15. bit0..bit7 indicates port num for directed - * packets in case of switch mode operation + * packets in case of switch mode operation and port num 0 + * for undirected packets in case of HSR offload mode */ - cppi5_desc_set_tags_ids(&first_desc->hdr, 0, (emac->port_id | (q_idx << 8= ))); + dst_tag_id =3D emac->port_id | (q_idx << 8); + + if (prueth->is_hsr_offload_mode && + (ndev->features & NETIF_F_HW_HSR_DUP)) + dst_tag_id =3D PRUETH_UNDIRECTED_PKT_DST_TAG; + + if (prueth->is_hsr_offload_mode && + (ndev->features & NETIF_F_HW_HSR_TAG_INS)) + epib[1] |=3D PRUETH_UNDIRECTED_PKT_TAG_INS; + + cppi5_desc_set_tags_ids(&first_desc->hdr, 0, dst_tag_id); k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); swdata =3D cppi5_hdesc_get_swdata(first_desc); diff --git a/drivers/net/ethernet/ti/icssg/icssg_config.c b/drivers/net/eth= ernet/ti/icssg/icssg_config.c index 7b2e6c192ff3..72ace151d8e9 100644 --- a/drivers/net/ethernet/ti/icssg/icssg_config.c +++ b/drivers/net/ethernet/ti/icssg/icssg_config.c @@ -531,7 +531,9 @@ static const struct icssg_r30_cmd emac_r32_bitmask[] = =3D { {{EMAC_NONE, 0xffff4000, EMAC_NONE, EMAC_NONE}}, /* Preemption on Tx ENA= BLE*/ {{EMAC_NONE, 0xbfff0000, EMAC_NONE, EMAC_NONE}}, /* Preemption on Tx DIS= ABLE*/ {{0xffff0010, EMAC_NONE, 0xffff0010, EMAC_NONE}}, /* VLAN AWARE*/ - {{0xffef0000, EMAC_NONE, 0xffef0000, EMAC_NONE}} /* VLAN UNWARE*/ + {{0xffef0000, EMAC_NONE, 0xffef0000, EMAC_NONE}}, /* VLAN UNWARE*/ + {{0xffff2000, EMAC_NONE, EMAC_NONE, EMAC_NONE}}, /* HSR_RX_OFFLOAD_ENABLE= */ + {{0xdfff0000, EMAC_NONE, EMAC_NONE, EMAC_NONE}} /* HSR_RX_OFFLOAD_DISABL= E */ }; =20 int icssg_set_port_state(struct prueth_emac *emac, diff --git a/drivers/net/ethernet/ti/icssg/icssg_config.h b/drivers/net/eth= ernet/ti/icssg/icssg_config.h index 1ac60283923b..92c2deaa3068 100644 --- a/drivers/net/ethernet/ti/icssg/icssg_config.h +++ b/drivers/net/ethernet/ti/icssg/icssg_config.h @@ -80,6 +80,8 @@ enum icssg_port_state_cmd { ICSSG_EMAC_PORT_PREMPT_TX_DISABLE, ICSSG_EMAC_PORT_VLAN_AWARE_ENABLE, ICSSG_EMAC_PORT_VLAN_AWARE_DISABLE, + ICSSG_EMAC_HSR_RX_OFFLOAD_ENABLE, + ICSSG_EMAC_HSR_RX_OFFLOAD_DISABLE, ICSSG_EMAC_PORT_MAX_COMMANDS }; =20 diff --git a/drivers/net/ethernet/ti/icssg/icssg_prueth.c b/drivers/net/eth= ernet/ti/icssg/icssg_prueth.c index b38a4a6072c4..d128764982ae 100644 --- a/drivers/net/ethernet/ti/icssg/icssg_prueth.c +++ b/drivers/net/ethernet/ti/icssg/icssg_prueth.c @@ -41,7 +41,10 @@ #define DEFAULT_PORT_MASK 1 #define DEFAULT_UNTAG_MASK 1 =20 -#define NETIF_PRUETH_HSR_OFFLOAD_FEATURES NETIF_F_HW_HSR_FWD +#define NETIF_PRUETH_HSR_OFFLOAD_FEATURES (NETIF_F_HW_HSR_FWD | \ + NETIF_F_HW_HSR_DUP | \ + NETIF_F_HW_HSR_TAG_INS | \ + NETIF_F_HW_HSR_TAG_RM) =20 /* CTRLMMR_ICSSG_RGMII_CTRL register bits */ #define ICSSG_CTRL_RGMII_ID_MODE BIT(24) @@ -744,6 +747,29 @@ static void emac_ndo_set_rx_mode(struct net_device *nd= ev) queue_work(emac->cmd_wq, &emac->rx_mode_work); } =20 +static netdev_features_t emac_ndo_fix_features(struct net_device *ndev, + netdev_features_t features) +{ + /* hsr tag insertion offload and hsr dup offload are tightly coupled in + * firmware implementation. Both these features need to be enabled / + * disabled together. + */ + if (!(ndev->features & (NETIF_F_HW_HSR_DUP | NETIF_F_HW_HSR_TAG_INS))) + if ((features & NETIF_F_HW_HSR_DUP) || + (features & NETIF_F_HW_HSR_TAG_INS)) + features |=3D NETIF_F_HW_HSR_DUP | + NETIF_F_HW_HSR_TAG_INS; + + if ((ndev->features & NETIF_F_HW_HSR_DUP) || + (ndev->features & NETIF_F_HW_HSR_TAG_INS)) + if (!(features & NETIF_F_HW_HSR_DUP) || + !(features & NETIF_F_HW_HSR_TAG_INS)) + features &=3D ~(NETIF_F_HW_HSR_DUP | + NETIF_F_HW_HSR_TAG_INS); + + return features; +} + static const struct net_device_ops emac_netdev_ops =3D { .ndo_open =3D emac_ndo_open, .ndo_stop =3D emac_ndo_stop, @@ -755,6 +781,7 @@ static const struct net_device_ops emac_netdev_ops =3D { .ndo_eth_ioctl =3D icssg_ndo_ioctl, .ndo_get_stats64 =3D icssg_ndo_get_stats64, .ndo_get_phys_port_name =3D icssg_ndo_get_phys_port_name, + .ndo_fix_features =3D emac_ndo_fix_features, }; =20 static int prueth_netdev_init(struct prueth *prueth, @@ -981,6 +1008,13 @@ static void icssg_change_mode(struct prueth *prueth) =20 for (mac =3D PRUETH_MAC0; mac < PRUETH_NUM_MACS; mac++) { emac =3D prueth->emac[mac]; + if (prueth->is_hsr_offload_mode) { + if (emac->ndev->features & NETIF_F_HW_HSR_TAG_RM) + icssg_set_port_state(emac, ICSSG_EMAC_HSR_RX_OFFLOAD_ENABLE); + else + icssg_set_port_state(emac, ICSSG_EMAC_HSR_RX_OFFLOAD_DISABLE); + } + if (netif_running(emac->ndev)) { icssg_fdb_add_del(emac, eth_stp_addr, prueth->default_vlan, ICSSG_FDB_ENTRY_P0_MEMBERSHIP | diff --git a/drivers/net/ethernet/ti/icssg/icssg_prueth.h b/drivers/net/eth= ernet/ti/icssg/icssg_prueth.h index a4b025fae797..bba6da2e6bd8 100644 --- a/drivers/net/ethernet/ti/icssg/icssg_prueth.h +++ b/drivers/net/ethernet/ti/icssg/icssg_prueth.h @@ -59,6 +59,9 @@ =20 #define IEP_DEFAULT_CYCLE_TIME_NS 1000000 /* 1 ms */ =20 +#define PRUETH_UNDIRECTED_PKT_DST_TAG 0 +#define PRUETH_UNDIRECTED_PKT_TAG_INS BIT(30) + /* Firmware status codes */ #define ICSS_HS_FW_READY 0x55555555 #define ICSS_HS_FW_DEAD 0xDEAD0000 /* lower 16 bits contain error code */ --=20 2.34.1 From nobody Sat Nov 30 05:39:17 2024 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07976176AB7; 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charset="utf-8" Add support for multicast filtering in HSR mode Reviewed-by: Roger Quadros Signed-off-by: MD Danish Anwar --- drivers/net/ethernet/ti/icssg/icssg_prueth.c | 42 +++++++++++++++++++- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/ti/icssg/icssg_prueth.c b/drivers/net/eth= ernet/ti/icssg/icssg_prueth.c index d128764982ae..5fd9902ab181 100644 --- a/drivers/net/ethernet/ti/icssg/icssg_prueth.c +++ b/drivers/net/ethernet/ti/icssg/icssg_prueth.c @@ -492,6 +492,36 @@ static int icssg_prueth_del_mcast(struct net_device *n= dev, const u8 *addr) return 0; } =20 +static int icssg_prueth_hsr_add_mcast(struct net_device *ndev, const u8 *a= ddr) +{ + struct prueth_emac *emac =3D netdev_priv(ndev); + struct prueth *prueth =3D emac->prueth; + + icssg_fdb_add_del(emac, addr, prueth->default_vlan, + ICSSG_FDB_ENTRY_P0_MEMBERSHIP | + ICSSG_FDB_ENTRY_P1_MEMBERSHIP | + ICSSG_FDB_ENTRY_P2_MEMBERSHIP | + ICSSG_FDB_ENTRY_BLOCK, true); + + icssg_vtbl_modify(emac, emac->port_vlan, BIT(emac->port_id), + BIT(emac->port_id), true); + return 0; +} + +static int icssg_prueth_hsr_del_mcast(struct net_device *ndev, const u8 *a= ddr) +{ + struct prueth_emac *emac =3D netdev_priv(ndev); + struct prueth *prueth =3D emac->prueth; + + icssg_fdb_add_del(emac, addr, prueth->default_vlan, + ICSSG_FDB_ENTRY_P0_MEMBERSHIP | + ICSSG_FDB_ENTRY_P1_MEMBERSHIP | + ICSSG_FDB_ENTRY_P2_MEMBERSHIP | + ICSSG_FDB_ENTRY_BLOCK, false); + + return 0; +} + /** * emac_ndo_open - EMAC device open * @ndev: network adapter device @@ -652,7 +682,10 @@ static int emac_ndo_stop(struct net_device *ndev) =20 icssg_class_disable(prueth->miig_rt, prueth_emac_slice(emac)); =20 - __dev_mc_unsync(ndev, icssg_prueth_del_mcast); + if (emac->prueth->is_hsr_offload_mode) + __dev_mc_unsync(ndev, icssg_prueth_hsr_del_mcast); + else + __dev_mc_unsync(ndev, icssg_prueth_del_mcast); =20 atomic_set(&emac->tdown_cnt, emac->tx_ch_num); /* ensure new tdown_cnt value is visible */ @@ -730,7 +763,12 @@ static void emac_ndo_set_rx_mode_work(struct work_stru= ct *work) return; } =20 - __dev_mc_sync(ndev, icssg_prueth_add_mcast, icssg_prueth_del_mcast); + if (emac->prueth->is_hsr_offload_mode) + __dev_mc_sync(ndev, icssg_prueth_hsr_add_mcast, + icssg_prueth_hsr_del_mcast); + else + __dev_mc_sync(ndev, icssg_prueth_add_mcast, + icssg_prueth_del_mcast); } =20 /** --=20 2.34.1