From nobody Sat Nov 30 03:28:39 2024 Received: from mail-pg1-f180.google.com (mail-pg1-f180.google.com [209.85.215.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D7BE188A22 for ; Thu, 12 Sep 2024 05:55:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120550; cv=none; b=GxKgZoIvDpAwHefgjPw8odYoHhSX9OB+8VbYSfYorKifmtZFdNGW16eOuHJC5xKngmg2ig+C1kKQQoEWYm7grMMjcqrUQQVwmPZ3sTUWDYn4VA5DvC6NZAnfXTA1DGMzfu2ZIjnCBurPnYtgHsPijZG/Bdxbs/77H1+LVunP/34= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120550; c=relaxed/simple; bh=n+1uXcpPSzDKbEZ3gf2yswWeiNf7ojNdJOC78EyvEvs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oyodHnS7ycPBPctJ+PfJ9w6RRXQuDSGMWC8nnrhLDzvk6Dw6mluFyZ4LH/+146DyMf6dd07gZwyAWXJ4/aAqHis760hbiVZX0JEq3CjU1QvpWBag7a/fPRI3DR8ZfMiSDi3TRvw++evmpYIWfanddEeYu40+Y4Vimq1X1qwzvpo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=snt5MbLj; arc=none smtp.client-ip=209.85.215.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="snt5MbLj" Received: by mail-pg1-f180.google.com with SMTP id 41be03b00d2f7-7d4fa972cbeso469971a12.2 for ; Wed, 11 Sep 2024 22:55:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1726120547; x=1726725347; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=XJ+D4p75bjfTb0EItLpHxQIjWmqIJlAlnUMhz5TxedE=; b=snt5MbLj+IcENEwYb0XRZagHioPIPXExiA0a5u4LjDbgsZa361tr1OL3+pS2d3CjFc 87J6plf1YrDqGXpMMyAI1rf8hvNIKbTL6YEvhakIjh59eC2clvSgedReo55M06HUqUyT aV8d7ULxpFioiFDqca/roiG9C5s2+NMPC0Qk/yANo4/k5Aoe7eIkm2qxUHdYRGDb+W68 tnBbAvFt5NCL7jwecTYuUMcvjbRr7HRal+/n8jeXnniXcc9fxRdvvNCPyLwO9HiLHamD r0G+Z6BDKDA3uaGaSlpBVLj6drXmltzrLPoumK25oMkNw+iVBy7tAlkTF+RQg5Z3hVMk 64mA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726120547; x=1726725347; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XJ+D4p75bjfTb0EItLpHxQIjWmqIJlAlnUMhz5TxedE=; b=gPcr0vmArW2+/vLGPWTWBY+Nw8jsLa/jlY6s3Ma6cXtFyB8Od/d4Uw3WhGVKwNcJar LPYGjSv1lzUsuRKDlzMFkwEf0xKhELb91AjAr5CUKoWHXun2ySk3bi6F7dvE4nkUMDn7 NeFf6tAGTcE+c2hAijoxtCfdI9Cg60aTydIlu0+A7wdGQOpMpN/GpJ3ES6JlrAUz1k2X JCzKuYz6IVznaa5DwE7vzQdMAq4bsnqxrJug0B8i30oRstXQh52YoToTUSboLjyIns4n Ck3yKMeUqjw1wm5XsjhqUVUUPiFfa7GkRVlM2inyfVhedXfiwEHwOULVxahpn/1pCXXN IS6Q== X-Forwarded-Encrypted: i=1; AJvYcCUULdyfSVpuMrknVlPxWEoSYxA41LYGZIPcfD8pner5EMgDZauv1wCXxsdAX2FdBkzqxOmHJa6oczVMH98=@vger.kernel.org X-Gm-Message-State: AOJu0YwhcxzuYPpimoae+ycF5QwJuMW99z8naStU2qhBz5hDzo2Tddvx QIuQ+9FcoAvftT6jqn9AF3LHe4hEBgyMVoowv6SO0hfRQG/MMtufPWS5DemmjBA= X-Google-Smtp-Source: AGHT+IG9O0CsFGhPXNWP6Lh0fHcN+qnZpsCNiZQA7ou2TZYGAxKoqEVVtduYd2aqXpKrOB/KDynEnQ== X-Received: by 2002:a17:902:bc82:b0:202:4712:e838 with SMTP id d9443c01a7336-2076e34805fmr20473945ad.14.1726120546804; Wed, 11 Sep 2024 22:55:46 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe99b6sm7870465ad.209.2024.09.11.22.55.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 22:55:45 -0700 (PDT) From: Charlie Jenkins Date: Wed, 11 Sep 2024 22:55:09 -0700 Subject: [PATCH v10 01/14] dt-bindings: riscv: Add xtheadvector ISA extension description Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240911-xtheadvector-v10-1-8d3930091246@rivosinc.com> References: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> In-Reply-To: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Conor Dooley X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1788; i=charlie@rivosinc.com; h=from:subject:message-id; bh=n+1uXcpPSzDKbEZ3gf2yswWeiNf7ojNdJOC78EyvEvs=; b=owGbwMvMwCHWx5hUnlvL8Y3xtFoSQ9qjpqgZ1w/w/ftku2TJD4uz+t+3x4iXX2BNW5b+/WQo6 8bjN+eIdJSyMIhxMMiKKbLwXGtgbr2jX3ZUtGwCzBxWJpAhDFycAjARlTOMDF/jJh5VvijwP67J VKVJwXXLN+O4Ccpr4rb16DJeSYqLLGD47+eWbnRtrtIkRe/gq3cFjFfOFeOyVO+O70hJSZ+nude JHQA= X-Developer-Key: i=charlie@rivosinc.com; a=openpgp; fpr=7D834FF11B1D8387E61C776FFB10D1F27D6B1354 The xtheadvector ISA extension is described on the T-Head extension spec Github page [1] at commit 95358cb2cca9. Link: https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9= 489361c61d335e03d3134b14133f/xtheadvector.adoc [1] Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley Reviewed-by: Andy Chiu --- Documentation/devicetree/bindings/riscv/extensions.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index a06dbc6b4928..1a3d01aedde6 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -556,6 +556,10 @@ properties: latency, as ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. =20 + # vendor extensions, each extension sorted alphanumerically under = the + # vendor they belong to. Vendors are sorted alphanumerically as we= ll. + + # Andes - const: xandespmu description: The Andes Technology performance monitor extension for counter= overflow @@ -563,6 +567,12 @@ properties: Registers in the AX45MP datasheet. https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.= 0.0-Datasheet.pdf =20 + # T-HEAD + - const: xtheadvector + description: + The T-HEAD specific 0.7.1 vector implementation as written in + https://github.com/T-head-Semi/thead-extension-spec/blob/95358= cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc. + allOf: # Zcb depends on Zca - if: --=20 2.45.0 From nobody Sat Nov 30 03:28:39 2024 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24190189536 for ; Thu, 12 Sep 2024 05:55:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120551; cv=none; b=jnod0GZQ9UfrZoG2HUN7i8NNiqLF7I11DmcaEcjW+sB3RdmiDLxeUJtAK/GBJcj6RiKWEh28DPFiB+vwzgPhCRyJ1Xgf2SwUalyiFE942M6MwUZVJkvCVqY1tou0fNpHswZndhtnNiS9K6DW2YTJbjphe3SlOD5xiFZeFxxbMSY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120551; c=relaxed/simple; bh=g0Gsy+5TQh3RSmd39xewdNDSsmzEd+HtR+40T1Y+noY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=q4Ciml7l2e4KFJUCKU+Fhg8MMZaM929e9ZMQsMggP4Q3QlKLMlaKJS00zpfJEq20aVLB+aJD4mCah2CDjXxoYwv9Uii+DkgSXgVGO4TntJiFp8KWjAUAPPJwIyPVZe+bhVw9wymBc4JZSrZNTrR42lRdZ/errQ4viZmfaOZJD2o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=1UTbr/Y3; arc=none smtp.client-ip=209.85.214.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="1UTbr/Y3" Received: by mail-pl1-f169.google.com with SMTP id d9443c01a7336-2053a0bd0a6so6472995ad.3 for ; Wed, 11 Sep 2024 22:55:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1726120549; x=1726725349; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=8a31h58dvirjjptvxje9y9Mqcx9iPDZwg1ciuyTglV0=; b=1UTbr/Y3hs1UDqtntIp9L6nDOdpZ1Kp/pVTR2rOwTpBkjzDghN3wuSPZVLZ8LEap4V 7LCPI8kTCGzNVzAcJFBYS+MKCtQXMXcoUOXFArx1wXK8Le6xjJpS80fyCKejq3Ubadsn p8fHwJL4MqRgvvH2RpBsxNGxq7X8ySTG3L3G7Z9COWE56SVUM0KaFwNaGjfKsXHETsFP AG9MmkX/rdJAEqFbimVeoNkS0hilY//LLowHj+5iFZijIDnnpliiEhXGNPXqurRP1kro 6JQfQ7G1Dl6qQ5zK+LvTG9N0oB3nDDYSk05btCrR/xO5Y6IFbStk6gcaY1ql1Kw9Zild dWUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726120549; x=1726725349; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8a31h58dvirjjptvxje9y9Mqcx9iPDZwg1ciuyTglV0=; b=i8H2+1a6cB8+tgjbzBeGJBQVGJtb5Xo8IrYrvt7VoaQ6ejMKZGFR2bnReIClA1Jp0z IGspWlc1nlwF1spcdzcfhQKul54ARzqIw3Unit8srsf2X1PJH9PtVw78naxbFf7+k/d1 g5FuF0OxEzuTFQcLs0MOf19fA0GJfWpkgkDPRrcEmNZ4brS7olWCRh3qkWvDmcMCFLUr pyYeJ26M/DgyUavO1sTVT1Vq3+fS5surQSv2WoMzEAdQR1cYNrDKM09uW2yfm0wi+qVi WxNvZyLRzFReyKOzTfPBHq2C4hOTZ+yFbrSs/eFSvqsRGkY+ZdjOi9WEODsyvQ5aWfb3 6xOg== X-Forwarded-Encrypted: i=1; AJvYcCWbmLTJHZU3ppZl5PBZmVA4UAeJnQtMTk3o+QVX0odpjxk2kgqvpLluqY5jTdwEjU9UInDmZFLLF50Jny0=@vger.kernel.org X-Gm-Message-State: AOJu0Ywp3poQ/tjZdLX8lv81x0R7HOpOVsUg93owX8U9EVlfphAhM7yd zNRdXsniC+7BcWIWZibL2KTnk0IFhlWfjMNZMWLsxOMnvgSbnU/0Zs5H2OSz/+o= X-Google-Smtp-Source: AGHT+IHKCeM+iDzgTZA8iai8wEAdx48qgNifGNBqlmMlN3z+2F0fcjMXoHNP4W4BOCCsUutd/a9kSQ== X-Received: by 2002:a17:902:d2ca:b0:207:1848:7221 with SMTP id d9443c01a7336-2076e435f13mr19074275ad.53.1726120549289; Wed, 11 Sep 2024 22:55:49 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe99b6sm7870465ad.209.2024.09.11.22.55.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 22:55:48 -0700 (PDT) From: Charlie Jenkins Date: Wed, 11 Sep 2024 22:55:10 -0700 Subject: [PATCH v10 02/14] dt-bindings: cpus: add a thead vlen register length property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240911-xtheadvector-v10-2-8d3930091246@rivosinc.com> References: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> In-Reply-To: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Conor Dooley X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1911; i=charlie@rivosinc.com; h=from:subject:message-id; bh=g0Gsy+5TQh3RSmd39xewdNDSsmzEd+HtR+40T1Y+noY=; b=owGbwMvMwCHWx5hUnlvL8Y3xtFoSQ9qjpqi6xw2/1SybArcG9ZkvPNr7wOuI2MvGzcmpp08lM 4gsfHalo5SFQYyDQVZMkYXnWgNz6x39sqOiZRNg5rAygQxh4OIUgInck2T4wx8msdT1Y+GCg4JJ iw/fOWJy7lHE19wTRd83WVxqDmV9ycrI0K+yobbz0fd2lzOdi1gq/n0TaeVWlxX4l5/FcOe1xYd lTAA= X-Developer-Key: i=charlie@rivosinc.com; a=openpgp; fpr=7D834FF11B1D8387E61C776FFB10D1F27D6B1354 Add a property analogous to the vlenb CSR so that software can detect the vector length of each CPU prior to it being brought online. Currently software has to assume that the vector length read from the boot CPU applies to all possible CPUs. On T-Head CPUs implementing pre-ratification vector, reading the th.vlenb CSR may produce an illegal instruction trap, so this property is required on such systems. Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley Reviewed-by: Andy Chiu --- Documentation/devicetree/bindings/riscv/cpus.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index 8edc8261241a..c0cf6cf56749 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -26,6 +26,18 @@ description: | allOf: - $ref: /schemas/cpu.yaml# - $ref: extensions.yaml + - if: + not: + properties: + compatible: + contains: + enum: + - thead,c906 + - thead,c910 + - thead,c920 + then: + properties: + thead,vlenb: false =20 properties: compatible: @@ -95,6 +107,13 @@ properties: description: The blocksize in bytes for the Zicboz cache operations. =20 + thead,vlenb: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + VLEN/8, the vector register length in bytes. This property is requir= ed on + thead systems where the vector register length is not identical on a= ll harts, or + the vlenb CSR is not available. + # RISC-V has multiple properties for cache op block sizes as the sizes # differ between individual CBO extensions cache-op-block-size: false --=20 2.45.0 From nobody Sat Nov 30 03:28:39 2024 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64DEA18BB86 for ; Thu, 12 Sep 2024 05:55:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120553; cv=none; b=CDBBUESyo+FMfddTRnc8ZZ1vKLqO+Nq4+Mcxch1k6DJV5tF1EzqXOZ2oz2Etyp4LXS8vGqvWRriRP8K1ynFPQDR471eyb1nFS/VOhvSIdQfaU8qgkjUFoSP6vnpj8zbsa2BcJ6jnewv4WpyHO1+PmLzs43im9nR9DjAJAulrVfM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120553; c=relaxed/simple; bh=twijwVNwXlRnqiWorC6lSyhzIHtshmEdOl4sTIAcK5Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dOi9rvcuFBWwSZPUJ0/9Dkt99JcdxvOyxWI45M7oXNdL/WZCoXk9OMT3AIWkRIXx8eYIIPPK+YANjLhTvN1sDLDt6uMZ9GJRf2ekHDKZ1kZhmMpFtd8RNnTM+YAypki7G9Tq9qibuWN7185DbZHiypfK3K38YDMUSAg1FKzfkIs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=ardJLvNY; arc=none smtp.client-ip=209.85.214.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="ardJLvNY" Received: by mail-pl1-f173.google.com with SMTP id d9443c01a7336-2053a0bd0a6so6473235ad.3 for ; Wed, 11 Sep 2024 22:55:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1726120552; x=1726725352; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=34tWDw4L8SN+akOs9Do5H0mwwhItc2hNKASWAYLthDo=; b=ardJLvNYZg5KC9Zh1GkwJJZOeIJWKLY3NH4zVjzGRbTtgz+ZUi683PNOIZyICYh4/x vJ0Paaapn5FRD+Jx6rjI9hiMRFim/PaTjppCy+5x4zE+7xnACoPNMOdbrzvS3vi/j3T4 AazJrhJztXwuPRF055H1z4yYaEVx1vENwGFQ3CuWnoEo9WWZFzsHwlEygwjdtghvqmAe KSDVcsreN7HqzSPS6uKgCwArB4tasjezM8n5Q551v4rXZavJdWsMrAVjdGhVN89H162a XkMLfhlNSu0XLeVLFoHuv862Y27xuqGO6tgQy1N9QwfVUtAYB631O/genSNmaWyBtovk 4d0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726120552; x=1726725352; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=34tWDw4L8SN+akOs9Do5H0mwwhItc2hNKASWAYLthDo=; b=cESQuaCzq6WlCNfMMgJP2TGkXgJm89xSamnMNQ8f/4Za7itpTsIGNYvho+naJw+XZH sU3vmb4Nydi2U/ivK5rUwKqbhIak+Xw+gzk5dZgO2dRDcfflrf6grcrWWFPpo/a7louh f8P8DhLjeYEuG+UEpdqxV+3nRo9mBFwLM+LMuCt5ZEegDsYDK3J2NfcfUxxOvC1V7k52 n14RDI1pODPjEe/0HQFvLTtd9JXtWTn47pQtx+P7apG6pi6FAtaER15aCLBwDodzDNvc bFz1h1JmMcPqn2mBRoNqva+Bk0c40/I99WIpEDXBA58I5uGqzndCslwCEW7xYRt+VSLt SPLQ== X-Forwarded-Encrypted: i=1; AJvYcCXgw0unbxObIHdVPYmziGrqL4Y/+hr3fv4CD+mfDsvIERHO4fde+L6Gpjl0EM8dyizyNL/LZ675CF8wMFs=@vger.kernel.org X-Gm-Message-State: AOJu0YzLMKNkNuYB/jUt6L0M03T1AYbmehfE2TDmwCG4omdUbCPbwbbZ 8frevtLzsSWijmOqJokr+OiUTdrPHqbV15qyKcRz/Kk/bZbRkgfbJNkRTAkaSQQ= X-Google-Smtp-Source: AGHT+IFiwN7AL0oMOImj8Bb6j31gbdzpkXOKklYI/Dyd/oOvuPIOVHkDWeO1Nnywoc6bxuIJ7G506g== X-Received: by 2002:a17:902:fc4c:b0:207:4c7c:743b with SMTP id d9443c01a7336-2076d90a1aamr22272135ad.0.1726120551451; Wed, 11 Sep 2024 22:55:51 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe99b6sm7870465ad.209.2024.09.11.22.55.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 22:55:50 -0700 (PDT) From: Charlie Jenkins Date: Wed, 11 Sep 2024 22:55:11 -0700 Subject: [PATCH v10 03/14] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240911-xtheadvector-v10-3-8d3930091246@rivosinc.com> References: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> In-Reply-To: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Conor Dooley X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=960; i=charlie@rivosinc.com; h=from:subject:message-id; bh=twijwVNwXlRnqiWorC6lSyhzIHtshmEdOl4sTIAcK5Q=; b=owGbwMvMwCHWx5hUnlvL8Y3xtFoSQ9qjpqjdgupZ/AlK1Q7FNw/u1tnC9ORpXqpi78+DtXKPk 5uMNrJ2lLIwiHEwyIopsvBca2BuvaNfdlS0bALMHFYmkCEMXJwCMJG3rAz/VOd8nRK482XkT6UZ tYt2FjXdjPqi+VXavm/u3tKdInOD3zMyPI7n++V4VnP92xmlpRHdhfJLrru5Hwm1Pvs24Vmrmdc lDgA= X-Developer-Key: i=charlie@rivosinc.com; a=openpgp; fpr=7D834FF11B1D8387E61C776FFB10D1F27D6B1354 The D1/D1s SoCs support xtheadvector so it can be included in the devicetree. Also include vlenb for the cpu. Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boo= t/dts/allwinner/sun20i-d1s.dtsi index 64c3c2e6cbe0..6367112e614a 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -27,7 +27,8 @@ cpu0: cpu@0 { riscv,isa =3D "rv64imafdc"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr= ", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadvector"; + thead,vlenb =3D <128>; #cooling-cells =3D <2>; =20 cpu0_intc: interrupt-controller { --=20 2.45.0 From nobody Sat Nov 30 03:28:39 2024 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EC6318BC0D for ; Thu, 12 Sep 2024 05:55:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120556; cv=none; b=ukwC6/R4nQTPsGKkv8FzCedrpKOVJUcsLzLN9iJQTrGATtWfU66CRDKyNZDFy0ElnROGNFmTgIUeAUkaMlw5BZwj6NJymZjjAGIUtVItks8cnEGk4Ugkz9aS477WBXQro0WPcHtBGwyxlK7YWbUUJ9M+P5Ee4Sc3cBi+sc1ZAqI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120556; c=relaxed/simple; bh=7SdRVAdBMHX6BLgD+XlbPRIw5BjYE7igOjwZllEvap0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QpVuU1HZhA0+zBU6lmjp1IsTLATlboxcsJ58C49sae5zJlBu6QrGHj1n+2DvxnphtVwn8jw6zLQC2l8iSXhv63+ssQXeko5Rs0/+2spRshfrPH3CVFZiZYhSXg+sjKJMsxAMF+KepzlTzU7EzxzumzTRt7dlfveTlKccTDNckd0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=twpEa0Ej; arc=none smtp.client-ip=209.85.214.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="twpEa0Ej" Received: by mail-pl1-f182.google.com with SMTP id d9443c01a7336-20696938f86so4837555ad.3 for ; Wed, 11 Sep 2024 22:55:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1726120554; x=1726725354; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=viUMUU3u3LkA8a3hOJ7VlIwEHpNEEIfLA3woGK8oJNk=; b=twpEa0Ej4W5/7Pr7nYVKanxfvtT8j0RJJLmbsMhvew+W+F89Htyx0jgWuxFhAso+vb kdt257AIACKRWxfE3s1hI7l9n5Cy4LFzUD4QPg2jkZO6aF3Szpsa3g5/6QOKLsIGSazT kIHZCiZTG28aP9Y3k43s8bnnmPUouCAvXh0rc/Ksd8aHiqm5D1IWTdMYvl6eJ40I2Pju FzLNS1SvQn5cNn1QaRw2XB6VcvAJ67AudymQ63OotyXyf0uIOKgRDA7S1ZmWttYRXxku bSam27Xaj7nje5T5NLO4FX3o+OGO4PW96hR6ZCfRQLJd44doSF/JTRqCwMmJP0vjJpY6 m9mQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726120554; x=1726725354; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=viUMUU3u3LkA8a3hOJ7VlIwEHpNEEIfLA3woGK8oJNk=; b=cDq5tUVnLh9eiJMSen12mmmRlxye0PFtsm8uicR3iueb5eZ0O2O+GOgXvxeTt3/hj+ K0q3CoEZiIkBHIq4M+l3tKmpltmqxuz3WMy9aTYFTJkgtNf0C0fnyUlkWWEv5HuPmi8G IaKc2aD7TcqIH60zcJTHTV5W8YVXdLfrAX0qOioIY0g8q3xTcIERBslff9bGe94fHu4j NqKsuHLgaHgEXfcLoGx5+y9srKQjk+QsKN43UVAwvuN7i6dBy56PzIZtpSz2OMajv1o0 j4r+d8cbDTE3ZMdwX/vUFglNze16vvzvQxvQd+bz6nIKNnrZqzpIwagPiPsr3GqovkBs +ugg== X-Forwarded-Encrypted: i=1; AJvYcCU02WfyGzXHrPqPdrPFZrl8467IR8CTJr0zIz9nsG0aJMj1me27eZ6sUp+B2qXRRBhlAO8NXoIwL5u2thE=@vger.kernel.org X-Gm-Message-State: AOJu0YzQYHwlwgxSxXddQvud718JCMe7eoYO7VFBQ9M3tW9/unsbZ7on gva9R4czZPiRCuzpsl7W4mv964RI72oBLj6yiVW2t0fLj2ZMZetc4aWVMgYxGN0= X-Google-Smtp-Source: AGHT+IG5mpBm1eyHei4WmYfnPGCFrEapYSKJ0y8GMBu3Dp21gWH8FBOiebyWcvmarJnu/rAhe4XXlQ== X-Received: by 2002:a17:903:18b:b0:202:301f:36fd with SMTP id d9443c01a7336-2076e361277mr25777315ad.18.1726120553537; Wed, 11 Sep 2024 22:55:53 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe99b6sm7870465ad.209.2024.09.11.22.55.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 22:55:52 -0700 (PDT) From: Charlie Jenkins Date: Wed, 11 Sep 2024 22:55:12 -0700 Subject: [PATCH v10 04/14] riscv: Add thead and xtheadvector as a vendor extension Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240911-xtheadvector-v10-4-8d3930091246@rivosinc.com> References: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> In-Reply-To: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Conor Dooley X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5060; i=charlie@rivosinc.com; h=from:subject:message-id; bh=7SdRVAdBMHX6BLgD+XlbPRIw5BjYE7igOjwZllEvap0=; b=owGbwMvMwCHWx5hUnlvL8Y3xtFoSQ9qjpujKtEsuX0JT9H+cVk2rs/fJ5S47O7F57erJCd4yr tNq3M06SlkYxDgYZMUUWXiuNTC33tEvOypaNgFmDisTyBAGLk4BmAhbMCPDu8Swk5LesyMrmJvK zC1a+TtlFy+KXzrf6ohbRM5jp9/7GX6zr4toNCzybo09+t3n9+evN9w/7X2//u5Vg+vMlyMvat1 mBwA= X-Developer-Key: i=charlie@rivosinc.com; a=openpgp; fpr=7D834FF11B1D8387E61C776FFB10D1F27D6B1354 Add support to the kernel for THead vendor extensions with the target of the new extension xtheadvector. Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley --- arch/riscv/Kconfig.vendor | 13 +++++++++++++ arch/riscv/include/asm/vendor_extensions/thead.h | 16 ++++++++++++++++ arch/riscv/kernel/cpufeature.c | 1 + arch/riscv/kernel/vendor_extensions.c | 10 ++++++++++ arch/riscv/kernel/vendor_extensions/Makefile | 1 + arch/riscv/kernel/vendor_extensions/thead.c | 18 ++++++++++++++++++ 6 files changed, 59 insertions(+) diff --git a/arch/riscv/Kconfig.vendor b/arch/riscv/Kconfig.vendor index 6f1cdd32ed29..9897442bd44f 100644 --- a/arch/riscv/Kconfig.vendor +++ b/arch/riscv/Kconfig.vendor @@ -16,4 +16,17 @@ config RISCV_ISA_VENDOR_EXT_ANDES If you don't know what to do here, say Y. endmenu =20 +menu "T-Head" +config RISCV_ISA_VENDOR_EXT_THEAD + bool "T-Head vendor extension support" + select RISCV_ISA_VENDOR_EXT + default y + help + Say N here to disable detection of and support for all T-Head vendor + extensions. Without this option enabled, T-Head vendor extensions will + not be detected at boot and their presence not reported to userspace. + + If you don't know what to do here, say Y. +endmenu + endmenu diff --git a/arch/riscv/include/asm/vendor_extensions/thead.h b/arch/riscv/= include/asm/vendor_extensions/thead.h new file mode 100644 index 000000000000..48421d1553ad --- /dev/null +++ b/arch/riscv/include/asm/vendor_extensions/thead.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_H +#define _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_H + +#include + +#include + +/* + * Extension keys must be strictly less than RISCV_ISA_VENDOR_EXT_MAX. + */ +#define RISCV_ISA_VENDOR_EXT_XTHEADVECTOR 0 + +extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_the= ad; + +#endif diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 8f20607adb40..46e69b9d66a7 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -25,6 +25,7 @@ #include #include #include +#include =20 #define NUM_ALPHA_EXTS ('z' - 'a' + 1) =20 diff --git a/arch/riscv/kernel/vendor_extensions.c b/arch/riscv/kernel/vend= or_extensions.c index b6c1e7b5d34b..662ba64a8f93 100644 --- a/arch/riscv/kernel/vendor_extensions.c +++ b/arch/riscv/kernel/vendor_extensions.c @@ -6,6 +6,7 @@ #include #include #include +#include =20 #include #include @@ -14,6 +15,9 @@ struct riscv_isa_vendor_ext_data_list *riscv_isa_vendor_e= xt_list[] =3D { #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_ANDES &riscv_isa_vendor_ext_list_andes, #endif +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD + &riscv_isa_vendor_ext_list_thead, +#endif }; =20 const size_t riscv_isa_vendor_ext_list_size =3D ARRAY_SIZE(riscv_isa_vendo= r_ext_list); @@ -41,6 +45,12 @@ bool __riscv_isa_vendor_extension_available(int cpu, uns= igned long vendor, unsig cpu_bmap =3D &riscv_isa_vendor_ext_list_andes.per_hart_isa_bitmap[cpu]; break; #endif + #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD + case THEAD_VENDOR_ID: + bmap =3D &riscv_isa_vendor_ext_list_thead.all_harts_isa_bitmap; + cpu_bmap =3D &riscv_isa_vendor_ext_list_thead.per_hart_isa_bitmap[cpu]; + break; + #endif default: return false; } diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kern= el/vendor_extensions/Makefile index 6a61aed944f1..353522cb3bf0 100644 --- a/arch/riscv/kernel/vendor_extensions/Makefile +++ b/arch/riscv/kernel/vendor_extensions/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only =20 obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) +=3D andes.o +obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) +=3D thead.o diff --git a/arch/riscv/kernel/vendor_extensions/thead.c b/arch/riscv/kerne= l/vendor_extensions/thead.c new file mode 100644 index 000000000000..0f27baf8d245 --- /dev/null +++ b/arch/riscv/kernel/vendor_extensions/thead.c @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include + +#include +#include + +/* All T-Head vendor extensions supported in Linux */ +static const struct riscv_isa_ext_data riscv_isa_vendor_ext_thead[] =3D { + __RISCV_ISA_EXT_DATA(xtheadvector, RISCV_ISA_VENDOR_EXT_XTHEADVECTOR), +}; + +struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_thead =3D { + .ext_data_count =3D ARRAY_SIZE(riscv_isa_vendor_ext_thead), + .ext_data =3D riscv_isa_vendor_ext_thead, +}; --=20 2.45.0 From nobody Sat Nov 30 03:28:39 2024 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 778DF18BC36 for ; Thu, 12 Sep 2024 05:55:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120558; cv=none; b=eMZbqRlMdDj3xgpywnMw/Kp7G3DMF30/RCBi4h25qNvDyFaRir67vlpN/5srmpCmzmywIMVMNTd6gCEF4AtHUcxLYgCfF8t1jflIu1Oz3FBgyB4izqxAIeLEhRoKjcms8/B48hYbPdv4Gup3e+VXogrPM2ZvqfgRw02yifS+gbA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120558; c=relaxed/simple; bh=Si8s9Nyy7nI3HfPFfu+caaKSxmtxlVlOGIUcFmHJG5o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BSz43LSdlsYVXyBsh/HCLzeypocuhaFLk8+uuCQurZBji+Qmba45uZi+LTBa05tbSo877ozL5gibLfZTKBpBY0JfIyRZkAGxgTOsUdtPT5KlrR0b0iinIjqoDyGL+/5LfwkLCIO0YOvY6fQ+V2b0c4myKtbfPiyUHkI75PTk2ZU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=pgKVFKzu; arc=none smtp.client-ip=209.85.214.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="pgKVFKzu" Received: by mail-pl1-f173.google.com with SMTP id d9443c01a7336-20551e2f1f8so6097685ad.2 for ; Wed, 11 Sep 2024 22:55:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1726120556; x=1726725356; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=3U6ebKIucceyY9AucAMv99ftPt4/S1Gk1T6FLUdGq4U=; b=pgKVFKzu1Y13pP0wWJbHZU+Sw9WqyLYkVFNrxLjmgL0D2/7vPlaSD0OVVkiqIChMQw 6AZZxmWx8Jawktuq+42x05fScvuf8iO812Y/xIXIex484wETOff3W3ob9K+tOiHDfWnS j/1nvlOs8BpcQ8NpxSj3M2uGvGxiTxFFamrnxII3/Mzn3fIQNcPkWCKiG4WKVCOHTDsh 2+UdbrhSCGCJuDTOnAkJsZsm7Rr/RM1N9clrl+8HdjvTCC2THNYU9tGLoHsMvi/+b0VG CUliE3fk/HBMd5WxCqyNAvM5g7QoAAKNUnGvpy8nRXzsHKZKrPHHzq1vDAfdVKyCdEyv bKBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726120556; x=1726725356; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3U6ebKIucceyY9AucAMv99ftPt4/S1Gk1T6FLUdGq4U=; b=ZA37nHHboFQr2iKB1do7NzdJvZyW+PS0j7c6Ght++igjv00v+keayBKhU5ZpGGK4AV ThA6r6OgPNXAf38a7hSitoGjifuMI7lwD+puMu+yKeNtADJ3W0d4aka64uwRr7iAwY5F cu5eg/kwpOO3aCvaRujZCCfTs98M9/Y06qbrg9eE8afje7fV22umt+oovYTpNE6pZjqr 0ZxJWBQDXiVdAebYlrP6UDQQW3gN1l86jbDOLXyW8SAxDj4GU9vuEFgb9kHFOk49dazC 6bkpkHSevMAUfcpy+NPa8YWlT2R8ngGO2dq721QF+xtcrhLQGKWhrFnvjSDosRM89aKG tf+w== X-Forwarded-Encrypted: i=1; AJvYcCVoWRu12mlePjmW0gQH3u0os0lquoBKx7dZJ3VxqTmUVPtfGtHfLxl80JSJbZJbtwn8naj8hzRKVa3mKIA=@vger.kernel.org X-Gm-Message-State: AOJu0YwV5Qqnt5NaX5LGQwVt2Kz0pq4v4CdMg40uTvGaIOWQUvFC2zOu ThKmcwu/LbU9F0eZHzCVUGhfva7tcSn0YeHgXaVYv25rLj8EQPJUUlaUH0UVvxc= X-Google-Smtp-Source: AGHT+IFRxeLD4QYAfUciKWeOBA1Y00HNRbIfhwiZjz8ibwyk3mpAks+EyiDAbMA0V3a6X7tOGGPqzw== X-Received: by 2002:a17:902:da8a:b0:205:68a4:b2d9 with SMTP id d9443c01a7336-2076e4150famr25676065ad.48.1726120555786; Wed, 11 Sep 2024 22:55:55 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe99b6sm7870465ad.209.2024.09.11.22.55.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 22:55:54 -0700 (PDT) From: Charlie Jenkins Date: Wed, 11 Sep 2024 22:55:13 -0700 Subject: [PATCH v10 05/14] riscv: vector: Use vlenb from DT for thead Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240911-xtheadvector-v10-5-8d3930091246@rivosinc.com> References: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> In-Reply-To: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Conor Dooley X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6175; i=charlie@rivosinc.com; h=from:subject:message-id; bh=Si8s9Nyy7nI3HfPFfu+caaKSxmtxlVlOGIUcFmHJG5o=; b=owGbwMvMwCHWx5hUnlvL8Y3xtFoSQ9qjpmgZ0Z2rbxyvu7rkDsM2FrYDZc/3XNtW/bIzkXXxa YOd4p/aO0pZGMQ4GGTFFFl4rjUwt97RLzsqWjYBZg4rE8gQBi5OAZjIvmOMDC9OvLild+OW2g9d M4nfd1qZpn63td5cv3l5dvkRrXtsAkoM/4MOf938qyOCZ8ekFMEiyw8LJfkLX6/ctS1g5a1cxdh id04A X-Developer-Key: i=charlie@rivosinc.com; a=openpgp; fpr=7D834FF11B1D8387E61C776FFB10D1F27D6B1354 If thead,vlenb is provided in the device tree, prefer that over reading the vlenb csr. Signed-off-by: Charlie Jenkins Acked-by: Conor Dooley --- arch/riscv/Kconfig.vendor | 13 +++++++ arch/riscv/include/asm/cpufeature.h | 2 + arch/riscv/include/asm/vendor_extensions/thead.h | 6 +++ arch/riscv/kernel/cpufeature.c | 48 ++++++++++++++++++++= ++++ arch/riscv/kernel/vector.c | 12 +++++- arch/riscv/kernel/vendor_extensions/thead.c | 11 ++++++ 6 files changed, 91 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig.vendor b/arch/riscv/Kconfig.vendor index 9897442bd44f..b096548fe0ff 100644 --- a/arch/riscv/Kconfig.vendor +++ b/arch/riscv/Kconfig.vendor @@ -26,6 +26,19 @@ config RISCV_ISA_VENDOR_EXT_THEAD extensions. Without this option enabled, T-Head vendor extensions will not be detected at boot and their presence not reported to userspace. =20 + If you don't know what to do here, say Y. + +config RISCV_ISA_XTHEADVECTOR + bool "xtheadvector extension support" + depends on RISCV_ISA_VENDOR_EXT_THEAD + depends on RISCV_ISA_V + depends on FPU + default y + help + Say N here if you want to disable all xtheadvector related procedures + in the kernel. This will disable vector for any T-Head board that + contains xtheadvector rather than the standard vector. + If you don't know what to do here, say Y. endmenu =20 diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index 45f9c1171a48..28bdeb1005e0 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -31,6 +31,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); /* Per-cpu ISA extensions. */ extern struct riscv_isainfo hart_isa[NR_CPUS]; =20 +extern u32 thead_vlenb_of; + void riscv_user_isa_enable(void); =20 #define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size, _= validate) { \ diff --git a/arch/riscv/include/asm/vendor_extensions/thead.h b/arch/riscv/= include/asm/vendor_extensions/thead.h index 48421d1553ad..190c91e37e95 100644 --- a/arch/riscv/include/asm/vendor_extensions/thead.h +++ b/arch/riscv/include/asm/vendor_extensions/thead.h @@ -13,4 +13,10 @@ =20 extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_the= ad; =20 +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD +void disable_xtheadvector(void); +#else +void disable_xtheadvector(void) { } +#endif + #endif diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 46e69b9d66a7..9340efd79af9 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -37,6 +37,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __rea= d_mostly; /* Per-cpu ISA extensions. */ struct riscv_isainfo hart_isa[NR_CPUS]; =20 +u32 thead_vlenb_of; + /** * riscv_isa_extension_base() - Get base extension word * @@ -772,6 +774,46 @@ static void __init riscv_fill_vendor_ext_list(int cpu) } } =20 +static int has_thead_homogeneous_vlenb(void) +{ + int cpu; + u32 prev_vlenb =3D 0; + u32 vlenb; + + /* Ignore thead,vlenb property if xtheavector is not enabled in the kerne= l */ + if (!IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR)) + return 0; + + for_each_possible_cpu(cpu) { + struct device_node *cpu_node; + + cpu_node =3D of_cpu_device_node_get(cpu); + if (!cpu_node) { + pr_warn("Unable to find cpu node\n"); + return -ENOENT; + } + + if (of_property_read_u32(cpu_node, "thead,vlenb", &vlenb)) { + of_node_put(cpu_node); + + if (prev_vlenb) + return -ENOENT; + continue; + } + + if (prev_vlenb && vlenb !=3D prev_vlenb) { + of_node_put(cpu_node); + return -ENOENT; + } + + prev_vlenb =3D vlenb; + of_node_put(cpu_node); + } + + thead_vlenb_of =3D vlenb; + return 0; +} + static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) { unsigned int cpu; @@ -825,6 +867,12 @@ static int __init riscv_fill_hwcap_from_ext_list(unsig= ned long *isa2hwcap) riscv_fill_vendor_ext_list(cpu); } =20 + if (riscv_isa_vendor_extension_available(THEAD_VENDOR_ID, XTHEADVECTOR) && + has_thead_homogeneous_vlenb() < 0) { + pr_warn("Unsupported heterogeneous vlenb detected, vector extension disa= bled.\n"); + disable_xtheadvector(); + } + if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) return -ENOENT; =20 diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c index 682b3feee451..9775d6a9c8ee 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c @@ -33,7 +33,17 @@ int riscv_v_setup_vsize(void) { unsigned long this_vsize; =20 - /* There are 32 vector registers with vlenb length. */ + /* + * There are 32 vector registers with vlenb length. + * + * If the thead,vlenb property was provided by the firmware, use that + * instead of probing the CSRs. + */ + if (thead_vlenb_of) { + this_vsize =3D thead_vlenb_of * 32; + return 0; + } + riscv_v_enable(); this_vsize =3D csr_read(CSR_VLENB) * 32; riscv_v_disable(); diff --git a/arch/riscv/kernel/vendor_extensions/thead.c b/arch/riscv/kerne= l/vendor_extensions/thead.c index 0f27baf8d245..519dbf70710a 100644 --- a/arch/riscv/kernel/vendor_extensions/thead.c +++ b/arch/riscv/kernel/vendor_extensions/thead.c @@ -5,6 +5,7 @@ #include =20 #include +#include #include =20 /* All T-Head vendor extensions supported in Linux */ @@ -16,3 +17,13 @@ struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_e= xt_list_thead =3D { .ext_data_count =3D ARRAY_SIZE(riscv_isa_vendor_ext_thead), .ext_data =3D riscv_isa_vendor_ext_thead, }; + +void disable_xtheadvector(void) +{ + int cpu; + + for_each_possible_cpu(cpu) + clear_bit(RISCV_ISA_VENDOR_EXT_XTHEADVECTOR, riscv_isa_vendor_ext_list_t= head.per_hart_isa_bitmap[cpu].isa); + + clear_bit(RISCV_ISA_VENDOR_EXT_XTHEADVECTOR, riscv_isa_vendor_ext_list_th= ead.all_harts_isa_bitmap.isa); +} --=20 2.45.0 From nobody Sat Nov 30 03:28:39 2024 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8044113D8A8 for ; Thu, 12 Sep 2024 05:55:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120559; cv=none; b=kHQ+JGADFBXauxXsh/X2f6qwHiTq4/A+o55io1VEQaqqe07xFDyzzY5sDeKo+0m9kJc/oqNR0so338l5L33fS9oQlc7NB+SZxfjUCh9EL/QrHIJLk/FfdOG1I2urC6MQmZq9+Thw95BWfAxdBfwkXtXkrQmrxNAtxUHqask0mqI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120559; c=relaxed/simple; bh=/SkqORRprGraSlNdCA3N7P9uibYmHsQsfL3EwVWnJvg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=M+IX3e8g5Hajl9sotlSxRYXPwBhrtZExchLxgXrUVPO0v+cSMtLkq1WwSrF9wTcgqap90/zDpTFB34PND+ZW40NIr9f7NoLum6ojWyyzPkSY24RdF88U79/ILEccPGpIizwJepIBjn/1XwYwdu5h965qCdWTOgtDzUaF1PbS0kA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=MRWU5z6B; arc=none smtp.client-ip=209.85.214.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="MRWU5z6B" Received: by mail-pl1-f169.google.com with SMTP id d9443c01a7336-1fc47abc040so5868975ad.0 for ; Wed, 11 Sep 2024 22:55:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1726120558; x=1726725358; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=QC5zCLZI62pAjh3MZXl2DmzWweDYeenNtUhW+BVEweY=; b=MRWU5z6Br3fL+g+ubhPbJckpBT+ad+LTRiXRcqId48dwDaXwk2Fwm4WMu9dwkQAXiN c17/nV/1UDyOFZm2vUBIudctCd+9IJ2EjwPrYRFVDmqAHyzs8ahu/N3Su7Isb3Wifl6n umJu3J6+v8MvG2YW+5TcMrkU0IQ8QtzIFjqUgeioWAufFDvhbO+98TdEz50R2FIbg/gO P7Tmfi01e3cmgp/b3tf0e5r4mc7fIXlm90t8XiC3d9oq3oTQrERaC2hu28Id8zqxKxHC GflI3+QAH5VyLaMqsOxdRkpwz06pRFHUYarKsUVYmw4/W/MgndjYM7On2EU7RlfddPpZ QMTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726120558; x=1726725358; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QC5zCLZI62pAjh3MZXl2DmzWweDYeenNtUhW+BVEweY=; b=p0UZTUSI18xrDcK242CJMF4SlUoqasYG1taV6YDFIpy2QQmvpTmTjnFm2jVoveBJaJ OIlkqpRI32dwrjRjDcZZPk4LMYI6HgtKcMBYwvuelc5QarrSAnWjY3qYKlux4kIEs81K kRlJ0hY7quwbMzDm09slNq+iWAIN3tjrhTuckaGeGtwLMyDw0PkkQGl7uDnllBCBkRKf Bm6NPep7HCs9td4qj8A0psIOzYLJKq7e2SKndw+ZbIadoh+AHVG7Pt2O9Jxpv1eeX1sa eX6zzhEZc4dcn9aQA/dkUvxvhWNdm8b2O/LXrBXZISgl6azemf3rASsz0o0P5glCSsau dWWA== X-Forwarded-Encrypted: i=1; AJvYcCWPeWwKaK+/nKrZU04OPfndhc6kyKB3TMvXnDYjngBtmfLuQKoWhGfjofUuRak0pMqidzmc6xPLcpl3S4I=@vger.kernel.org X-Gm-Message-State: AOJu0YywF/GwUqjSuex+Nk2ArxNm4Z9B6roQBRgSgPrJbklh+dPFN4Es yqTmn/oEkVx5aJpjEY3lFdN3FLuQI/5r+7Btr0E21GjvEivOVEUCCdywEHM93Fs= X-Google-Smtp-Source: AGHT+IGyDCzQZjkQHkJXtnWNtioMB6ctq+/3Xni39dhHW8vmk0vcTDkokS2omVuMqKCmz0Pis2iBfg== X-Received: by 2002:a17:902:d50c:b0:207:1708:734c with SMTP id d9443c01a7336-2076e31f979mr25362825ad.11.1726120557914; Wed, 11 Sep 2024 22:55:57 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe99b6sm7870465ad.209.2024.09.11.22.55.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 22:55:57 -0700 (PDT) From: Charlie Jenkins Date: Wed, 11 Sep 2024 22:55:14 -0700 Subject: [PATCH v10 06/14] RISC-V: define the elements of the VCSR vector CSR Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240911-xtheadvector-v10-6-8d3930091246@rivosinc.com> References: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> In-Reply-To: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Heiko Stuebner , Conor Dooley , Heiko Stuebner X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=930; i=charlie@rivosinc.com; h=from:subject:message-id; bh=DIdTxrF0tPCTSVf2TD2d8xS0VDMxpxf73XTxU8DNXFU=; b=owGbwMvMwCHWx5hUnlvL8Y3xtFoSQ9qjpmjOUPYZ0uVTnX69zzU2OC36c3lXu8jeU+emTV3HF sS2tzW5o5SFQYyDQVZMkYXnWgNz6x39sqOiZRNg5rAygQxh4OIUgImUnGb4H/6mcBlT+5PDddcq mEIs/EWF7tvNM/wy2bNfgf/E2QyRCEaGKRJ9P6slZRemCE29I+349qW70NMJUx7HqUctlvt859w 2JgA= X-Developer-Key: i=charlie@rivosinc.com; a=openpgp; fpr=7D834FF11B1D8387E61C776FFB10D1F27D6B1354 From: Heiko Stuebner The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0]. Define constants for those to access the elements in a readable way. Acked-by: Guo Ren Reviewed-by: Conor Dooley Signed-off-by: Heiko Stuebner Signed-off-by: Charlie Jenkins Reviewed-by: Andy Chiu --- arch/riscv/include/asm/csr.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 25966995da04..3eeb07d73065 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -300,6 +300,10 @@ #define CSR_STIMECMP 0x14D #define CSR_STIMECMPH 0x15D =20 +#define VCSR_VXRM_MASK 3 +#define VCSR_VXRM_SHIFT 1 +#define VCSR_VXSAT_MASK 1 + /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ #define CSR_SISELECT 0x150 #define CSR_SIREG 0x151 --=20 2.45.0 From nobody Sat Nov 30 03:28:39 2024 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF94A18E036 for ; Thu, 12 Sep 2024 05:56:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120563; cv=none; b=gYWRBREoTHQp9hf9I4spwPhQ3Z5F739EPytmfCks2Xw8P8Vp7HlbQ5xBWFUuChGM0haE1FPCnJWUFkgPa7SmXc+MQJMtsKJsZCvbZV7/zjZ3BCbomOA5kERWtyLcL4G45XQ0QZWnH1/4ex8wRBy95MWQrn13QvWeTGg9hr+17bc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120563; c=relaxed/simple; bh=M4fQyJxhZ7NtPnQCPQfoncg1fbWtYe6qmsOGHrd6z/g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tpCq/Mk2ONKXSWlpRO+9Ak6yfRc5EuWOdj8bvt92RdKwFuilrdnA5wBxkR6Ge3TjKexDJMZ2LtgHQY0AbzRpTQ+p72s0A2+Uwlk4bp7Y2Wm8cbNIvEo4Y9TH44m+MTtcYcDQRWr4BT/5vhiV6324HVq/H7R3c6fxBXc9oiCppCA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=q38/obtw; arc=none smtp.client-ip=209.85.214.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="q38/obtw" Received: by mail-pl1-f173.google.com with SMTP id d9443c01a7336-2054e22ce3fso6441755ad.2 for ; Wed, 11 Sep 2024 22:56:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1726120560; x=1726725360; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=I6vSC44jl4CdBSHHJd2q6Sf8U8Y24j++yUJmo2Jtjkw=; b=q38/obtwjk/92IvamvOzYbfLFFwqngpL5DqSBnxyZT3w+R/9m0DhkmUdNg2tkiM0bE n1HWVl2ZpcO8We/ywkE7i5WaawoFJuDG9Zzg2F5Zcr5/+6wWpn5c6p8forBTYlQwqOdw MnXSLo8p+XkhSE5ZdFwTzvQhnd17TI+EBNv5bgdHh4p8PmPTbIwyX9dTzXzrNrZRXBp5 1u9RfJD1J/bCNX+CrOocILqSTJ3wECfWcFr84TZz5lQ+vVkXVNoojpzCE/8GihqrH6Ms vO7p48KE+egPlj7c49wSajjwdC95kXzbn7Oksv6s0Xs/YJYjIZUzMkvskiAjBtQHmk9B oZWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726120560; x=1726725360; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I6vSC44jl4CdBSHHJd2q6Sf8U8Y24j++yUJmo2Jtjkw=; b=B3VEbSG7LuWDzTWN17VAuTvtv+Ht8jLw/dM43FnNrOnKU0whiohpzzfhd+DZMitXqn c8DsxHJQ1LCiJn6NJVcFG2l8Xm6bDCHq7YoofMMI4HxF7VkksIW41agsPqKrzueK63Kq vEDWwTE3bk9TTIK0zVKgRGnsj8Bxu1How2CXkoOnIqciyuVHJ56ZgGp+vkto7Y4oUVB1 ZcBzjjH8pFGZA1CcHN7LQ/qXb0/tj5qQp67TW24tx4ClXPWKaHRw28nzaIFgiuru1Esu 2nbYX1xThVnSIRq8pq77e701BqCd8K6O7KQnR6I/uHf1clokfFoVgiXBWd3POoqdpT+f a+Ng== X-Forwarded-Encrypted: i=1; AJvYcCXC/suJIUU6Zbd7CsQuE2ztP2N8yUuDQbmTOGrGhV/xr47ZC3YiOZXhiWUyH3UUd0ThluQhhulvEvZxqYU=@vger.kernel.org X-Gm-Message-State: AOJu0YwE3RAywS4JCtvs9gd+0X0yaRDQCVnbkHUcrum/TVUJt/F4McF0 Cev9z6upFb5yAlCKyIW6LoVFQK+gqBFmljUkE+LTuwuWNXf8ZY1D4t9zQnbIFAM= X-Google-Smtp-Source: AGHT+IEPAuMTwq96E1itGrD7jktU/8wAEcvnLz9ajoH5Z6N4peyxFR/uYKlbWT48re/ej30oK7FXSQ== X-Received: by 2002:a17:902:e5c8:b0:1fc:2e38:d3de with SMTP id d9443c01a7336-2076e315577mr29117125ad.7.1726120560046; Wed, 11 Sep 2024 22:56:00 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe99b6sm7870465ad.209.2024.09.11.22.55.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 22:55:59 -0700 (PDT) From: Charlie Jenkins Date: Wed, 11 Sep 2024 22:55:15 -0700 Subject: [PATCH v10 07/14] riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240911-xtheadvector-v10-7-8d3930091246@rivosinc.com> References: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> In-Reply-To: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Heiko Stuebner X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1045; i=charlie@rivosinc.com; h=from:subject:message-id; bh=M4fQyJxhZ7NtPnQCPQfoncg1fbWtYe6qmsOGHrd6z/g=; b=owGbwMvMwCHWx5hUnlvL8Y3xtFoSQ9qjpuhlprePJ7PoOP6JyDK7e+qIg/XFCBf7KI/47gTND TN8G390lLIwiHEwyIopsvBca2BuvaNfdlS0bALMHFYmkCEMXJwCMJEfWowMk5Qyeb/kX3u0ViT3 QPelJQcOT96xynnJ0UM/uh1TPXavXszwP/L3LxeW9v9MaQ4WD9lfbH0/QXhWmvC5Gj1PfmMujgI NZgA= X-Developer-Key: i=charlie@rivosinc.com; a=openpgp; fpr=7D834FF11B1D8387E61C776FFB10D1F27D6B1354 The VXRM vector csr for xtheadvector has an encoding of 0xa and VXSAT has an encoding of 0x9. Co-developed-by: Heiko Stuebner Signed-off-by: Heiko Stuebner Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/csr.h | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 3eeb07d73065..c0a60c4ed911 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -300,9 +300,14 @@ #define CSR_STIMECMP 0x14D #define CSR_STIMECMPH 0x15D =20 -#define VCSR_VXRM_MASK 3 -#define VCSR_VXRM_SHIFT 1 -#define VCSR_VXSAT_MASK 1 +/* xtheadvector symbolic CSR names */ +#define CSR_VXSAT 0x9 +#define CSR_VXRM 0xa + +/* xtheadvector CSR masks */ +#define CSR_VXRM_MASK 3 +#define CSR_VXRM_SHIFT 1 +#define CSR_VXSAT_MASK 1 =20 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ #define CSR_SISELECT 0x150 --=20 2.45.0 From nobody Sat Nov 30 03:28:39 2024 Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3EBF18E047 for ; Thu, 12 Sep 2024 05:56:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120564; cv=none; b=I20ap8QKyUFRUeip6sNLm3OA3AP8+2faOofoowqdnlU4SkcA/dnYfDjg3NCk2mo8MLO3oPObOjsNgCsBTM4Gl4bejfFcQw2Krd/bWBMub6lVLdfCMMKM65A/r3Y0qBc4koHWfZwD0K6a7L2xmBQ6IiDzLUk52nVhE6bJH4B9vTY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120564; c=relaxed/simple; bh=JFu+LGCqiNnapZxee6sXBtAHc3I5ntU7jWhjkky+nXI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uqgktNSz9cS3z9tVbqF/4xHKnJTCf1mTFqvtpT3pCFkMyZHEmB8QBIZboApER1j1GLhKhBfCFvml7dj8Ew28vSGeM2HJ9yrC2W0EwIBGAEU2a9e/B1aSA68/lRSaTyeMdnEsN/3P4gNF4Ezt6eTU/4Up7WyK/7ToyQoL44DzqvQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=XQID2+2i; arc=none smtp.client-ip=209.85.214.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="XQID2+2i" Received: by mail-pl1-f174.google.com with SMTP id d9443c01a7336-20570b42f24so6799985ad.1 for ; Wed, 11 Sep 2024 22:56:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1726120562; x=1726725362; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=GSL6WjjHpdqYO1H/eXwGFHcRmPD/KtF7kVjlnnuCHwE=; b=XQID2+2iDlpDoWrxUm9TtXaBJZoIRu2TwsndyeKz3M/gJvUfR8NTYXkrhgZmLRj1Xe /GqpQl5jD3wiih/86Ij3Yq6A6oPm0IhzmfrjAcizor8R1CyFO8LziG12kXzHBm0VQhTp +VslEWtmNlGudHfScT4mUvsGsh68TT3IwWQn5yXA3K6uF/IRJMf9xkSN4SWTRbCQY9pL cNyy9qVAl3FjT3bXHLd5NuqsLF/ngQLzKDhFFBYFjU2pw0enpCswDOV1RC1O8oDbAwUs tlhFSLG3WskMEU1OcFFLkiNxKkwugDDCmc6avfnlNMTrlAzaCoj+rF2l2hmkqHDi+1bV N4DQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726120562; x=1726725362; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GSL6WjjHpdqYO1H/eXwGFHcRmPD/KtF7kVjlnnuCHwE=; b=l8ZAfkBQqFpyCKGbGar5VERhwA6Icra+3lnRaU05e5Pm1Gw06o91z/YNK+SW0EQFDF 1kSzVHr5H+puDcxinmQCM81rZa5KwHQA0aR4HPkdDasgHeyU9Av0B9HaduKhF9zVWk79 jUN01V9ICabxk6gfNAo1cVnU6L92kQMb9vpjTdMN7vD+9x7ia002xWSDIj+PvJhTzTAB OMe/wRCYU9nHbNMG8bA4isSVNe33wCtvHM5LSrE850UH8u1ywbc6hbB8XGI6LWqbiDWc JuRzuL2Uxxl/jm0amBeeG9j62x0+3HU6r7Ekyg/MH5wi8VY0pMAcS6A9I8niYlWlb6NB YNyg== X-Forwarded-Encrypted: i=1; AJvYcCXjlAjTD+SqNfPnwQM7kTBaYh5oQCaY70aEevmELs8/XM4i2yl4ov0DnziyTbQewTImu+W82bee1mDU99A=@vger.kernel.org X-Gm-Message-State: AOJu0Ywp27UXKQRad0d/j/nkxUm/0/gfmThlcfBo7rN3Sp2YeL3Rk3wx gZMXoScxUM2mwkFxTWrkZnaDfvR0ONGhH2NMRSu1DbE0zVMZ811MHK9jg/VDlEo= X-Google-Smtp-Source: AGHT+IECLV4z5WDlwOdbMshxCcr9zLYBzDjXvcLIsnzDjItc5dYHcznYBe2fAYb+H9t8yei2s9bchw== X-Received: by 2002:a17:902:e94d:b0:205:5f36:ffa0 with SMTP id d9443c01a7336-2076e393a75mr23890435ad.35.1726120562132; Wed, 11 Sep 2024 22:56:02 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe99b6sm7870465ad.209.2024.09.11.22.56.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 22:56:01 -0700 (PDT) From: Charlie Jenkins Date: Wed, 11 Sep 2024 22:55:16 -0700 Subject: [PATCH v10 08/14] riscv: Add xtheadvector instruction definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240911-xtheadvector-v10-8-8d3930091246@rivosinc.com> References: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> In-Reply-To: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Heiko Stuebner X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1954; i=charlie@rivosinc.com; h=from:subject:message-id; bh=JFu+LGCqiNnapZxee6sXBtAHc3I5ntU7jWhjkky+nXI=; b=owGbwMvMwCHWx5hUnlvL8Y3xtFoSQ9qjppjtbE1Gn1/GLT7Y32OjauP5VlT7/OyP+W09k2cLq n7awmDcUcrCIMbBICumyMJzrYG59Y5+2VHRsgkwc1iZQIYwcHEKwEQYyhj+Z6bdPced43yXUW6D orbittf5dpOX+Kz9zpP0a76w9fHN7Qz/dA4YC3+u/hnRdmNK36wKUf6il72pz5yflxyZyXomrly LDwA= X-Developer-Key: i=charlie@rivosinc.com; a=openpgp; fpr=7D834FF11B1D8387E61C776FFB10D1F27D6B1354 xtheadvector uses different encodings than standard vector for vsetvli and vector loads/stores. Write the instruction formats to be used in assembly code. Co-developed-by: Heiko Stuebner Signed-off-by: Heiko Stuebner Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/vendor_extensions/thead.h | 26 ++++++++++++++++++++= ++++ 1 file changed, 26 insertions(+) diff --git a/arch/riscv/include/asm/vendor_extensions/thead.h b/arch/riscv/= include/asm/vendor_extensions/thead.h index 190c91e37e95..118aa0f82c82 100644 --- a/arch/riscv/include/asm/vendor_extensions/thead.h +++ b/arch/riscv/include/asm/vendor_extensions/thead.h @@ -19,4 +19,30 @@ void disable_xtheadvector(void); void disable_xtheadvector(void) { } #endif =20 +/* Extension specific helpers */ + +/* + * Vector 0.7.1 as used for example on T-Head Xuantie cores, uses an older + * encoding for vsetvli (ta, ma vs. d1), so provide an instruction for + * vsetvli t4, x0, e8, m8, d1 + */ +#define THEAD_VSETVLI_T4X0E8M8D1 ".long 0x00307ed7\n\t" +#define THEAD_VSETVLI_X0X0E8M8D1 ".long 0x00307057\n\t" + +/* + * While in theory, the vector-0.7.1 vsb.v and vlb.v result in the same + * encoding as the standard vse8.v and vle8.v, compilers seem to optimize + * the call resulting in a different encoding and then using a value for + * the "mop" field that is not part of vector-0.7.1 + * So encode specific variants for vstate_save and _restore. + */ +#define THEAD_VSB_V_V0T0 ".long 0x02028027\n\t" +#define THEAD_VSB_V_V8T0 ".long 0x02028427\n\t" +#define THEAD_VSB_V_V16T0 ".long 0x02028827\n\t" +#define THEAD_VSB_V_V24T0 ".long 0x02028c27\n\t" +#define THEAD_VLB_V_V0T0 ".long 0x012028007\n\t" +#define THEAD_VLB_V_V8T0 ".long 0x012028407\n\t" +#define THEAD_VLB_V_V16T0 ".long 0x012028807\n\t" +#define THEAD_VLB_V_V24T0 ".long 0x012028c07\n\t" + #endif --=20 2.45.0 From nobody Sat Nov 30 03:28:39 2024 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A28818FDD8 for ; Thu, 12 Sep 2024 05:56:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120567; cv=none; b=lshI+XLr2X1lpipEeeuLfF2ZY8kwByfSIUTBKjwb5GAs6ojCAJyvuWncI5mkKckfA7QzZXnm4q5xjPEjw0A/E3IxxWq0XuZDzs2NwcKsDM3rzlsHPQ0ylR4tjjbZui/QeqaD1mgbn7S8YEleCGYB6v8g4/JU8ms8+tGc06IOeQk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120567; c=relaxed/simple; bh=KXMK7KbCXxiiC9xFyQBSs0qvxVZEtx4HxJkajVMHJeM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Te7I9NGynnYDtttAdajvgR9819W1UQHAxS7IQyZobtUTZjA+R7i7YM8M/f4Blv9BNPR63XRvaWo74gNUEQiF8bWa0l7wn74h+MTRgNKSI6kCIyqDTkstr2JRtpqYK3d82e5oHa3kkOPkrWCKD3+85romwaXj14bEhpMnW5El4WU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=bRe1ZQo5; arc=none smtp.client-ip=209.85.214.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="bRe1ZQo5" Received: by mail-pl1-f176.google.com with SMTP id d9443c01a7336-20543fdb7acso4850125ad.1 for ; Wed, 11 Sep 2024 22:56:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1726120564; x=1726725364; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=J2Ah96/8ONM6MIAUxtwGiEu7xgp2rf5KDsot5Xq3WII=; b=bRe1ZQo5ycmBhL5KaBg0mY6M2BRBTSqXZml5ShIvUYnrn+VilLCMORJRO25N9O9UV1 WIpq7iYmoP1XCw5yDnyJrNxGtYZHfprTbclYdIZUh7DPiztfIJyQx/rMU2nw9OVKwyio berMANFJWRzQqK5VCXvc+kXyS+HLWMKfwshRCHPclC1GaKqW1IHbGZ/Vdf8zW7hfetvy GuklEov3nuyln+feHYxcaXnQZHbrDNZY+QzIr8NVcwZ7d3SiLvkwhpKkD9xv2Df38YoX zlXhK3Ad6Dg6ZzuI/n/q9eW/VNlOreak4lX64X05kpLcQ3oF53UHWP40We4sj5usE9Pd GUjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726120564; x=1726725364; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J2Ah96/8ONM6MIAUxtwGiEu7xgp2rf5KDsot5Xq3WII=; b=s6LLejoq5KONaOPRglnbbj1giAZN1SVC8AgjoPDpdsMfoCL1FHHGBmskVU62wPcXpr 463xiG6aw0Mt47GjpFL36UoUDqthppjQIA4PE/wV8wvX4RpcE2dFVLtwydAAVO5/tHid zjZ58jWRohU70/rC+7ku4tPiff19gJAQycT9tQ8Lhvxxq/W8it2WMbbe3rvd5H5CzVDT CIVppDc7u+yPbBON60bj+2H8WaBel/BjY5qFiBsU0KH9O4HVZdQ2YBrQ6doZYUHEEN6D qtoO5+yYY1hKxOkG7+IpCoG1LeVOn7v2DuIFbZAyLIKeDr/GktcQwaSPFRd3zqYkxXDH t6Gg== X-Forwarded-Encrypted: i=1; AJvYcCW4gnkwymPXLwleBgV+Th4BMgLmMh+XoMlEDPNrE5+mABBMImpc2NQozftKwLrZcS3UyKRlNNkCQ4BmWAA=@vger.kernel.org X-Gm-Message-State: AOJu0YyGGOL0S+YSNGVcszP9+uL6I/fN/WHeyB1TvGcf5AwR0ynt/+e3 gfV071wVck6un8XeqJ/JwZPo/lvJNA99fUKzSXyJr5tsjDJjNCVBLAbrZMMrwNs= X-Google-Smtp-Source: AGHT+IGNGp4kbihpikoba7PnYpbIf38vrPY1Wy4j5dh6aJyjCGXFk0RVUVCjwCGGB26WutgEF1iy+A== X-Received: by 2002:a17:903:41d1:b0:206:d6ac:854f with SMTP id d9443c01a7336-2076e3157aemr25856935ad.3.1726120564237; Wed, 11 Sep 2024 22:56:04 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe99b6sm7870465ad.209.2024.09.11.22.56.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 22:56:03 -0700 (PDT) From: Charlie Jenkins Date: Wed, 11 Sep 2024 22:55:17 -0700 Subject: [PATCH v10 09/14] riscv: vector: Support xtheadvector save/restore Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240911-xtheadvector-v10-9-8d3930091246@rivosinc.com> References: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> In-Reply-To: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Conor Dooley X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=19197; i=charlie@rivosinc.com; h=from:subject:message-id; bh=KXMK7KbCXxiiC9xFyQBSs0qvxVZEtx4HxJkajVMHJeM=; b=owGbwMvMwCHWx5hUnlvL8Y3xtFoSQ9qjppia8x56f11vi+ytM3l/X2LBy/69TbObHW/8OV3uN /uLpN2xjlIWBjEOBlkxRRaeaw3MrXf0y46Klk2AmcPKBDKEgYtTACZS/J3hN2u2Io+M//rDlrvy ly+LDlnBt6vhlFvH9IMTJqScdw1UWczIMFHYm3mtxKXKByIPTnuVnDYVatR49cLHbbLt0+4pSiG MHAA= X-Developer-Key: i=charlie@rivosinc.com; a=openpgp; fpr=7D834FF11B1D8387E61C776FFB10D1F27D6B1354 Use alternatives to add support for xtheadvector vector save/restore routines. Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley Reviewed-by: Andy Chiu --- arch/riscv/include/asm/csr.h | 6 + arch/riscv/include/asm/switch_to.h | 2 +- arch/riscv/include/asm/vector.h | 225 +++++++++++++++++++++++++----= ---- arch/riscv/kernel/cpufeature.c | 6 +- arch/riscv/kernel/kernel_mode_vector.c | 8 +- arch/riscv/kernel/process.c | 4 +- arch/riscv/kernel/signal.c | 6 +- arch/riscv/kernel/vector.c | 12 +- 8 files changed, 200 insertions(+), 69 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index c0a60c4ed911..b4b3fcb1d142 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -30,6 +30,12 @@ #define SR_VS_CLEAN _AC(0x00000400, UL) #define SR_VS_DIRTY _AC(0x00000600, UL) =20 +#define SR_VS_THEAD _AC(0x01800000, UL) /* xtheadvector Status */ +#define SR_VS_OFF_THEAD _AC(0x00000000, UL) +#define SR_VS_INITIAL_THEAD _AC(0x00800000, UL) +#define SR_VS_CLEAN_THEAD _AC(0x01000000, UL) +#define SR_VS_DIRTY_THEAD _AC(0x01800000, UL) + #define SR_XS _AC(0x00018000, UL) /* Extension Status */ #define SR_XS_OFF _AC(0x00000000, UL) #define SR_XS_INITIAL _AC(0x00008000, UL) diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index 7594df37cc9f..f9cbebe372b8 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -99,7 +99,7 @@ do { \ __set_prev_cpu(__prev->thread); \ if (has_fpu()) \ __switch_to_fpu(__prev, __next); \ - if (has_vector()) \ + if (has_vector() || has_xtheadvector()) \ __switch_to_vector(__prev, __next); \ if (switch_to_should_flush_icache(__next)) \ local_flush_icache_all(); \ diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vecto= r.h index be7d309cca8a..6fd05efc6837 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -18,6 +18,27 @@ #include #include #include +#include +#include +#include + +#define __riscv_v_vstate_or(_val, TYPE) ({ \ + typeof(_val) _res =3D _val; \ + if (has_xtheadvector()) \ + _res =3D (_res & ~SR_VS_THEAD) | SR_VS_##TYPE##_THEAD; \ + else \ + _res =3D (_res & ~SR_VS) | SR_VS_##TYPE; \ + _res; \ +}) + +#define __riscv_v_vstate_check(_val, TYPE) ({ \ + bool _res; \ + if (has_xtheadvector()) \ + _res =3D ((_val) & SR_VS_THEAD) =3D=3D SR_VS_##TYPE##_THEAD; \ + else \ + _res =3D ((_val) & SR_VS) =3D=3D SR_VS_##TYPE; \ + _res; \ +}) =20 extern unsigned long riscv_v_vsize; int riscv_v_setup_vsize(void); @@ -40,39 +61,62 @@ static __always_inline bool has_vector(void) return riscv_has_extension_unlikely(RISCV_ISA_EXT_ZVE32X); } =20 +static __always_inline bool has_xtheadvector_no_alternatives(void) +{ + if (IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR)) + return riscv_isa_vendor_extension_available(THEAD_VENDOR_ID, XTHEADVECTO= R); + else + return false; +} + +static __always_inline bool has_xtheadvector(void) +{ + if (IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR)) + return riscv_has_vendor_extension_unlikely(THEAD_VENDOR_ID, + RISCV_ISA_VENDOR_EXT_XTHEADVECTOR); + else + return false; +} + static inline void __riscv_v_vstate_clean(struct pt_regs *regs) { - regs->status =3D (regs->status & ~SR_VS) | SR_VS_CLEAN; + regs->status =3D __riscv_v_vstate_or(regs->status, CLEAN); } =20 static inline void __riscv_v_vstate_dirty(struct pt_regs *regs) { - regs->status =3D (regs->status & ~SR_VS) | SR_VS_DIRTY; + regs->status =3D __riscv_v_vstate_or(regs->status, DIRTY); } =20 static inline void riscv_v_vstate_off(struct pt_regs *regs) { - regs->status =3D (regs->status & ~SR_VS) | SR_VS_OFF; + regs->status =3D __riscv_v_vstate_or(regs->status, OFF); } =20 static inline void riscv_v_vstate_on(struct pt_regs *regs) { - regs->status =3D (regs->status & ~SR_VS) | SR_VS_INITIAL; + regs->status =3D __riscv_v_vstate_or(regs->status, INITIAL); } =20 static inline bool riscv_v_vstate_query(struct pt_regs *regs) { - return (regs->status & SR_VS) !=3D 0; + return !__riscv_v_vstate_check(regs->status, OFF); } =20 static __always_inline void riscv_v_enable(void) { - csr_set(CSR_SSTATUS, SR_VS); + if (has_xtheadvector()) + csr_set(CSR_SSTATUS, SR_VS_THEAD); + else + csr_set(CSR_SSTATUS, SR_VS); } =20 static __always_inline void riscv_v_disable(void) { - csr_clear(CSR_SSTATUS, SR_VS); + if (has_xtheadvector()) + csr_clear(CSR_SSTATUS, SR_VS_THEAD); + else + csr_clear(CSR_SSTATUS, SR_VS); } =20 static __always_inline void __vstate_csr_save(struct __riscv_v_ext_state *= dest) @@ -81,10 +125,36 @@ static __always_inline void __vstate_csr_save(struct _= _riscv_v_ext_state *dest) "csrr %0, " __stringify(CSR_VSTART) "\n\t" "csrr %1, " __stringify(CSR_VTYPE) "\n\t" "csrr %2, " __stringify(CSR_VL) "\n\t" - "csrr %3, " __stringify(CSR_VCSR) "\n\t" - "csrr %4, " __stringify(CSR_VLENB) "\n\t" : "=3Dr" (dest->vstart), "=3Dr" (dest->vtype), "=3Dr" (dest->vl), - "=3Dr" (dest->vcsr), "=3Dr" (dest->vlenb) : :); + "=3Dr" (dest->vcsr) : :); + + if (has_xtheadvector()) { + unsigned long status; + + /* + * CSR_VCSR is defined as + * [2:1] - vxrm[1:0] + * [0] - vxsat + * The earlier vector spec implemented by T-Head uses separate + * registers for the same bit-elements, so just combine those + * into the existing output field. + * + * Additionally T-Head cores need FS to be enabled when accessing + * the VXRM and VXSAT CSRs, otherwise ending in illegal instructions. + * Though the cores do not implement the VXRM and VXSAT fields in the + * FCSR CSR that vector-0.7.1 specifies. + */ + status =3D csr_read_set(CSR_STATUS, SR_FS_DIRTY); + dest->vcsr =3D csr_read(CSR_VXSAT) | csr_read(CSR_VXRM) << CSR_VXRM_SHIF= T; + + dest->vlenb =3D riscv_v_vsize / 32; + + if ((status & SR_FS) !=3D SR_FS_DIRTY) + csr_write(CSR_STATUS, status); + } else { + dest->vcsr =3D csr_read(CSR_VCSR); + dest->vlenb =3D csr_read(CSR_VLENB); + } } =20 static __always_inline void __vstate_csr_restore(struct __riscv_v_ext_stat= e *src) @@ -95,9 +165,25 @@ static __always_inline void __vstate_csr_restore(struct= __riscv_v_ext_state *src "vsetvl x0, %2, %1\n\t" ".option pop\n\t" "csrw " __stringify(CSR_VSTART) ", %0\n\t" - "csrw " __stringify(CSR_VCSR) ", %3\n\t" - : : "r" (src->vstart), "r" (src->vtype), "r" (src->vl), - "r" (src->vcsr) :); + : : "r" (src->vstart), "r" (src->vtype), "r" (src->vl)); + + if (has_xtheadvector()) { + unsigned long status =3D csr_read(CSR_SSTATUS); + + /* + * Similar to __vstate_csr_save above, restore values for the + * separate VXRM and VXSAT CSRs from the vcsr variable. + */ + status =3D csr_read_set(CSR_STATUS, SR_FS_DIRTY); + + csr_write(CSR_VXRM, (src->vcsr >> CSR_VXRM_SHIFT) & CSR_VXRM_MASK); + csr_write(CSR_VXSAT, src->vcsr & CSR_VXSAT_MASK); + + if ((status & SR_FS) !=3D SR_FS_DIRTY) + csr_write(CSR_STATUS, status); + } else { + csr_write(CSR_VCSR, src->vcsr); + } } =20 static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_= to, @@ -107,19 +193,33 @@ static inline void __riscv_v_vstate_save(struct __ris= cv_v_ext_state *save_to, =20 riscv_v_enable(); __vstate_csr_save(save_to); - asm volatile ( - ".option push\n\t" - ".option arch, +zve32x\n\t" - "vsetvli %0, x0, e8, m8, ta, ma\n\t" - "vse8.v v0, (%1)\n\t" - "add %1, %1, %0\n\t" - "vse8.v v8, (%1)\n\t" - "add %1, %1, %0\n\t" - "vse8.v v16, (%1)\n\t" - "add %1, %1, %0\n\t" - "vse8.v v24, (%1)\n\t" - ".option pop\n\t" - : "=3D&r" (vl) : "r" (datap) : "memory"); + if (has_xtheadvector()) { + asm volatile ( + "mv t0, %0\n\t" + THEAD_VSETVLI_T4X0E8M8D1 + THEAD_VSB_V_V0T0 + "add t0, t0, t4\n\t" + THEAD_VSB_V_V0T0 + "add t0, t0, t4\n\t" + THEAD_VSB_V_V0T0 + "add t0, t0, t4\n\t" + THEAD_VSB_V_V0T0 + : : "r" (datap) : "memory", "t0", "t4"); + } else { + asm volatile ( + ".option push\n\t" + ".option arch, +zve32x\n\t" + "vsetvli %0, x0, e8, m8, ta, ma\n\t" + "vse8.v v0, (%1)\n\t" + "add %1, %1, %0\n\t" + "vse8.v v8, (%1)\n\t" + "add %1, %1, %0\n\t" + "vse8.v v16, (%1)\n\t" + "add %1, %1, %0\n\t" + "vse8.v v24, (%1)\n\t" + ".option pop\n\t" + : "=3D&r" (vl) : "r" (datap) : "memory"); + } riscv_v_disable(); } =20 @@ -129,28 +229,51 @@ static inline void __riscv_v_vstate_restore(struct __= riscv_v_ext_state *restore_ unsigned long vl; =20 riscv_v_enable(); - asm volatile ( - ".option push\n\t" - ".option arch, +zve32x\n\t" - "vsetvli %0, x0, e8, m8, ta, ma\n\t" - "vle8.v v0, (%1)\n\t" - "add %1, %1, %0\n\t" - "vle8.v v8, (%1)\n\t" - "add %1, %1, %0\n\t" - "vle8.v v16, (%1)\n\t" - "add %1, %1, %0\n\t" - "vle8.v v24, (%1)\n\t" - ".option pop\n\t" - : "=3D&r" (vl) : "r" (datap) : "memory"); + if (has_xtheadvector()) { + asm volatile ( + "mv t0, %0\n\t" + THEAD_VSETVLI_T4X0E8M8D1 + THEAD_VLB_V_V0T0 + "add t0, t0, t4\n\t" + THEAD_VLB_V_V0T0 + "add t0, t0, t4\n\t" + THEAD_VLB_V_V0T0 + "add t0, t0, t4\n\t" + THEAD_VLB_V_V0T0 + : : "r" (datap) : "memory", "t0", "t4"); + } else { + asm volatile ( + ".option push\n\t" + ".option arch, +zve32x\n\t" + "vsetvli %0, x0, e8, m8, ta, ma\n\t" + "vle8.v v0, (%1)\n\t" + "add %1, %1, %0\n\t" + "vle8.v v8, (%1)\n\t" + "add %1, %1, %0\n\t" + "vle8.v v16, (%1)\n\t" + "add %1, %1, %0\n\t" + "vle8.v v24, (%1)\n\t" + ".option pop\n\t" + : "=3D&r" (vl) : "r" (datap) : "memory"); + } __vstate_csr_restore(restore_from); riscv_v_disable(); } =20 static inline void __riscv_v_vstate_discard(void) { - unsigned long vl, vtype_inval =3D 1UL << (BITS_PER_LONG - 1); + unsigned long vtype_inval =3D 1UL << (BITS_PER_LONG - 1); =20 riscv_v_enable(); + if (has_xtheadvector()) + asm volatile (THEAD_VSETVLI_X0X0E8M8D1); + else + asm volatile ( + ".option push\n\t" + ".option arch, +v\n\t" + "vsetvli x0, x0, e8, m8, ta, ma\n\t" + ".option pop\n\t"); + asm volatile ( ".option push\n\t" ".option arch, +zve32x\n\t" @@ -159,25 +282,25 @@ static inline void __riscv_v_vstate_discard(void) "vmv.v.i v8, -1\n\t" "vmv.v.i v16, -1\n\t" "vmv.v.i v24, -1\n\t" - "vsetvl %0, x0, %1\n\t" + "vsetvl x0, x0, %0\n\t" ".option pop\n\t" - : "=3D&r" (vl) : "r" (vtype_inval) : "memory"); + : : "r" (vtype_inval)); + riscv_v_disable(); } =20 static inline void riscv_v_vstate_discard(struct pt_regs *regs) { - if ((regs->status & SR_VS) =3D=3D SR_VS_OFF) - return; - - __riscv_v_vstate_discard(); - __riscv_v_vstate_dirty(regs); + if (riscv_v_vstate_query(regs)) { + __riscv_v_vstate_discard(); + __riscv_v_vstate_dirty(regs); + } } =20 static inline void riscv_v_vstate_save(struct __riscv_v_ext_state *vstate, struct pt_regs *regs) { - if ((regs->status & SR_VS) =3D=3D SR_VS_DIRTY) { + if (__riscv_v_vstate_check(regs->status, DIRTY)) { __riscv_v_vstate_save(vstate, vstate->datap); __riscv_v_vstate_clean(regs); } @@ -186,7 +309,7 @@ static inline void riscv_v_vstate_save(struct __riscv_v= _ext_state *vstate, static inline void riscv_v_vstate_restore(struct __riscv_v_ext_state *vsta= te, struct pt_regs *regs) { - if ((regs->status & SR_VS) !=3D SR_VS_OFF) { + if (riscv_v_vstate_query(regs)) { __riscv_v_vstate_restore(vstate, vstate->datap); __riscv_v_vstate_clean(regs); } @@ -195,7 +318,7 @@ static inline void riscv_v_vstate_restore(struct __risc= v_v_ext_state *vstate, static inline void riscv_v_vstate_set_restore(struct task_struct *task, struct pt_regs *regs) { - if ((regs->status & SR_VS) !=3D SR_VS_OFF) { + if (riscv_v_vstate_query(regs)) { set_tsk_thread_flag(task, TIF_RISCV_V_DEFER_RESTORE); riscv_v_vstate_on(regs); } @@ -268,6 +391,8 @@ struct pt_regs; =20 static inline int riscv_v_setup_vsize(void) { return -EOPNOTSUPP; } static __always_inline bool has_vector(void) { return false; } +static __always_inline bool has_xtheadvector_no_alternatives(void) { retur= n false; } +static __always_inline bool has_xtheadvector(void) { return false; } static inline bool riscv_v_first_use_handler(struct pt_regs *regs) { retur= n false; } static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return fal= se; } static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; } diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 9340efd79af9..56b5054b8f86 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -867,8 +867,7 @@ static int __init riscv_fill_hwcap_from_ext_list(unsign= ed long *isa2hwcap) riscv_fill_vendor_ext_list(cpu); } =20 - if (riscv_isa_vendor_extension_available(THEAD_VENDOR_ID, XTHEADVECTOR) && - has_thead_homogeneous_vlenb() < 0) { + if (has_xtheadvector_no_alternatives() && has_thead_homogeneous_vlenb() <= 0) { pr_warn("Unsupported heterogeneous vlenb detected, vector extension disa= bled.\n"); disable_xtheadvector(); } @@ -925,7 +924,8 @@ void __init riscv_fill_hwcap(void) elf_hwcap &=3D ~COMPAT_HWCAP_ISA_F; } =20 - if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ZVE32X)) { + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ZVE32X) || + has_xtheadvector_no_alternatives()) { /* * This cannot fail when called on the boot hart */ diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/ker= nel_mode_vector.c index 6afe80c7f03a..99972a48e86b 100644 --- a/arch/riscv/kernel/kernel_mode_vector.c +++ b/arch/riscv/kernel/kernel_mode_vector.c @@ -143,7 +143,7 @@ static int riscv_v_start_kernel_context(bool *is_nested) =20 /* Transfer the ownership of V from user to kernel, then save */ riscv_v_start(RISCV_PREEMPT_V | RISCV_PREEMPT_V_DIRTY); - if ((task_pt_regs(current)->status & SR_VS) =3D=3D SR_VS_DIRTY) { + if (__riscv_v_vstate_check(task_pt_regs(current)->status, DIRTY)) { uvstate =3D ¤t->thread.vstate; __riscv_v_vstate_save(uvstate, uvstate->datap); } @@ -160,7 +160,7 @@ asmlinkage void riscv_v_context_nesting_start(struct pt= _regs *regs) return; =20 depth =3D riscv_v_ctx_get_depth(); - if (depth =3D=3D 0 && (regs->status & SR_VS) =3D=3D SR_VS_DIRTY) + if (depth =3D=3D 0 && __riscv_v_vstate_check(regs->status, DIRTY)) riscv_preempt_v_set_dirty(); =20 riscv_v_ctx_depth_inc(); @@ -208,7 +208,7 @@ void kernel_vector_begin(void) { bool nested =3D false; =20 - if (WARN_ON(!has_vector())) + if (WARN_ON(!(has_vector() || has_xtheadvector()))) return; =20 BUG_ON(!may_use_simd()); @@ -236,7 +236,7 @@ EXPORT_SYMBOL_GPL(kernel_vector_begin); */ void kernel_vector_end(void) { - if (WARN_ON(!has_vector())) + if (WARN_ON(!(has_vector() || has_xtheadvector()))) return; =20 riscv_v_disable(); diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index e4bc61c4e58a..191023decd16 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -176,7 +176,7 @@ void flush_thread(void) void arch_release_task_struct(struct task_struct *tsk) { /* Free the vector context of datap. */ - if (has_vector()) + if (has_vector() || has_xtheadvector()) riscv_v_thread_free(tsk); } =20 @@ -222,7 +222,7 @@ int copy_thread(struct task_struct *p, const struct ker= nel_clone_args *args) p->thread.s[0] =3D 0; } p->thread.riscv_v_flags =3D 0; - if (has_vector()) + if (has_vector() || has_xtheadvector()) riscv_v_thread_alloc(p); p->thread.ra =3D (unsigned long)ret_from_fork; p->thread.sp =3D (unsigned long)childregs; /* kernel sp */ diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index dcd282419456..94e905eea1de 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -189,7 +189,7 @@ static long restore_sigcontext(struct pt_regs *regs, =20 return 0; case RISCV_V_MAGIC: - if (!has_vector() || !riscv_v_vstate_query(regs) || + if (!(has_vector() || has_xtheadvector()) || !riscv_v_vstate_query(regs= ) || size !=3D riscv_v_sc_size) return -EINVAL; =20 @@ -211,7 +211,7 @@ static size_t get_rt_frame_size(bool cal_all) =20 frame_size =3D sizeof(*frame); =20 - if (has_vector()) { + if (has_vector() || has_xtheadvector()) { if (cal_all || riscv_v_vstate_query(task_pt_regs(current))) total_context_size +=3D riscv_v_sc_size; } @@ -284,7 +284,7 @@ static long setup_sigcontext(struct rt_sigframe __user = *frame, if (has_fpu()) err |=3D save_fp_state(regs, &sc->sc_fpregs); /* Save the vector state. */ - if (has_vector() && riscv_v_vstate_query(regs)) + if ((has_vector() || has_xtheadvector()) && riscv_v_vstate_query(regs)) err |=3D save_v_state(regs, (void __user **)&sc_ext_ptr); /* Write zero to fp-reserved space and check it on restore_sigcontext */ err |=3D __put_user(0, &sc->sc_extdesc.reserved); diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c index 9775d6a9c8ee..f3e1de574050 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c @@ -63,7 +63,7 @@ int riscv_v_setup_vsize(void) =20 void __init riscv_v_setup_ctx_cache(void) { - if (!has_vector()) + if (!(has_vector() || has_xtheadvector())) return; =20 riscv_v_user_cachep =3D kmem_cache_create_usercopy("riscv_vector_ctx", @@ -183,7 +183,7 @@ bool riscv_v_first_use_handler(struct pt_regs *regs) u32 __user *epc =3D (u32 __user *)regs->epc; u32 insn =3D (u32)regs->badaddr; =20 - if (!has_vector()) + if (!(has_vector() || has_xtheadvector())) return false; =20 /* Do not handle if V is not supported, or disabled */ @@ -226,7 +226,7 @@ void riscv_v_vstate_ctrl_init(struct task_struct *tsk) bool inherit; int cur, next; =20 - if (!has_vector()) + if (!(has_vector() || has_xtheadvector())) return; =20 next =3D riscv_v_ctrl_get_next(tsk); @@ -248,7 +248,7 @@ void riscv_v_vstate_ctrl_init(struct task_struct *tsk) =20 long riscv_v_vstate_ctrl_get_current(void) { - if (!has_vector()) + if (!(has_vector() || has_xtheadvector())) return -EINVAL; =20 return current->thread.vstate_ctrl & PR_RISCV_V_VSTATE_CTRL_MASK; @@ -259,7 +259,7 @@ long riscv_v_vstate_ctrl_set_current(unsigned long arg) bool inherit; int cur, next; =20 - if (!has_vector()) + if (!(has_vector() || has_xtheadvector())) return -EINVAL; =20 if (arg & ~PR_RISCV_V_VSTATE_CTRL_MASK) @@ -309,7 +309,7 @@ static struct ctl_table riscv_v_default_vstate_table[] = =3D { =20 static int __init riscv_v_sysctl_init(void) { - if (has_vector()) + if (has_vector() || has_xtheadvector()) if (!register_sysctl("abi", riscv_v_default_vstate_table)) return -EINVAL; return 0; --=20 2.45.0 From nobody Sat Nov 30 03:28:39 2024 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2184B19048C for ; Thu, 12 Sep 2024 05:56:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120568; cv=none; b=KC8CqonXyjO6xtvVLBxocvOyKK3oiK0QCTcf1VseTYKVO8bJoUmAJleHlbJJb99vLW6vbTyfb0AJpw0XCbnTVX5lcFwmSpulxkL0HSVUFOVRLfJaizjU/jURu8fC426pdAmrnlEjkQ7/HD3r4jxnsFP70tVFRHULHmslpKs9ooU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120568; c=relaxed/simple; bh=8kD/lDOSxQ4iVYaYEwxdpJh5wgIKszrhE4FEXnByLMs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=q2BPrWdlkXmBJ+Tu5UfbqY6FufsBLsXV/2B2MGcoVXCP66rZjarSFQZ3R+ex6VXjRWGXwiwQvU54znWb+RvmN80g3wF8xsMNFDAb9uUWaDm26aqhaCHgIpCg2d55zUXHDX0nTVqNQuTV0KLfdTYbRSv7q/UnlHEnnhCs/YACQGI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=B+Ul8UVa; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="B+Ul8UVa" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-2059112f0a7so5439635ad.3 for ; Wed, 11 Sep 2024 22:56:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1726120566; x=1726725366; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=D01ZlODzldl6pwLwzxaH5YS2gXfh7f2sIelDqEUUONI=; b=B+Ul8UVaS0SoycZtNQRQrHfGF82KhKdYa336Um3l49dvumY/JAImmXPegFR+TgSW+q PjMnu5NzzcaREU5OkBIGyhken/n6y8EVpSv5u0s1s3UdnKWLQ47pOjqrS7ql3jyAdwBK YDe9VtWXSoR9odA0ElLksmKFmiQlZSfo7m8nKpGNbopzbw1BLW+tnRC4woXvgraHklIz DF/upLxtGxDr5ocasPiRq0MJjEgBIeslrF1lgDEOOPaayagF7lujbW9HGTr4sYHV+9Jc c+X84rBHe8T3ebmulCE2UasgShPltnN1mh9Gl+FGHfhqVyluhzsrfwld76CBhNwqkWnr xadg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726120566; x=1726725366; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D01ZlODzldl6pwLwzxaH5YS2gXfh7f2sIelDqEUUONI=; b=UzDh3a0Y8KnkYSMq86pVBNN7CB7jqZHPOGi0WMqg+/L+5SnbC5pDGY5+hAIP+j6Gxm e/9hu/2xmh+/NPWQGzN584IQ0hZIt25jTv9/Hke3hAQY57iXVvFuZ60tEOdWJzhbf1+O Ai18Urwi13WTAW1IlEwX4ehXIrm7uLJb7+EjwSmt7zIooYFEOdpTBx5gj6Gg3RbN5dqs L9ic+CJMutq5ZjwaUgy23GxEOuObA8W5MDOByjUgukuvDEqsygjucTKwkVtsWQ4hLDAG PvlZjJI68lFDd9Fyz8MMT5SOgHSvqV2j72amK9WrmaUwnJuWH+hbKzZcr84B3g0t0HS2 JtQw== X-Forwarded-Encrypted: i=1; AJvYcCUKdjQeefdG/cUfakFgWhCzEZnqKEiRegdBxkICwhOVFLDJSjZ95kHEEU+XDqzAc9LBzeE71eyWmwKTW2Y=@vger.kernel.org X-Gm-Message-State: AOJu0YyspZENeU/U7gPfvmqRgKHBRwo1MJH/fTopeoYO18dfXqvW08yV bGhbbaCBRq0VTncC2PLROuyY0iJChEdAZkD4ArfzuNoeQoJ8/dzBzeYi4Nm01mg= X-Google-Smtp-Source: AGHT+IE8ZLfj1mhjATB0p3w65vw/xvykupYsUkaQ8UqZVsDf8hgCRU4vzyrpRG00oNWAqgf9kqoqdg== X-Received: by 2002:a17:903:234b:b0:203:a0c5:fcfd with SMTP id d9443c01a7336-2076e31c105mr27721755ad.3.1726120566254; Wed, 11 Sep 2024 22:56:06 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe99b6sm7870465ad.209.2024.09.11.22.56.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 22:56:05 -0700 (PDT) From: Charlie Jenkins Date: Wed, 11 Sep 2024 22:55:18 -0700 Subject: [PATCH v10 10/14] riscv: hwprobe: Add thead vendor extension probing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240911-xtheadvector-v10-10-8d3930091246@rivosinc.com> References: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> In-Reply-To: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=7365; i=charlie@rivosinc.com; h=from:subject:message-id; bh=8kD/lDOSxQ4iVYaYEwxdpJh5wgIKszrhE4FEXnByLMs=; b=owGbwMvMwCHWx5hUnlvL8Y3xtFoSQ9qjphinR4dOFwi9uK5xlWl6Qvr6VSGlLLVHklpYqv8t5 8r/q7yzo5SFQYyDQVZMkYXnWgNz6x39sqOiZRNg5rAygQxh4OIUgIl8vcPIcDi/n+FfEuu1Uyvt c83rZbL7dNIll/L9n2shzqgmUbWyhZFh8ULrwJmiYc1V+T9O5zy/NPuU/XeWrhkXr2fpmb6wffu bGwA= X-Developer-Key: i=charlie@rivosinc.com; a=openpgp; fpr=7D834FF11B1D8387E61C776FFB10D1F27D6B1354 Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0" which allows userspace to probe for the new RISCV_ISA_VENDOR_EXT_XTHEADVECTOR vendor extension. This new key will allow userspace code to probe for which thead vendor extensions are supported. This API is modeled to be consistent with RISCV_HWPROBE_KEY_IMA_EXT_0. The bitmask returned will have each bit corresponding to a supported thead vendor extension of the cpumask set. Just like RISCV_HWPROBE_KEY_IMA_EXT_0, this allows a userspace program to determine all of the supported thead vendor extensions in one call. Signed-off-by: Charlie Jenkins Reviewed-by: Evan Green --- arch/riscv/include/asm/hwprobe.h | 3 +- .../include/asm/vendor_extensions/thead_hwprobe.h | 19 +++++++++++ .../include/asm/vendor_extensions/vendor_hwprobe.h | 37 ++++++++++++++++++= ++++ arch/riscv/include/uapi/asm/hwprobe.h | 3 +- arch/riscv/include/uapi/asm/vendor/thead.h | 3 ++ arch/riscv/kernel/sys_hwprobe.c | 5 +++ arch/riscv/kernel/vendor_extensions/Makefile | 1 + .../riscv/kernel/vendor_extensions/thead_hwprobe.c | 19 +++++++++++ 8 files changed, 88 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwpr= obe.h index ef01c182af2b..6148e1eab64c 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* - * Copyright 2023 Rivos, Inc + * Copyright 2023-2024 Rivos, Inc */ =20 #ifndef _ASM_HWPROBE_H @@ -21,6 +21,7 @@ static inline bool hwprobe_key_is_bitmask(__s64 key) case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: case RISCV_HWPROBE_KEY_IMA_EXT_0: case RISCV_HWPROBE_KEY_CPUPERF_0: + case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0: return true; } =20 diff --git a/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h b/arc= h/riscv/include/asm/vendor_extensions/thead_hwprobe.h new file mode 100644 index 000000000000..65a9c5612466 --- /dev/null +++ b/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_HWPROBE_H +#define _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_HWPROBE_H + +#include + +#include + +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD +void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const stru= ct cpumask *cpus); +#else +static inline void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pa= ir, + const struct cpumask *cpus) +{ + pair->value =3D 0; +} +#endif + +#endif diff --git a/arch/riscv/include/asm/vendor_extensions/vendor_hwprobe.h b/ar= ch/riscv/include/asm/vendor_extensions/vendor_hwprobe.h new file mode 100644 index 000000000000..6b9293e984a9 --- /dev/null +++ b/arch/riscv/include/asm/vendor_extensions/vendor_hwprobe.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2024 Rivos, Inc + */ + +#ifndef _ASM_RISCV_SYS_HWPROBE_H +#define _ASM_RISCV_SYS_HWPROBE_H + +#include + +#define VENDOR_EXT_KEY(ext) \ + do { \ + if (__riscv_isa_extension_available(isainfo->isa, RISCV_ISA_VENDOR_EXT_#= #ext)) \ + pair->value |=3D RISCV_HWPROBE_VENDOR_EXT_##ext; \ + else \ + missing |=3D RISCV_HWPROBE_VENDOR_EXT_##ext; \ + } while (false) + +/* + * Loop through and record extensions that 1) anyone has, and 2) anyone + * doesn't have. + * + * _extension_checks is an arbitrary C block to set the values of pair->va= lue + * and missing. It should be filled with VENDOR_EXT_KEY expressions. + */ +#define VENDOR_EXTENSION_SUPPORTED(pair, cpus, per_hart_vendor_bitmap, _ex= tension_checks) \ + do { \ + int cpu; \ + u64 missing =3D 0; \ + for_each_cpu(cpu, (cpus)) { \ + struct riscv_isavendorinfo *isainfo =3D &(per_hart_vendor_bitmap)[cpu];= \ + _extension_checks \ + } \ + (pair)->value &=3D ~missing; \ + } while (false) \ + +#endif /* _ASM_RISCV_SYS_HWPROBE_H */ diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index b706c8e47b02..452d0b84f17f 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* - * Copyright 2023 Rivos, Inc + * Copyright 2023-2024 Rivos, Inc */ =20 #ifndef _UAPI_ASM_HWPROBE_H @@ -82,6 +82,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6 #define RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS 7 #define RISCV_HWPROBE_KEY_TIME_CSR_FREQ 8 +#define RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 9 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ =20 /* Flags */ diff --git a/arch/riscv/include/uapi/asm/vendor/thead.h b/arch/riscv/includ= e/uapi/asm/vendor/thead.h new file mode 100644 index 000000000000..43790ebe5faf --- /dev/null +++ b/arch/riscv/include/uapi/asm/vendor/thead.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ + +#define RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR (1 << 0) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprob= e.c index 8d1b5c35d2a7..5a3dc8e66c85 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -15,6 +15,7 @@ #include #include #include +#include #include =20 =20 @@ -241,6 +242,10 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pai= r, pair->value =3D riscv_timebase; break; =20 + case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0: + hwprobe_isa_vendor_ext_thead_0(pair, cpus); + break; + /* * For forward compatibility, unknown keys don't fail the whole * call, but get their element key set to -1 and value set to 0 diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kern= el/vendor_extensions/Makefile index 353522cb3bf0..866414c81a9f 100644 --- a/arch/riscv/kernel/vendor_extensions/Makefile +++ b/arch/riscv/kernel/vendor_extensions/Makefile @@ -2,3 +2,4 @@ =20 obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) +=3D andes.o obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) +=3D thead.o +obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) +=3D thead_hwprobe.o diff --git a/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c b/arch/ris= cv/kernel/vendor_extensions/thead_hwprobe.c new file mode 100644 index 000000000000..2eba34011786 --- /dev/null +++ b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include + +#include +#include + +#include +#include + +void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const stru= ct cpumask *cpus) +{ + VENDOR_EXTENSION_SUPPORTED(pair, cpus, + riscv_isa_vendor_ext_list_thead.per_hart_isa_bitmap, { + VENDOR_EXT_KEY(XTHEADVECTOR); + }); +} --=20 2.45.0 From nobody Sat Nov 30 03:28:39 2024 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 270F91917CE for ; Thu, 12 Sep 2024 05:56:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120570; cv=none; b=UufE7cdJn9pie7VBDonYt9VCEvxzjotM8tSkwCDI3WyT5/2182e0NJkc69RglcvTVe2exsc0KObwkd7U+wtU91QluX8Wp1puWd3LCoWnPNsrhJG3sWmxLsB1euYS0wwsMKmvFCYbweqyCZb+AiiWRaS64W5WPQCsOEFpNSHE5To= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120570; c=relaxed/simple; bh=R1ruP19VNMYIJ2t74sibaC/YoWJ+uh82rPlu1gqwh/o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PvL044x5v5yNnp1cr5FF/yHSbJVAesG85xG05t4N7Q1V+hDp643zu9nfxkeqk/fNZaW5TT/AjHzZq/Bs7ITqW1lfE+wJyMtd29kvCtfBBEoXas+650vawDMzraxHD1zoTPhBhboll6QEWfjzfe/fJIrwEiY0L2gv8yEx2s9Fwko= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=wiyY5qi0; arc=none smtp.client-ip=209.85.214.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="wiyY5qi0" Received: by mail-pl1-f175.google.com with SMTP id d9443c01a7336-20551e2f1f8so6098975ad.2 for ; Wed, 11 Sep 2024 22:56:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1726120568; x=1726725368; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=WzA4CLrN9c04I0TkiHjILEnLnNrrRfsvuLr439lHPOs=; b=wiyY5qi0BgKPpmcC2sYG6K6jmjYwYxHudvxIZicqMgUQew2H7/1A/eb1DHXjIoifvS Oc1/A1GfNqUv+ugZOIXkcxBe9FAgl755KK3TJU6L/wtldRNDEsTHxG5/0PQJL79TGACh iRi3rHeUPWNUL1Qg1AlSLLft6HT0IRuERlfh/mOR81LkjJ5PujOKQaAByRcuId25EU+L lK61ulq5qMyNG15PB4d0Td6YXUuZdu5pM+75tb3Kc9ExUNDGuRqe9rtFnWD8ARseiwap Hl7H9EUDt2n4+7SrG0ZiJb05nWx2giIRQ/trv39dFL8C3Rm7PkzapenEQpe+i3OowxGE k/Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726120568; x=1726725368; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WzA4CLrN9c04I0TkiHjILEnLnNrrRfsvuLr439lHPOs=; b=j+KZL4hdESLUdZSf7Jq/jnpYUxqH0z8r31XzGlDc2RbzFulEBf9AlAx/tFtmReBFBH WkXgYAuyXRPdNXqYOw6H9DX2hIo8rztj5Yk1RSznS5cCjx6x3ywxiYMuwTWot9o8l32K AnwTyxBO0Y2tEXfZTeFkbiQexfEiRLkGYyNc62TfcJ3IJcZKaNwFozfx4/0XhUb5bWyT Ea5/qYpjal9Cvlhl8FOYteJ2WPhGsbFHFGiU1bf9hvZ3ztLHs6jecx/okWlLhcc0TIYv tc8oHDDnMFA5h34wbYD0VyXCq1Gi3c1ZsWvnicIE17wlHvk2zhRa22X0e4UgblhsuyL9 n7ng== X-Forwarded-Encrypted: i=1; AJvYcCXtkcvu0w2u6fTHC5kdm5OQ/mCSFLnbWUtwN0tEHUdvaZkniDrSwvfWgQ/4hWrvuBrdkSxW/DZDnptXFJA=@vger.kernel.org X-Gm-Message-State: AOJu0YxMWZz0QxgA1K9ktqn+ZXkqn3RKvMruOI30vkKyW3BcRSvKTiAm PuonpujuI8cU74BcrMupNSUylS6Dou9ecSe5t8NQp9NU7qykaMC4z/7hVL9bzP4= X-Google-Smtp-Source: AGHT+IGAuCccU07DZqdkiMWs0Ena2Nnk3dSiXEP2sYQH784oXf5a8ibel1CZaIU3Cgs5q7SC+nXlTg== X-Received: by 2002:a17:902:da8a:b0:205:68a4:b2d9 with SMTP id d9443c01a7336-2076e4150famr25682015ad.48.1726120568364; Wed, 11 Sep 2024 22:56:08 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe99b6sm7870465ad.209.2024.09.11.22.56.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 22:56:07 -0700 (PDT) From: Charlie Jenkins Date: Wed, 11 Sep 2024 22:55:19 -0700 Subject: [PATCH v10 11/14] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240911-xtheadvector-v10-11-8d3930091246@rivosinc.com> References: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> In-Reply-To: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1263; i=charlie@rivosinc.com; h=from:subject:message-id; bh=R1ruP19VNMYIJ2t74sibaC/YoWJ+uh82rPlu1gqwh/o=; b=owGbwMvMwCHWx5hUnlvL8Y3xtFoSQ9qjpljm0+eaN738l85uMF36i+LEa+wXNIQaszqzX2xan Wzwst6so5SFQYyDQVZMkYXnWgNz6x39sqOiZRNg5rAygQxh4OIUgIl0KTIyfFf95Nteqhx7X/P8 DuUjS9qEgl7qbb1ybo3LoWPHqvhZ/zAynCvdIxn/d0l27MM1l1UiWNIzcuvPtW2QWLHppnzMlsJ SVgA= X-Developer-Key: i=charlie@rivosinc.com; a=openpgp; fpr=7D834FF11B1D8387E61C776FFB10D1F27D6B1354 Document support for thead vendor extensions using the key RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 and xtheadvector extension using the key RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR. Signed-off-by: Charlie Jenkins Reviewed-by: Evan Green --- Documentation/arch/riscv/hwprobe.rst | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 3db60a0911df..400753d166ee 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -266,3 +266,13 @@ The following keys are defined: represent the highest userspace virtual address usable. =20 * :c:macro:`RISCV_HWPROBE_KEY_TIME_CSR_FREQ`: Frequency (in Hz) of `time C= SR`. + +* :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0`: A bitmask containing the + thead vendor extensions that are compatible with the + :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. + + * T-HEAD + + * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`: The xtheadvector v= endor + extension is supported in the T-Head ISA extensions spec starting = from + commit a18c801634 ("Add T-Head VECTOR vendor extension. "). --=20 2.45.0 From nobody Sat Nov 30 03:28:39 2024 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FA4A1922CD for ; Thu, 12 Sep 2024 05:56:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120574; cv=none; b=ID8caSy8qh3KgiBke7BKmGlArwlW/EDbKkfvgxtJNRkkSoI4mpZHXgWuXtyYgs+zkCntR61KBIs+hEU6wbYce88gQDGiaWdBXIsFbgZHDzKLVXxRv2+fkeKwQnZbywa634rCl64xDnr3UMs/KU+vtFxmknbNqaphICyBm38Aji0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120574; c=relaxed/simple; bh=G18loSJF3wjUKC0fiIddR4KY4ojwxUJpqwitEAsPQlA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VCeK9CTtRiosimPPcpUQ08nv13PsfJr5tNArueOLEfmnsSkoQBxWbfOcYmC1peTASapOVUD/5yz7RhH6y+9U7UFSqGUIsduDmbrObUDD5slAGT6XXVZVHiAxKBn9zlVhGfLfLU9jwMZj129b7bL2k17URNFBphDoC8NiHhQuo1o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=ITbdKWlh; arc=none smtp.client-ip=209.85.214.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="ITbdKWlh" Received: by mail-pl1-f182.google.com with SMTP id d9443c01a7336-20688fbaeafso7444455ad.0 for ; Wed, 11 Sep 2024 22:56:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1726120571; x=1726725371; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=OfGwMNaaN7lzjO2AB0iAlYzcDlw0mxC1YLUkpCvPDpY=; b=ITbdKWlhZmP8UDop6ByqoSLxgpiTsXpXf8DfRNnQo7nzRVYoCxgX+IXHoE/f81B2FF /2wblxFJZgX+TcAWlAHMcRY/MOzQsuCKiJVhA41/tKSUU8qUdmYCTBKtg2b2EMLdhOyB B0aWVAcwyJQDapRs4qVRH2Shcb2takcn6jb65UaqLQpuuvYlz5IZtaDDkcY4w/fd70kb pJWfJhRH9V8NlSYp9Q8O5X0SDDJSFBDuvbCEaPJARqtw7x4IJIo7u7vbIBxRzQiyEp2z ZaQNsQE6+tkgInFJTbK43B+3+B6poxAUFn/oMPirZpsnJ5bpG7clJHOuyEHoGTTbkT4Q iiwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726120571; x=1726725371; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OfGwMNaaN7lzjO2AB0iAlYzcDlw0mxC1YLUkpCvPDpY=; b=GO+HqeiMDSY3esGmFYBb0QjQV3BbA8Zq8yiyo/njNXFCpfeXGfSEku8CBVMoc53M64 9XciuCIt0SteI+hwvGs0Lx5XQsgigvb35Jn8iTsKL51/bI2DHlAsIEMzZ1DcANzCaTAC P6+UACIWoPiuw7OP9ytaQxY42Zbc//t7OPFMXk/MXcak3n03/tPIdUN43AJoZI88VqLy od910NnmRy96Sb7FKIDrU6mM9qWsOMIMfZm5e8KwlcFARjENJpAUYWI6m69EDlMM8UbT mvohKJesoZwcovFKM/eTvdxnvCP67Y1KezNOBroc9npdCdy42QVwIGtERJ7hLJRRokYu FxsA== X-Forwarded-Encrypted: i=1; AJvYcCXyU6PRLIaPZwAXbuWHffkONz9B/lyjm9ZXUdACd9qhnVverI2t2xbjbVPQ8SWWsE0Zf7OdjkPK/kdezHM=@vger.kernel.org X-Gm-Message-State: AOJu0YyLSr5+WtVkYS+SUGdSimV2HeHv3Ti/O+hrpdZ1Zoi6K+mje1Yw GGOowf6ctBnFf0jyNtV3o60iTRqJsI/Fciuc1UKEP8RLiy2tdTzu/gUltIlZG2k= X-Google-Smtp-Source: AGHT+IGyWa3dRPT+F0tzruAICprBYOVGUCh6YAqIyLxv7jiWaDnPsl8Ozd0jH4BXkphvQ31cVWsPug== X-Received: by 2002:a17:902:e805:b0:207:3a4a:de43 with SMTP id d9443c01a7336-2076e3b8ca8mr32668535ad.34.1726120570477; Wed, 11 Sep 2024 22:56:10 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe99b6sm7870465ad.209.2024.09.11.22.56.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 22:56:09 -0700 (PDT) From: Charlie Jenkins Date: Wed, 11 Sep 2024 22:55:20 -0700 Subject: [PATCH v10 12/14] selftests: riscv: Fix vector tests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240911-xtheadvector-v10-12-8d3930091246@rivosinc.com> References: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> In-Reply-To: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=19792; i=charlie@rivosinc.com; h=from:subject:message-id; bh=G18loSJF3wjUKC0fiIddR4KY4ojwxUJpqwitEAsPQlA=; b=owGbwMvMwCHWx5hUnlvL8Y3xtFoSQ9qjpti+bQmvEgL4Ons3vvtsrFonkcvgeTJqNteuEt3Zc w6dcMrqKGVhEONgkBVTZOG51sDceke/7Kho2QSYOaxMIEMYuDgFYCKuqxgZ3qeuvaDlohGno5qy +OXrFrYdEgo/1/ya8kcxZdrOyza3whkZps7KU+tdJqlScPHIxaQ50/fvDW8/fO2WhcqtI3ukr3I k8wMA X-Developer-Key: i=charlie@rivosinc.com; a=openpgp; fpr=7D834FF11B1D8387E61C776FFB10D1F27D6B1354 Overhaul the riscv vector tests to use kselftest_harness to help the test cases correctly report the results and decouple the individual test cases from each other. With this refactoring, only run the test cases if vector is reported and properly report the test case as skipped otherwise. The v_initval_nolibc test was previously not checking if vector was supported and used a function (malloc) which invalidates the state of the vector registers. Signed-off-by: Charlie Jenkins --- tools/testing/selftests/riscv/vector/.gitignore | 3 +- tools/testing/selftests/riscv/vector/Makefile | 17 +- .../selftests/riscv/vector/v_exec_initval_nolibc.c | 85 +++++++ tools/testing/selftests/riscv/vector/v_helpers.c | 57 +++++ tools/testing/selftests/riscv/vector/v_helpers.h | 6 + tools/testing/selftests/riscv/vector/v_initval.c | 16 ++ .../selftests/riscv/vector/v_initval_nolibc.c | 68 ----- .../testing/selftests/riscv/vector/vstate_prctl.c | 278 ++++++++++++-----= ---- 8 files changed, 337 insertions(+), 193 deletions(-) diff --git a/tools/testing/selftests/riscv/vector/.gitignore b/tools/testin= g/selftests/riscv/vector/.gitignore index 9ae7964491d5..7d9c87cd0649 100644 --- a/tools/testing/selftests/riscv/vector/.gitignore +++ b/tools/testing/selftests/riscv/vector/.gitignore @@ -1,3 +1,4 @@ vstate_exec_nolibc vstate_prctl -v_initval_nolibc +v_initval +v_exec_initval_nolibc diff --git a/tools/testing/selftests/riscv/vector/Makefile b/tools/testing/= selftests/riscv/vector/Makefile index bfff0ff4f3be..995746359477 100644 --- a/tools/testing/selftests/riscv/vector/Makefile +++ b/tools/testing/selftests/riscv/vector/Makefile @@ -2,18 +2,27 @@ # Copyright (C) 2021 ARM Limited # Originally tools/testing/arm64/abi/Makefile =20 -TEST_GEN_PROGS :=3D vstate_prctl v_initval_nolibc -TEST_GEN_PROGS_EXTENDED :=3D vstate_exec_nolibc +TEST_GEN_PROGS :=3D v_initval vstate_prctl +TEST_GEN_PROGS_EXTENDED :=3D vstate_exec_nolibc v_exec_initval_nolibc sys_= hwprobe.o v_helpers.o =20 include ../../lib.mk =20 -$(OUTPUT)/vstate_prctl: vstate_prctl.c ../hwprobe/sys_hwprobe.S +$(OUTPUT)/sys_hwprobe.o: ../hwprobe/sys_hwprobe.S + $(CC) -static -c -o$@ $(CFLAGS) $^ + +$(OUTPUT)/v_helpers.o: v_helpers.c + $(CC) -static -c -o$@ $(CFLAGS) $^ + +$(OUTPUT)/vstate_prctl: vstate_prctl.c $(OUTPUT)/sys_hwprobe.o $(OUTPUT)/v= _helpers.o $(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^ =20 $(OUTPUT)/vstate_exec_nolibc: vstate_exec_nolibc.c $(CC) -nostdlib -static -include ../../../../include/nolibc/nolibc.h \ -Wall $(CFLAGS) $(LDFLAGS) $^ -o $@ -lgcc =20 -$(OUTPUT)/v_initval_nolibc: v_initval_nolibc.c +$(OUTPUT)/v_initval: v_initval.c $(OUTPUT)/sys_hwprobe.o $(OUTPUT)/v_helpe= rs.o + $(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^ + +$(OUTPUT)/v_exec_initval_nolibc: v_exec_initval_nolibc.c $(CC) -nostdlib -static -include ../../../../include/nolibc/nolibc.h \ -Wall $(CFLAGS) $(LDFLAGS) $^ -o $@ -lgcc diff --git a/tools/testing/selftests/riscv/vector/v_exec_initval_nolibc.c b= /tools/testing/selftests/riscv/vector/v_exec_initval_nolibc.c new file mode 100644 index 000000000000..4a39cab29c34 --- /dev/null +++ b/tools/testing/selftests/riscv/vector/v_exec_initval_nolibc.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Get values of vector registers as soon as the program starts to test if + * is properly cleaning the values before starting a new program. Vector + * registers are caller saved, so no function calls may happen before read= ing + * the values. To further ensure consistency, this file is compiled without + * libc and without auto-vectorization. + * + * To be "clean" all values must be either all ones or all zeroes. + */ + +#define __stringify_1(x...) #x +#define __stringify(x...) __stringify_1(x) + +int main(int argc, char **argv) +{ + char prev_value =3D 0, value; + unsigned long vl; + int first =3D 1; + + asm volatile ( + ".option push\n\t" + ".option arch, +v\n\t" + "vsetvli %[vl], x0, e8, m1, ta, ma\n\t" + ".option pop\n\t" + : [vl] "=3Dr" (vl) + ); + +#define CHECK_VECTOR_REGISTER(register) ({ \ + for (int i =3D 0; i < vl; i++) { \ + asm volatile ( \ + ".option push\n\t" \ + ".option arch, +v\n\t" \ + "vmv.x.s %0, " __stringify(register) "\n\t" \ + "vsrl.vi " __stringify(register) ", " __stringify(register) ", 8\n\t" \ + ".option pop\n\t" \ + : "=3Dr" (value)); \ + if (first) { \ + first =3D 0; \ + } else if (value !=3D prev_value || !(value =3D=3D 0x00 || value =3D=3D = 0xff)) { \ + printf("Register " __stringify(register) \ + " values not clean! value: %u\n", value); \ + exit(-1); \ + } \ + prev_value =3D value; \ + } \ +}) + + CHECK_VECTOR_REGISTER(v0); + CHECK_VECTOR_REGISTER(v1); + CHECK_VECTOR_REGISTER(v2); + CHECK_VECTOR_REGISTER(v3); + CHECK_VECTOR_REGISTER(v4); + CHECK_VECTOR_REGISTER(v5); + CHECK_VECTOR_REGISTER(v6); + CHECK_VECTOR_REGISTER(v7); + CHECK_VECTOR_REGISTER(v8); + CHECK_VECTOR_REGISTER(v9); + CHECK_VECTOR_REGISTER(v10); + CHECK_VECTOR_REGISTER(v11); + CHECK_VECTOR_REGISTER(v12); + CHECK_VECTOR_REGISTER(v13); + CHECK_VECTOR_REGISTER(v14); + CHECK_VECTOR_REGISTER(v15); + CHECK_VECTOR_REGISTER(v16); + CHECK_VECTOR_REGISTER(v17); + CHECK_VECTOR_REGISTER(v18); + CHECK_VECTOR_REGISTER(v19); + CHECK_VECTOR_REGISTER(v20); + CHECK_VECTOR_REGISTER(v21); + CHECK_VECTOR_REGISTER(v22); + CHECK_VECTOR_REGISTER(v23); + CHECK_VECTOR_REGISTER(v24); + CHECK_VECTOR_REGISTER(v25); + CHECK_VECTOR_REGISTER(v26); + CHECK_VECTOR_REGISTER(v27); + CHECK_VECTOR_REGISTER(v28); + CHECK_VECTOR_REGISTER(v29); + CHECK_VECTOR_REGISTER(v30); + CHECK_VECTOR_REGISTER(v31); + +#undef CHECK_VECTOR_REGISTER + + return 0; +} diff --git a/tools/testing/selftests/riscv/vector/v_helpers.c b/tools/testi= ng/selftests/riscv/vector/v_helpers.c new file mode 100644 index 000000000000..d50f4dfbf9e5 --- /dev/null +++ b/tools/testing/selftests/riscv/vector/v_helpers.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "../hwprobe/hwprobe.h" +#include +#include +#include +#include +#include + +bool is_vector_supported(void) +{ + struct riscv_hwprobe pair; + + pair.key =3D RISCV_HWPROBE_KEY_IMA_EXT_0; + riscv_hwprobe(&pair, 1, 0, NULL, 0); + return pair.value & RISCV_HWPROBE_EXT_ZVE32X; +} + +int launch_test(char *next_program, int test_inherit) +{ + char *exec_argv[3], *exec_envp[1]; + int rc, pid, status; + + pid =3D fork(); + if (pid < 0) { + printf("fork failed %d", pid); + return -1; + } + + if (!pid) { + exec_argv[0] =3D next_program; + exec_argv[1] =3D test_inherit !=3D 0 ? "x" : NULL; + exec_argv[2] =3D NULL; + exec_envp[0] =3D NULL; + /* launch the program again to check inherit */ + rc =3D execve(next_program, exec_argv, exec_envp); + if (rc) { + perror("execve"); + printf("child execve failed %d\n", rc); + exit(-1); + } + } + + rc =3D waitpid(-1, &status, 0); + if (rc < 0) { + printf("waitpid failed\n"); + return -3; + } + + if ((WIFEXITED(status) && WEXITSTATUS(status) =3D=3D -1) || + WIFSIGNALED(status)) { + printf("child exited abnormally\n"); + return -4; + } + + return WEXITSTATUS(status); +} diff --git a/tools/testing/selftests/riscv/vector/v_helpers.h b/tools/testi= ng/selftests/riscv/vector/v_helpers.h new file mode 100644 index 000000000000..faeeeb625b6e --- /dev/null +++ b/tools/testing/selftests/riscv/vector/v_helpers.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include + +bool is_vector_supported(void); + +int launch_test(char *next_program, int test_inherit); diff --git a/tools/testing/selftests/riscv/vector/v_initval.c b/tools/testi= ng/selftests/riscv/vector/v_initval.c new file mode 100644 index 000000000000..f38b5797fa31 --- /dev/null +++ b/tools/testing/selftests/riscv/vector/v_initval.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "../../kselftest_harness.h" +#include "v_helpers.h" + +#define NEXT_PROGRAM "./v_exec_initval_nolibc" + +TEST(v_initval) +{ + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); + + ASSERT_EQ(0, launch_test(NEXT_PROGRAM, 0)); +} + +TEST_HARNESS_MAIN diff --git a/tools/testing/selftests/riscv/vector/v_initval_nolibc.c b/tool= s/testing/selftests/riscv/vector/v_initval_nolibc.c deleted file mode 100644 index 1dd94197da30..000000000000 --- a/tools/testing/selftests/riscv/vector/v_initval_nolibc.c +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include "../../kselftest.h" -#define MAX_VSIZE (8192 * 32) - -void dump(char *ptr, int size) -{ - int i =3D 0; - - for (i =3D 0; i < size; i++) { - if (i !=3D 0) { - if (i % 16 =3D=3D 0) - printf("\n"); - else if (i % 8 =3D=3D 0) - printf(" "); - } - printf("%02x ", ptr[i]); - } - printf("\n"); -} - -int main(void) -{ - int i; - unsigned long vl; - char *datap, *tmp; - - datap =3D malloc(MAX_VSIZE); - if (!datap) { - ksft_test_result_fail("fail to allocate memory for size =3D %d\n", MAX_V= SIZE); - exit(-1); - } - - tmp =3D datap; - asm volatile ( - ".option push\n\t" - ".option arch, +v\n\t" - "vsetvli %0, x0, e8, m8, ta, ma\n\t" - "vse8.v v0, (%2)\n\t" - "add %1, %2, %0\n\t" - "vse8.v v8, (%1)\n\t" - "add %1, %1, %0\n\t" - "vse8.v v16, (%1)\n\t" - "add %1, %1, %0\n\t" - "vse8.v v24, (%1)\n\t" - ".option pop\n\t" - : "=3D&r" (vl), "=3Dr" (tmp) : "r" (datap) : "memory"); - - ksft_print_msg("vl =3D %lu\n", vl); - - if (datap[0] !=3D 0x00 && datap[0] !=3D 0xff) { - ksft_test_result_fail("v-regesters are not properly initialized\n"); - dump(datap, vl * 4); - exit(-1); - } - - for (i =3D 1; i < vl * 4; i++) { - if (datap[i] !=3D datap[0]) { - ksft_test_result_fail("detect stale values on v-regesters\n"); - dump(datap, vl * 4); - exit(-2); - } - } - - free(datap); - ksft_exit_pass(); - return 0; -} diff --git a/tools/testing/selftests/riscv/vector/vstate_prctl.c b/tools/te= sting/selftests/riscv/vector/vstate_prctl.c index 895177f6bf4c..2fc86924bf42 100644 --- a/tools/testing/selftests/riscv/vector/vstate_prctl.c +++ b/tools/testing/selftests/riscv/vector/vstate_prctl.c @@ -3,50 +3,13 @@ #include #include #include +#include +#include =20 -#include "../hwprobe/hwprobe.h" -#include "../../kselftest.h" +#include "../../kselftest_harness.h" +#include "v_helpers.h" =20 #define NEXT_PROGRAM "./vstate_exec_nolibc" -static int launch_test(int test_inherit) -{ - char *exec_argv[3], *exec_envp[1]; - int rc, pid, status; - - pid =3D fork(); - if (pid < 0) { - ksft_test_result_fail("fork failed %d", pid); - return -1; - } - - if (!pid) { - exec_argv[0] =3D NEXT_PROGRAM; - exec_argv[1] =3D test_inherit !=3D 0 ? "x" : NULL; - exec_argv[2] =3D NULL; - exec_envp[0] =3D NULL; - /* launch the program again to check inherit */ - rc =3D execve(NEXT_PROGRAM, exec_argv, exec_envp); - if (rc) { - perror("execve"); - ksft_test_result_fail("child execve failed %d\n", rc); - exit(-1); - } - } - - rc =3D waitpid(-1, &status, 0); - if (rc < 0) { - ksft_test_result_fail("waitpid failed\n"); - return -3; - } - - if ((WIFEXITED(status) && WEXITSTATUS(status) =3D=3D -1) || - WIFSIGNALED(status)) { - ksft_test_result_fail("child exited abnormally\n"); - return -4; - } - - return WEXITSTATUS(status); -} =20 int test_and_compare_child(long provided, long expected, int inherit) { @@ -54,128 +17,203 @@ int test_and_compare_child(long provided, long expect= ed, int inherit) =20 rc =3D prctl(PR_RISCV_V_SET_CONTROL, provided); if (rc !=3D 0) { - ksft_test_result_fail("prctl with provided arg %lx failed with code %d\n= ", - provided, rc); + printf("prctl with provided arg %lx failed with code %d\n", + provided, rc); return -1; } - rc =3D launch_test(inherit); + rc =3D launch_test(NEXT_PROGRAM, inherit); if (rc !=3D expected) { - ksft_test_result_fail("Test failed, check %d !=3D %ld\n", rc, - expected); + printf("Test failed, check %d !=3D %ld\n", rc, expected); return -2; } return 0; } =20 -#define PR_RISCV_V_VSTATE_CTRL_CUR_SHIFT 0 -#define PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT 2 +#define PR_RISCV_V_VSTATE_CTRL_CUR_SHIFT 0 +#define PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT 2 =20 -int main(void) +TEST(get_control_no_v) { - struct riscv_hwprobe pair; - long flag, expected; long rc; =20 - pair.key =3D RISCV_HWPROBE_KEY_IMA_EXT_0; - rc =3D riscv_hwprobe(&pair, 1, 0, NULL, 0); - if (rc < 0) { - ksft_test_result_fail("hwprobe() failed with %ld\n", rc); - return -1; - } + if (is_vector_supported()) + SKIP(return, "Test expects vector to be not supported"); =20 - if (pair.key !=3D RISCV_HWPROBE_KEY_IMA_EXT_0) { - ksft_test_result_fail("hwprobe cannot probe RISCV_HWPROBE_KEY_IMA_EXT_0\= n"); - return -2; - } + rc =3D prctl(PR_RISCV_V_GET_CONTROL); + EXPECT_EQ(-1, rc) + TH_LOG("GET_CONTROL should fail on kernel/hw without ZVE32X"); + EXPECT_EQ(EINVAL, errno) + TH_LOG("GET_CONTROL should fail on kernel/hw without ZVE32X"); +} =20 - if (!(pair.value & RISCV_HWPROBE_EXT_ZVE32X)) { - rc =3D prctl(PR_RISCV_V_GET_CONTROL); - if (rc !=3D -1 || errno !=3D EINVAL) { - ksft_test_result_fail("GET_CONTROL should fail on kernel/hw without ZVE= 32X\n"); - return -3; - } - - rc =3D prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); - if (rc !=3D -1 || errno !=3D EINVAL) { - ksft_test_result_fail("SET_CONTROL should fail on kernel/hw without ZVE= 32X\n"); - return -4; - } - - ksft_test_result_skip("Vector not supported\n"); - return 0; - } +TEST(set_control_no_v) +{ + long rc; + + if (is_vector_supported()) + SKIP(return, "Test expects vector to be not supported"); + + rc =3D prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); + EXPECT_EQ(-1, rc) + TH_LOG("SET_CONTROL should fail on kernel/hw without ZVE32X"); + EXPECT_EQ(EINVAL, errno) + TH_LOG("SET_CONTROL should fail on kernel/hw without ZVE32X"); +} + +TEST(vstate_on_current) +{ + long flag; + long rc; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 flag =3D PR_RISCV_V_VSTATE_CTRL_ON; rc =3D prctl(PR_RISCV_V_SET_CONTROL, flag); - if (rc !=3D 0) { - ksft_test_result_fail("Enabling V for current should always success\n"); - return -5; - } + EXPECT_EQ(0, rc) TH_LOG("Enabling V for current should always success"); +} + +TEST(vstate_off_eperm) +{ + long flag; + long rc; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 flag =3D PR_RISCV_V_VSTATE_CTRL_OFF; rc =3D prctl(PR_RISCV_V_SET_CONTROL, flag); - if (rc !=3D -1 || errno !=3D EPERM) { - ksft_test_result_fail("Disabling current's V alive must fail with EPERM(= %d)\n", - errno); - return -5; - } + EXPECT_EQ(EPERM, errno) + TH_LOG("Disabling V in current thread with V enabled must fail with EPERM= (%d)", errno); + EXPECT_EQ(-1, rc) + TH_LOG("Disabling V in current thread with V enabled must fail with EPERM= (%d)", errno); +} + +TEST(vstate_on_no_nesting) +{ + long flag; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 /* Turn on next's vector explicitly and test */ flag =3D PR_RISCV_V_VSTATE_CTRL_ON << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; - if (test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_ON, 0)) - return -6; + + EXPECT_EQ(0, + test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_ON, 0)); +} + +TEST(vstate_off_nesting) +{ + long flag; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 /* Turn off next's vector explicitly and test */ flag =3D PR_RISCV_V_VSTATE_CTRL_OFF << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; - if (test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_OFF, 0)) - return -7; + + EXPECT_EQ(0, + test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_OFF, 1)); +} + +TEST(vstate_on_inherit_no_nesting) +{ + long flag, expected; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); + + /* Turn on next's vector explicitly and test no inherit */ + flag =3D PR_RISCV_V_VSTATE_CTRL_ON << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; + flag |=3D PR_RISCV_V_VSTATE_CTRL_INHERIT; + expected =3D flag | PR_RISCV_V_VSTATE_CTRL_ON; + + EXPECT_EQ(0, test_and_compare_child(flag, expected, 0)); +} + +TEST(vstate_on_inherit) +{ + long flag, expected; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 /* Turn on next's vector explicitly and test inherit */ flag =3D PR_RISCV_V_VSTATE_CTRL_ON << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; flag |=3D PR_RISCV_V_VSTATE_CTRL_INHERIT; expected =3D flag | PR_RISCV_V_VSTATE_CTRL_ON; - if (test_and_compare_child(flag, expected, 0)) - return -8; =20 - if (test_and_compare_child(flag, expected, 1)) - return -9; + EXPECT_EQ(0, test_and_compare_child(flag, expected, 1)); +} + +TEST(vstate_off_inherit_no_nesting) +{ + long flag, expected; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); + + /* Turn off next's vector explicitly and test no inherit */ + flag =3D PR_RISCV_V_VSTATE_CTRL_OFF << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; + flag |=3D PR_RISCV_V_VSTATE_CTRL_INHERIT; + expected =3D flag | PR_RISCV_V_VSTATE_CTRL_OFF; + + EXPECT_EQ(0, test_and_compare_child(flag, expected, 0)); +} + +TEST(vstate_off_inherit) +{ + long flag, expected; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 /* Turn off next's vector explicitly and test inherit */ flag =3D PR_RISCV_V_VSTATE_CTRL_OFF << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; flag |=3D PR_RISCV_V_VSTATE_CTRL_INHERIT; expected =3D flag | PR_RISCV_V_VSTATE_CTRL_OFF; - if (test_and_compare_child(flag, expected, 0)) - return -10; =20 - if (test_and_compare_child(flag, expected, 1)) - return -11; + EXPECT_EQ(0, test_and_compare_child(flag, expected, 1)); +} + +/* arguments should fail with EINVAL */ +TEST(inval_set_control_1) +{ + int rc; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 - /* arguments should fail with EINVAL */ rc =3D prctl(PR_RISCV_V_SET_CONTROL, 0xff0); - if (rc !=3D -1 || errno !=3D EINVAL) { - ksft_test_result_fail("Undefined control argument should return EINVAL\n= "); - return -12; - } + EXPECT_EQ(-1, rc); + EXPECT_EQ(EINVAL, errno); +} + +/* arguments should fail with EINVAL */ +TEST(inval_set_control_2) +{ + int rc; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 rc =3D prctl(PR_RISCV_V_SET_CONTROL, 0x3); - if (rc !=3D -1 || errno !=3D EINVAL) { - ksft_test_result_fail("Undefined control argument should return EINVAL\n= "); - return -12; - } + EXPECT_EQ(-1, rc); + EXPECT_EQ(EINVAL, errno); +} =20 - rc =3D prctl(PR_RISCV_V_SET_CONTROL, 0xc); - if (rc !=3D -1 || errno !=3D EINVAL) { - ksft_test_result_fail("Undefined control argument should return EINVAL\n= "); - return -12; - } +/* arguments should fail with EINVAL */ +TEST(inval_set_control_3) +{ + int rc; =20 - rc =3D prctl(PR_RISCV_V_SET_CONTROL, 0xc); - if (rc !=3D -1 || errno !=3D EINVAL) { - ksft_test_result_fail("Undefined control argument should return EINVAL\n= "); - return -12; - } + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 - ksft_test_result_pass("tests for riscv_v_vstate_ctrl pass\n"); - ksft_exit_pass(); - return 0; + rc =3D prctl(PR_RISCV_V_SET_CONTROL, 0xc); + EXPECT_EQ(-1, rc); + EXPECT_EQ(EINVAL, errno); } + +TEST_HARNESS_MAIN --=20 2.45.0 From nobody Sat Nov 30 03:28:39 2024 Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BADB192B8D for ; Thu, 12 Sep 2024 05:56:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120575; cv=none; b=Ww5+mRUOhZOGVX6r9np61kMj6YvOd80DZgkM3E4WBITIJMySWDSsg9HbWskHoustATWtK/xJNnHNjJCkKlcSDXJjB2alkU/hUWoKpKtLChLRDI3thU4D9S3FUBlixezZQUKEd+6BxdO8r5DO5m6wSomreZeIeFuh/UbmLMwO79w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120575; c=relaxed/simple; bh=r5q5Nx9ziC3kMn5UCdprb8sC68/F7tS+KE0AR3MsHAI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YZ7+KPSmNlQxQ9UpfJib1pKrkRfNU3SPEsIFtVMQb/riN0+5K+QzgeRMgNm8V0nj4j4n43spDLfERUyIlA2EPoINXr8o+HxCyScawSnY0eH9gLi+xQHSRJY37kk4yNeqWvbJGiKeLIMG93qq+fcMx+Ggu7sN7wT2VFy8taQOxCc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=gm9ihrau; arc=none smtp.client-ip=209.85.214.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="gm9ihrau" Received: by mail-pl1-f170.google.com with SMTP id d9443c01a7336-2053f6b8201so5666055ad.2 for ; Wed, 11 Sep 2024 22:56:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1726120573; x=1726725373; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Rl8hTq3snwrtlchQoxOGzkM3W0TMCzfAHv0H42fdImw=; b=gm9ihrauLEVpOgDT+fiGHMDqzBykhJN0CKrn+cHaL+LWKakpKchhz7a1zug2fGWGHY GBqifmt+tESRMuTpf+x9TQ6VVOdVDr14AsAz96iXau1iPEmz2vYamEj8ppbSmDDwwNU7 o/LOnmKpb1ZBZH/tOnDj4lFS3E4I4J9ENaetNlM8AQwik09cyz9NHw3EBB+rqSCRmGO6 T4fqgu47+s2H2j5xbqm9djAb4nZueY/ADcplMD0ubueWBmPz7atdWBT8GC/Qh4RGV3sk rOwCcEDtt3tIiOibn9CZjoCGWWpUUae8w1vQ7OfQNa0Fs8Ed7Eyuq3dcCiM5ptENFdtl R7Qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726120573; x=1726725373; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Rl8hTq3snwrtlchQoxOGzkM3W0TMCzfAHv0H42fdImw=; b=PR7xx0wypULHYpm5a6rwT6m4vTSDBte4SookG0HxKDCabglr8KdcqvHIYTuUBBQ1Wr j1rlMCM3nNEn/jNZb+PZnagi5YNz9Ek0NF0ADdKJuI8FVv2UtRQx5Rki/XEHlwlkDCEx NU7u386FGAvVOeYRADiddLGbch1u/F7rh6v/5wMDqAX2yOWbkp/ItsRcpuawkaMCHTWP OknHpPXHvaGFv4McEo57L8vw+nNRxKyZfplGweV5SayLueGdYKnSxcygyi7IRC54SwuR UV7w7llZVC8sm7veZirNGdnk7Yk6iVZHn3o+9nlg9wXDt5nH+DuYoHaiIxLBE9s4SlRF o/Yg== X-Forwarded-Encrypted: i=1; AJvYcCWbqjorjxMj68aMuRwVZxcCng+RhUcgKQnY7Hgy7jZhivaPmHTAAy5mX8BSW+oqap3bXZWyXx2mZTeid6M=@vger.kernel.org X-Gm-Message-State: AOJu0YyWpt4pulj8QF9uFXkDuR5KTT414q60vqYupC7IocXOF93QXLoR +5RsRoiR8903urXlJjWmSB2Gpac7lnLnEW2DzEWW/cZjdvuCd5F3pLzO6ZdwGQI= X-Google-Smtp-Source: AGHT+IHhtHN70ssQAQ9tvmFco1lcYpC7nPZvWradR6gyrPO0ML6odlzOOORZ19HXgympUfBzHt3KcQ== X-Received: by 2002:a17:902:d4cd:b0:1fd:8eaf:ea73 with SMTP id d9443c01a7336-2076e393a6amr22375125ad.35.1726120572647; Wed, 11 Sep 2024 22:56:12 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe99b6sm7870465ad.209.2024.09.11.22.56.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 22:56:11 -0700 (PDT) From: Charlie Jenkins Date: Wed, 11 Sep 2024 22:55:21 -0700 Subject: [PATCH v10 13/14] selftests: riscv: Support xtheadvector in vector tests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240911-xtheadvector-v10-13-8d3930091246@rivosinc.com> References: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> In-Reply-To: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=12867; i=charlie@rivosinc.com; h=from:subject:message-id; bh=r5q5Nx9ziC3kMn5UCdprb8sC68/F7tS+KE0AR3MsHAI=; b=owGbwMvMwCHWx5hUnlvL8Y3xtFoSQ9qjptiUSJ0ZizZmHT9v9OmXk+7/SoeeyxXT+/nuy07TF Xqi2B/VUcrCIMbBICumyMJzrYG59Y5+2VHRsgkwc1iZQIYwcHEKwETarzL8z3nbqW2q5DXnSpOV 3zlHsbXNa/8w/Xu1yV+hPWxB7vPvgQz/LDQiW5JDpmx+IbtSpjx0WtXMi5NrJnWKbTa9P1OiUtq LAwA= X-Developer-Key: i=charlie@rivosinc.com; a=openpgp; fpr=7D834FF11B1D8387E61C776FFB10D1F27D6B1354 Extend existing vector tests to be compatible with the xtheadvector instructions. Signed-off-by: Charlie Jenkins --- .../selftests/riscv/vector/v_exec_initval_nolibc.c | 23 ++++-- tools/testing/selftests/riscv/vector/v_helpers.c | 17 ++++- tools/testing/selftests/riscv/vector/v_helpers.h | 4 +- tools/testing/selftests/riscv/vector/v_initval.c | 12 ++- .../selftests/riscv/vector/vstate_exec_nolibc.c | 20 +++-- .../testing/selftests/riscv/vector/vstate_prctl.c | 89 ++++++++++++++----= ---- 6 files changed, 113 insertions(+), 52 deletions(-) diff --git a/tools/testing/selftests/riscv/vector/v_exec_initval_nolibc.c b= /tools/testing/selftests/riscv/vector/v_exec_initval_nolibc.c index 4a39cab29c34..35c0812e32de 100644 --- a/tools/testing/selftests/riscv/vector/v_exec_initval_nolibc.c +++ b/tools/testing/selftests/riscv/vector/v_exec_initval_nolibc.c @@ -18,13 +18,22 @@ int main(int argc, char **argv) unsigned long vl; int first =3D 1; =20 - asm volatile ( - ".option push\n\t" - ".option arch, +v\n\t" - "vsetvli %[vl], x0, e8, m1, ta, ma\n\t" - ".option pop\n\t" - : [vl] "=3Dr" (vl) - ); + if (argc > 2 && strcmp(argv[2], "x")) + asm volatile ( + // 0 | zimm[10:0] | rs1 | 1 1 1 | rd |1010111| vsetvli + // vsetvli t4, x0, e8, m1, d1 + ".4byte 0b00000000000000000111111011010111\n\t" + "mv %[vl], t4\n\t" + : [vl] "=3Dr" (vl) : : "t4" + ); + else + asm volatile ( + ".option push\n\t" + ".option arch, +v\n\t" + "vsetvli %[vl], x0, e8, m1, ta, ma\n\t" + ".option pop\n\t" + : [vl] "=3Dr" (vl) + ); =20 #define CHECK_VECTOR_REGISTER(register) ({ \ for (int i =3D 0; i < vl; i++) { \ diff --git a/tools/testing/selftests/riscv/vector/v_helpers.c b/tools/testi= ng/selftests/riscv/vector/v_helpers.c index d50f4dfbf9e5..01a8799dcb78 100644 --- a/tools/testing/selftests/riscv/vector/v_helpers.c +++ b/tools/testing/selftests/riscv/vector/v_helpers.c @@ -1,12 +1,22 @@ // SPDX-License-Identifier: GPL-2.0-only =20 #include "../hwprobe/hwprobe.h" +#include #include #include #include #include #include =20 +bool is_xtheadvector_supported(void) +{ + struct riscv_hwprobe pair; + + pair.key =3D RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0; + riscv_hwprobe(&pair, 1, 0, NULL, 0); + return pair.value & RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR; +} + bool is_vector_supported(void) { struct riscv_hwprobe pair; @@ -16,9 +26,9 @@ bool is_vector_supported(void) return pair.value & RISCV_HWPROBE_EXT_ZVE32X; } =20 -int launch_test(char *next_program, int test_inherit) +int launch_test(char *next_program, int test_inherit, int xtheadvector) { - char *exec_argv[3], *exec_envp[1]; + char *exec_argv[4], *exec_envp[1]; int rc, pid, status; =20 pid =3D fork(); @@ -30,7 +40,8 @@ int launch_test(char *next_program, int test_inherit) if (!pid) { exec_argv[0] =3D next_program; exec_argv[1] =3D test_inherit !=3D 0 ? "x" : NULL; - exec_argv[2] =3D NULL; + exec_argv[2] =3D xtheadvector !=3D 0 ? "x" : NULL; + exec_argv[3] =3D NULL; exec_envp[0] =3D NULL; /* launch the program again to check inherit */ rc =3D execve(next_program, exec_argv, exec_envp); diff --git a/tools/testing/selftests/riscv/vector/v_helpers.h b/tools/testi= ng/selftests/riscv/vector/v_helpers.h index faeeeb625b6e..763cddfe26da 100644 --- a/tools/testing/selftests/riscv/vector/v_helpers.h +++ b/tools/testing/selftests/riscv/vector/v_helpers.h @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include =20 +bool is_xtheadvector_supported(void); + bool is_vector_supported(void); =20 -int launch_test(char *next_program, int test_inherit); +int launch_test(char *next_program, int test_inherit, int xtheadvector); diff --git a/tools/testing/selftests/riscv/vector/v_initval.c b/tools/testi= ng/selftests/riscv/vector/v_initval.c index f38b5797fa31..be9e1d18ad29 100644 --- a/tools/testing/selftests/riscv/vector/v_initval.c +++ b/tools/testing/selftests/riscv/vector/v_initval.c @@ -7,10 +7,16 @@ =20 TEST(v_initval) { - if (!is_vector_supported()) - SKIP(return, "Vector not supported"); + int xtheadvector =3D 0; =20 - ASSERT_EQ(0, launch_test(NEXT_PROGRAM, 0)); + if (!is_vector_supported()) { + if (is_xtheadvector_supported()) + xtheadvector =3D 1; + else + SKIP(return, "Vector not supported"); + } + + ASSERT_EQ(0, launch_test(NEXT_PROGRAM, 0, xtheadvector)); } =20 TEST_HARNESS_MAIN diff --git a/tools/testing/selftests/riscv/vector/vstate_exec_nolibc.c b/to= ols/testing/selftests/riscv/vector/vstate_exec_nolibc.c index 1f9969bed235..7b7d6f21acb4 100644 --- a/tools/testing/selftests/riscv/vector/vstate_exec_nolibc.c +++ b/tools/testing/selftests/riscv/vector/vstate_exec_nolibc.c @@ -6,13 +6,16 @@ =20 int main(int argc, char **argv) { - int rc, pid, status, test_inherit =3D 0; + int rc, pid, status, test_inherit =3D 0, xtheadvector =3D 0; long ctrl, ctrl_c; char *exec_argv[2], *exec_envp[2]; =20 - if (argc > 1) + if (argc > 1 && strcmp(argv[1], "x")) test_inherit =3D 1; =20 + if (argc > 2 && strcmp(argv[2], "x")) + xtheadvector =3D 1; + ctrl =3D my_syscall1(__NR_prctl, PR_RISCV_V_GET_CONTROL); if (ctrl < 0) { puts("PR_RISCV_V_GET_CONTROL is not supported\n"); @@ -53,11 +56,14 @@ int main(int argc, char **argv) puts("child's vstate_ctrl not equal to parent's\n"); exit(-1); } - asm volatile (".option push\n\t" - ".option arch, +v\n\t" - "vsetvli x0, x0, e32, m8, ta, ma\n\t" - ".option pop\n\t" - ); + if (xtheadvector) + asm volatile (".4byte 0x00007ed7"); + else + asm volatile (".option push\n\t" + ".option arch, +v\n\t" + "vsetvli x0, x0, e32, m8, ta, ma\n\t" + ".option pop\n\t" + ); exit(ctrl); } } diff --git a/tools/testing/selftests/riscv/vector/vstate_prctl.c b/tools/te= sting/selftests/riscv/vector/vstate_prctl.c index 2fc86924bf42..62fbb17a0556 100644 --- a/tools/testing/selftests/riscv/vector/vstate_prctl.c +++ b/tools/testing/selftests/riscv/vector/vstate_prctl.c @@ -11,7 +11,7 @@ =20 #define NEXT_PROGRAM "./vstate_exec_nolibc" =20 -int test_and_compare_child(long provided, long expected, int inherit) +int test_and_compare_child(long provided, long expected, int inherit, int = xtheadvector) { int rc; =20 @@ -21,7 +21,7 @@ int test_and_compare_child(long provided, long expected, = int inherit) provided, rc); return -1; } - rc =3D launch_test(NEXT_PROGRAM, inherit); + rc =3D launch_test(NEXT_PROGRAM, inherit, xtheadvector); if (rc !=3D expected) { printf("Test failed, check %d !=3D %ld\n", rc, expected); return -2; @@ -36,7 +36,7 @@ TEST(get_control_no_v) { long rc; =20 - if (is_vector_supported()) + if (is_vector_supported() || is_xtheadvector_supported()) SKIP(return, "Test expects vector to be not supported"); =20 rc =3D prctl(PR_RISCV_V_GET_CONTROL); @@ -50,7 +50,7 @@ TEST(set_control_no_v) { long rc; =20 - if (is_vector_supported()) + if (is_vector_supported() || is_xtheadvector_supported()) SKIP(return, "Test expects vector to be not supported"); =20 rc =3D prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); @@ -65,12 +65,12 @@ TEST(vstate_on_current) long flag; long rc; =20 - if (!is_vector_supported()) + if (!is_vector_supported() && !is_xtheadvector_supported()) SKIP(return, "Vector not supported"); =20 flag =3D PR_RISCV_V_VSTATE_CTRL_ON; rc =3D prctl(PR_RISCV_V_SET_CONTROL, flag); - EXPECT_EQ(0, rc) TH_LOG("Enabling V for current should always success"); + EXPECT_EQ(0, rc) TH_LOG("Enabling V for current should always succeed"); } =20 TEST(vstate_off_eperm) @@ -78,7 +78,7 @@ TEST(vstate_off_eperm) long flag; long rc; =20 - if (!is_vector_supported()) + if (!is_vector_supported() && !is_xtheadvector_supported()) SKIP(return, "Vector not supported"); =20 flag =3D PR_RISCV_V_VSTATE_CTRL_OFF; @@ -92,89 +92,116 @@ TEST(vstate_off_eperm) TEST(vstate_on_no_nesting) { long flag; + int xtheadvector =3D 0; =20 - if (!is_vector_supported()) - SKIP(return, "Vector not supported"); + if (!is_vector_supported()) { + if (is_xtheadvector_supported()) + xtheadvector =3D 1; + else + SKIP(return, "Vector not supported"); + } =20 /* Turn on next's vector explicitly and test */ flag =3D PR_RISCV_V_VSTATE_CTRL_ON << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; =20 - EXPECT_EQ(0, - test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_ON, 0)); + EXPECT_EQ(0, test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_ON, 0, x= theadvector)); } =20 TEST(vstate_off_nesting) { long flag; + int xtheadvector =3D 0; =20 - if (!is_vector_supported()) - SKIP(return, "Vector not supported"); + if (!is_vector_supported()) { + if (is_xtheadvector_supported()) + xtheadvector =3D 1; + else + SKIP(return, "Vector not supported"); + } =20 /* Turn off next's vector explicitly and test */ flag =3D PR_RISCV_V_VSTATE_CTRL_OFF << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; =20 - EXPECT_EQ(0, - test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_OFF, 1)); + EXPECT_EQ(0, test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_OFF, 1, = xtheadvector)); } =20 TEST(vstate_on_inherit_no_nesting) { long flag, expected; + int xtheadvector =3D 0; =20 - if (!is_vector_supported()) - SKIP(return, "Vector not supported"); + if (!is_vector_supported()) { + if (is_xtheadvector_supported()) + xtheadvector =3D 1; + else + SKIP(return, "Vector not supported"); + } =20 /* Turn on next's vector explicitly and test no inherit */ flag =3D PR_RISCV_V_VSTATE_CTRL_ON << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; flag |=3D PR_RISCV_V_VSTATE_CTRL_INHERIT; expected =3D flag | PR_RISCV_V_VSTATE_CTRL_ON; =20 - EXPECT_EQ(0, test_and_compare_child(flag, expected, 0)); + EXPECT_EQ(0, test_and_compare_child(flag, expected, 0, xtheadvector)); } =20 TEST(vstate_on_inherit) { long flag, expected; + int xtheadvector =3D 0; =20 - if (!is_vector_supported()) - SKIP(return, "Vector not supported"); + if (!is_vector_supported()) { + if (is_xtheadvector_supported()) + xtheadvector =3D 1; + else + SKIP(return, "Vector not supported"); + } =20 /* Turn on next's vector explicitly and test inherit */ flag =3D PR_RISCV_V_VSTATE_CTRL_ON << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; flag |=3D PR_RISCV_V_VSTATE_CTRL_INHERIT; expected =3D flag | PR_RISCV_V_VSTATE_CTRL_ON; =20 - EXPECT_EQ(0, test_and_compare_child(flag, expected, 1)); + EXPECT_EQ(0, test_and_compare_child(flag, expected, 1, xtheadvector)); } =20 TEST(vstate_off_inherit_no_nesting) { long flag, expected; + int xtheadvector =3D 0; =20 - if (!is_vector_supported()) - SKIP(return, "Vector not supported"); - + if (!is_vector_supported()) { + if (is_xtheadvector_supported()) + xtheadvector =3D 1; + else + SKIP(return, "Vector not supported"); + } /* Turn off next's vector explicitly and test no inherit */ flag =3D PR_RISCV_V_VSTATE_CTRL_OFF << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; flag |=3D PR_RISCV_V_VSTATE_CTRL_INHERIT; expected =3D flag | PR_RISCV_V_VSTATE_CTRL_OFF; =20 - EXPECT_EQ(0, test_and_compare_child(flag, expected, 0)); + EXPECT_EQ(0, test_and_compare_child(flag, expected, 0, xtheadvector)); } =20 TEST(vstate_off_inherit) { long flag, expected; + int xtheadvector =3D 0; =20 - if (!is_vector_supported()) - SKIP(return, "Vector not supported"); + if (!is_vector_supported()) { + if (is_xtheadvector_supported()) + xtheadvector =3D 1; + else + SKIP(return, "Vector not supported"); + } =20 /* Turn off next's vector explicitly and test inherit */ flag =3D PR_RISCV_V_VSTATE_CTRL_OFF << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; flag |=3D PR_RISCV_V_VSTATE_CTRL_INHERIT; expected =3D flag | PR_RISCV_V_VSTATE_CTRL_OFF; =20 - EXPECT_EQ(0, test_and_compare_child(flag, expected, 1)); + EXPECT_EQ(0, test_and_compare_child(flag, expected, 1, xtheadvector)); } =20 /* arguments should fail with EINVAL */ @@ -182,7 +209,7 @@ TEST(inval_set_control_1) { int rc; =20 - if (!is_vector_supported()) + if (!is_vector_supported() && !is_xtheadvector_supported()) SKIP(return, "Vector not supported"); =20 rc =3D prctl(PR_RISCV_V_SET_CONTROL, 0xff0); @@ -195,7 +222,7 @@ TEST(inval_set_control_2) { int rc; =20 - if (!is_vector_supported()) + if (!is_vector_supported() && !is_xtheadvector_supported()) SKIP(return, "Vector not supported"); =20 rc =3D prctl(PR_RISCV_V_SET_CONTROL, 0x3); @@ -208,7 +235,7 @@ TEST(inval_set_control_3) { int rc; =20 - if (!is_vector_supported()) + if (!is_vector_supported() && !is_xtheadvector_supported()) SKIP(return, "Vector not supported"); =20 rc =3D prctl(PR_RISCV_V_SET_CONTROL, 0xc); --=20 2.45.0 From nobody Sat Nov 30 03:28:39 2024 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86FC8195980 for ; Thu, 12 Sep 2024 05:56:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120577; cv=none; b=qMj26jbBJv/j9U7muFCCuoCxAi+uNFj2iBWJC6l0XG5bYHKneO/8Ryunv/5Wx5h3sp51PxD6qG9HPzhzp52Ard8qrVQswiMD2om4/gObJzfomHtFrrLt5TNfjV+fJ6pz1h/P84i5wtX+Xx1QKjwOQhvQYLMqGzFJe4QdwPfr9l0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726120577; c=relaxed/simple; bh=2MZb8AJQZs0wG05Wps2DKInawqFPfqgCL1L5PflC7B4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qbZDLmAopPgCveX3+5Yf5eKaHc/c4B2Ns+j8zQGgnOKCyWMXcQ3lMzcflB4eBrYcUzPY/nh1hzI1iccwtXxs3XhKTiP15A77yKmtMURx68QSKbtIkxHXpo0i7/xV7f0yna/IWSbMXLtZy+lzyX7nBtv3l8s0xXnZHWQj5fJfAZo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=hyDPEtRC; arc=none smtp.client-ip=209.85.214.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="hyDPEtRC" Received: by mail-pl1-f169.google.com with SMTP id d9443c01a7336-2068a7c9286so6959485ad.1 for ; Wed, 11 Sep 2024 22:56:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1726120575; x=1726725375; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=lZGiXXErbLpwtJqQgRszC/20gA32B7VjfeYUlTIyz2Y=; b=hyDPEtRC1YSt8HY3ToJaylrg4hdczZZ7pciTOXe+yihIExv3zUrO8PnhsYZbWaRyMA vHbQFClUH8soXWFxs1mFaHU5YqJ61s+BSVUu84mqvPNaMgeIOUXTbx/W6yQPlvgSU+as 3KEU2sKqXGjI3HBAHWUmZVOKie3tji/kp3kkK2itynJ9XFrRNWy8Odton1NaE79ODav7 iUPTYb8YC/THRXe04ylG9vB+MIknaT30hCo0bX5xaeW7D41oBOfZbSn+P4HpTeRTJ0rs I3n6S60AuXHDo0CBJ41Xe50BQBzby8JPLIureTLUQWFWKUIF9WXtuLvDMX34OTpppE5S XyEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726120575; x=1726725375; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lZGiXXErbLpwtJqQgRszC/20gA32B7VjfeYUlTIyz2Y=; b=jk+pHMRxR7X92ZBi+15ZYJNGkcVNZBVWijqKYcyvjEiq02d3JE5H5eAqcHdBu1UUBO Cikvckk0S/M+ivqQ83f0/euoKKla2HmnJBDnl3+QNcudfvc397QErqUeoYO4wdO47ZUR b+2Xbkm1uQJJV/RaGELoZyaV+kKTUAzAuIVpAlUUcZfxmOlBn/tPR+psnqJOb+zgaEI4 UmsH7xpLpXt7/X4mnKvesNjCILPz7ZiR1tW9yH1MX2RBFPJkPW03rsdklcaicr3Y7cEq uJ1tD/sqDbeWpngqcxefscj5c9IUue1yhr7pLS7RbFugP4SG4oFVXmBedABTIh9fBosR Vuog== X-Forwarded-Encrypted: i=1; AJvYcCWmStnRNdfZRxPPjkVyZcZl+2LtSBdOnsWko0oZBCbhvGtiDwDo32Z6VQpcDkqm1s2VwZQMHuVh9/oymUg=@vger.kernel.org X-Gm-Message-State: AOJu0YyhE8cyK/FT1B0jubM4TxxJ84Mr8hFiYKCF/u0rqjpQ63KHQC3C WtojQXEGdYtN0uda6bS6ZOmi5uOxYwpcIG5EXUP9IiXibpBIyWYLX887KOrYQZM= X-Google-Smtp-Source: AGHT+IEP6KKwUZUW8OkMBb/fzUUdV4ELJioR4iSAdt1JCFUkRDRHnlZjxlI1+ScQqzaBoVsDlqO0MA== X-Received: by 2002:a17:902:e852:b0:205:8407:6321 with SMTP id d9443c01a7336-2076e32e467mr26718025ad.9.1726120574663; Wed, 11 Sep 2024 22:56:14 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe99b6sm7870465ad.209.2024.09.11.22.56.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 22:56:13 -0700 (PDT) From: Charlie Jenkins Date: Wed, 11 Sep 2024 22:55:22 -0700 Subject: [PATCH v10 14/14] riscv: Add ghostwrite vulnerability Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240911-xtheadvector-v10-14-8d3930091246@rivosinc.com> References: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> In-Reply-To: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=9377; i=charlie@rivosinc.com; h=from:subject:message-id; bh=2MZb8AJQZs0wG05Wps2DKInawqFPfqgCL1L5PflC7B4=; b=owGbwMvMwCHWx5hUnlvL8Y3xtFoSQ9qjptiFMw5nP9trcGhyZOLbtRZvpOqP7b6X2+nx55Y4v 1rzq847HaUsDGIcDLJiiiw81xqYW+/olx0VLZsAM4eVCWQIAxenAEzkRikjw8kZu9hvVjGoXk3b vvRgabHQ1BfzTnhorbhbdZajvjUkTp7hf/4B+f1yv02/VcdquBxsSyl53Xbll6Ms+zxRa+/jDSu DWAE= X-Developer-Key: i=charlie@rivosinc.com; a=openpgp; fpr=7D834FF11B1D8387E61C776FFB10D1F27D6B1354 Follow the patterns of the other architectures that use GENERIC_CPU_VULNERABILITIES for riscv to introduce the ghostwrite vulnerability and mitigation. The mitigation is to disable all vector which is accomplished by clearing the bit from the cpufeature field. Ghostwrite only affects thead c9xx CPUs that impelment xtheadvector, so the vulerability will only be mitigated on these CPUs. Signed-off-by: Charlie Jenkins --- arch/riscv/Kconfig.errata | 11 ++++++++ arch/riscv/errata/thead/errata.c | 28 ++++++++++++++++++ arch/riscv/include/asm/bugs.h | 22 +++++++++++++++ arch/riscv/include/asm/errata_list.h | 3 +- arch/riscv/kernel/Makefile | 2 ++ arch/riscv/kernel/bugs.c | 55 ++++++++++++++++++++++++++++++++= ++++ arch/riscv/kernel/cpufeature.c | 9 +++++- drivers/base/cpu.c | 3 ++ include/linux/cpu.h | 1 + 9 files changed, 132 insertions(+), 2 deletions(-) diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index 2acc7d876e1f..e318119d570d 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -119,4 +119,15 @@ config ERRATA_THEAD_PMU =20 If you don't know what to do here, say "Y". =20 +config ERRATA_THEAD_GHOSTWRITE + bool "Apply T-Head Ghostwrite errata" + depends on ERRATA_THEAD && RISCV_ISA_XTHEADVECTOR + default y + help + The T-Head C9xx cores have a vulnerability in the xtheadvector + instruction set. When this errata is enabled, the CPUs will be probed + to determine if they are vulnerable and disable xtheadvector. + + If you don't know what to do here, say "Y". + endmenu # "CPU errata selection" diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/err= ata.c index f5120e07c318..5cc008ab41a8 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -142,6 +143,31 @@ static bool errata_probe_pmu(unsigned int stage, return true; } =20 +static bool errata_probe_ghostwrite(unsigned int stage, + unsigned long arch_id, unsigned long impid) +{ + if (!IS_ENABLED(CONFIG_ERRATA_THEAD_GHOSTWRITE)) + return false; + + /* + * target-c9xx cores report arch_id and impid as 0 + * + * While ghostwrite may not affect all c9xx cores that implement + * xtheadvector, there is no futher granularity than c9xx. Assume + * vulnerable for this entire class of processors when xtheadvector is + * enabled. + */ + if (arch_id !=3D 0 || impid !=3D 0) + return false; + + if (stage !=3D RISCV_ALTERNATIVES_EARLY_BOOT) + return false; + + ghostwrite_set_vulnerable(); + + return true; +} + static u32 thead_errata_probe(unsigned int stage, unsigned long archid, unsigned long impid) { @@ -155,6 +181,8 @@ static u32 thead_errata_probe(unsigned int stage, if (errata_probe_pmu(stage, archid, impid)) cpu_req_errata |=3D BIT(ERRATA_THEAD_PMU); =20 + errata_probe_ghostwrite(stage, archid, impid); + return cpu_req_errata; } =20 diff --git a/arch/riscv/include/asm/bugs.h b/arch/riscv/include/asm/bugs.h new file mode 100644 index 000000000000..e294b15bf78e --- /dev/null +++ b/arch/riscv/include/asm/bugs.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Interface for managing mitigations for riscv vulnerabilities. + * + * Copyright (C) 2024 Rivos Inc. + */ + +#ifndef __ASM_BUGS_H +#define __ASM_BUGS_H + +/* Watch out, ordering is important here. */ +enum mitigation_state { + UNAFFECTED, + MITIGATED, + VULNERABLE, +}; + +void ghostwrite_set_vulnerable(void); +void ghostwrite_enable_mitigation(void); +enum mitigation_state ghostwrite_get_state(void); + +#endif /* __ASM_BUGS_H */ diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/= errata_list.h index 7c8a71a526a3..6e426ed7919a 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -25,7 +25,8 @@ #ifdef CONFIG_ERRATA_THEAD #define ERRATA_THEAD_MAE 0 #define ERRATA_THEAD_PMU 1 -#define ERRATA_THEAD_NUMBER 2 +#define ERRATA_THEAD_GHOSTWRITE 2 +#define ERRATA_THEAD_NUMBER 3 #endif =20 #ifdef __ASSEMBLY__ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 06d407f1b30b..d7a54e34178e 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -113,3 +113,5 @@ obj-$(CONFIG_COMPAT) +=3D compat_vdso/ obj-$(CONFIG_64BIT) +=3D pi/ obj-$(CONFIG_ACPI) +=3D acpi.o obj-$(CONFIG_ACPI_NUMA) +=3D acpi_numa.o + +obj-$(CONFIG_GENERIC_CPU_VULNERABILITIES) +=3D bugs.o diff --git a/arch/riscv/kernel/bugs.c b/arch/riscv/kernel/bugs.c new file mode 100644 index 000000000000..0c19691b4cd5 --- /dev/null +++ b/arch/riscv/kernel/bugs.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Rivos Inc. + */ + +#include +#include +#include + +#include +#include + +static enum mitigation_state ghostwrite_state; + +void ghostwrite_set_vulnerable(void) +{ + ghostwrite_state =3D VULNERABLE; +} + +/* + * Vendor extension alternatives will use the value set at the time of boot + * alternative patching, thus this must be called before boot alternatives= are + * patched (and after extension probing) to be effective. + */ +void ghostwrite_enable_mitigation(void) +{ + if (IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR) && + ghostwrite_state =3D=3D VULNERABLE && !cpu_mitigations_off()) { + disable_xtheadvector(); + ghostwrite_state =3D MITIGATED; + } +} + +enum mitigation_state ghostwrite_get_state(void) +{ + return ghostwrite_state; +} + +ssize_t cpu_show_ghostwrite(struct device *dev, struct device_attribute *a= ttr, char *buf) +{ + if (IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR)) { + switch (ghostwrite_state) { + case UNAFFECTED: + return sprintf(buf, "Not affected\n"); + case MITIGATED: + return sprintf(buf, "Mitigation: xtheadvector disabled\n"); + case VULNERABLE: + fallthrough; + default: + return sprintf(buf, "Vulnerable\n"); + } + } else { + return sprintf(buf, "Not affected\n"); + } +} diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 56b5054b8f86..1f4329bb8a9d 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -867,7 +868,13 @@ static int __init riscv_fill_hwcap_from_ext_list(unsig= ned long *isa2hwcap) riscv_fill_vendor_ext_list(cpu); } =20 - if (has_xtheadvector_no_alternatives() && has_thead_homogeneous_vlenb() <= 0) { + /* + * Execute ghostwrite mitigation immediately after detecting extensions + * to disable xtheadvector if necessary. + */ + if (ghostwrite_get_state() =3D=3D VULNERABLE) { + ghostwrite_enable_mitigation(); + } else if (has_xtheadvector_no_alternatives() && has_thead_homogeneous_vl= enb() < 0) { pr_warn("Unsupported heterogeneous vlenb detected, vector extension disa= bled.\n"); disable_xtheadvector(); } diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c index fdaa24bb641a..a7e511849875 100644 --- a/drivers/base/cpu.c +++ b/drivers/base/cpu.c @@ -599,6 +599,7 @@ CPU_SHOW_VULN_FALLBACK(retbleed); CPU_SHOW_VULN_FALLBACK(spec_rstack_overflow); CPU_SHOW_VULN_FALLBACK(gds); CPU_SHOW_VULN_FALLBACK(reg_file_data_sampling); +CPU_SHOW_VULN_FALLBACK(ghostwrite); =20 static DEVICE_ATTR(meltdown, 0444, cpu_show_meltdown, NULL); static DEVICE_ATTR(spectre_v1, 0444, cpu_show_spectre_v1, NULL); @@ -614,6 +615,7 @@ static DEVICE_ATTR(retbleed, 0444, cpu_show_retbleed, N= ULL); static DEVICE_ATTR(spec_rstack_overflow, 0444, cpu_show_spec_rstack_overfl= ow, NULL); static DEVICE_ATTR(gather_data_sampling, 0444, cpu_show_gds, NULL); static DEVICE_ATTR(reg_file_data_sampling, 0444, cpu_show_reg_file_data_sa= mpling, NULL); +static DEVICE_ATTR(ghostwrite, 0444, cpu_show_ghostwrite, NULL); =20 static struct attribute *cpu_root_vulnerabilities_attrs[] =3D { &dev_attr_meltdown.attr, @@ -630,6 +632,7 @@ static struct attribute *cpu_root_vulnerabilities_attrs= [] =3D { &dev_attr_spec_rstack_overflow.attr, &dev_attr_gather_data_sampling.attr, &dev_attr_reg_file_data_sampling.attr, + &dev_attr_ghostwrite.attr, NULL }; =20 diff --git a/include/linux/cpu.h b/include/linux/cpu.h index bdcec1732445..6a0a8f1c7c90 100644 --- a/include/linux/cpu.h +++ b/include/linux/cpu.h @@ -77,6 +77,7 @@ extern ssize_t cpu_show_gds(struct device *dev, struct device_attribute *attr, char *buf); extern ssize_t cpu_show_reg_file_data_sampling(struct device *dev, struct device_attribute *attr, char *buf); +extern ssize_t cpu_show_ghostwrite(struct device *dev, struct device_attri= bute *attr, char *buf); =20 extern __printf(4, 5) struct device *cpu_device_create(struct device *parent, void *drvdata, --=20 2.45.0