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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Convert the Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Controller to dt-schema. Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Reviewed-by: Rob Herring (Arm) --- .../bindings/clock/amlogic,meson8-clkc.yaml | 45 +++++++++++++++++++ .../bindings/clock/amlogic,meson8b-clkc.txt | 51 ------------------= ---- 2 files changed, 45 insertions(+), 51 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8-clkc.ya= ml b/Documentation/devicetree/bindings/clock/amlogic,meson8-clkc.yaml new file mode 100644 index 000000000000..ab73d4654171 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8-clkc.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,meson8-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Controller + +maintainers: + - Neil Armstrong + +properties: + compatible: + oneOf: + - enum: + - amlogic,meson8-clkc + - amlogic,meson8b-clkc + - items: + - const: amlogic,meson8m2-clkc + - const: amlogic,meson8-clkc + + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + minItems: 2 + items: + - const: xtal + - const: ddr_pll + - const: clk_32k + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - clocks + - clock-names + - '#reset-cells' + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.t= xt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt deleted file mode 100644 index cc51e4746b3b..000000000000 --- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt +++ /dev/null @@ -1,51 +0,0 @@ -* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit - -The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and -supplies clock to various controllers within the SoC. - -Required Properties: - -- compatible: must be one of: - - "amlogic,meson8-clkc" for Meson8 (S802) SoCs - - "amlogic,meson8b-clkc" for Meson8 (S805) SoCs - - "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs -- #clock-cells: should be 1. -- #reset-cells: should be 1. -- clocks: list of clock phandles, one for each entry in clock-names -- clock-names: should contain the following: - * "xtal": the 24MHz system oscillator - * "ddr_pll": the DDR PLL clock - * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_= IN) - -Parent node should have the following properties : -- compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon" -- reg: base address and size of the HHI system control register space. - -Each clock is assigned an identifier and client nodes can use this identif= ier -to specify the clock which they consume. All available clocks are defined = as -preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can= be -used in device tree sources. - -Similarly a preprocessor macro for each reset line is defined in -dt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the -device tree sources). - - -Example: Clock controller node: - - clkc: clock-controller { - compatible =3D "amlogic,meson8b-clkc"; - #clock-cells =3D <1>; - #reset-cells =3D <1>; - }; - - -Example: UART controller node that consumes the clock generated by the clo= ck - controller: - - uart_AO: serial@c81004c0 { - compatible =3D "amlogic,meson-uart"; - reg =3D <0xc81004c0 0x14>; - interrupts =3D <0 90 1>; - clocks =3D <&clkc CLKID_CLK81>; - }; --- base-commit: 47ac09b91befbb6a235ab620c32af719f8208399 change-id: 20240911-topic-amlogic-arm32-upstream-bindings-fixes-convert-mes= on8-clkc-7dec15a0a5f0 Best regards, --=20 Neil Armstrong