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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Tengfei Fan --- include/dt-bindings/arm/qcom,ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/q= com,ids.h index 8332f8d82f96..c187a60d4d1f 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -276,6 +276,7 @@ #define QCOM_ID_QCM8550 604 #define QCOM_ID_IPQ5300 624 #define QCOM_ID_IPQ5321 650 +#define QCOM_ID_QCS9100 667 #define QCOM_ID_QCS8300 674 #define QCOM_ID_QCS8275 675 =20 --=20 2.25.1 From nobody Sat Nov 30 05:34:35 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F3189188013; Wed, 11 Sep 2024 11:11:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; 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QCS9100 is a IoT version of SA8775p, hence use the latter's compatible string as fallback. Signed-off-by: Tengfei Fan Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/qcom.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 5cb54d69af0b..b0ba422eec71 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -45,6 +45,7 @@ description: | qcs8550 qcm2290 qcm6490 + qcs9100 qdu1000 qrb2210 qrb4210 @@ -912,6 +913,13 @@ properties: - qcom,sa8775p-ride-r3 - const: qcom,sa8775p =20 + - items: + - enum: + - qcom,qcs9100-ride + - qcom,qcs9100-ride-r3 + - const: qcom,qcs9100 + - const: qcom,sa8775p + - items: - enum: - google,cheza --=20 2.25.1 From nobody Sat Nov 30 05:34:35 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6D9418EFE6; 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Wed, 11 Sep 2024 11:11:23 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48BBBMtu008845 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 11 Sep 2024 11:11:22 GMT Received: from tengfan-gv.ap.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Sep 2024 04:11:17 -0700 From: Tengfei Fan Date: Wed, 11 Sep 2024 19:10:58 +0800 Subject: [PATCH v2 4/4] arm64: dts: qcom: qcs9100: Add support for the QCS9100 Ride and Ride Rev3 boards Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240911-add_qcs9100_support-v2-4-e43a71ceb017@quicinc.com> References: <20240911-add_qcs9100_support-v2-0-e43a71ceb017@quicinc.com> In-Reply-To: <20240911-add_qcs9100_support-v2-0-e43a71ceb017@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , Tengfei Fan X-Mailer: b4 0.15-dev-a66ce X-Developer-Signature: v=1; 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The QCS9100 is a variant of the SA8775p, and they are fully compatible with each other. The QCS9100 Ride/Ride Rev3 board is essentially the same as the SA8775p Ride/Ride Rev3 board, with the QCS9100 SoC mounted instead of the SA8775p. Signed-off-by: Tengfei Fan Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/Makefile | 2 ++ arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts | 11 +++++++++++ arch/arm64/boot/dts/qcom/qcs9100-ride.dts | 11 +++++++++++ 3 files changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index ae002c7cf126..b3c369305731 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -112,6 +112,8 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs6490-rb3gen2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-aim300-aiot.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9100-ride.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9100-ride-r3.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qdu1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qrb2210-rb1.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qrb4210-rb2.dtb diff --git a/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts b/arch/arm64/boot= /dts/qcom/qcs9100-ride-r3.dts new file mode 100644 index 000000000000..759d1ec694b2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ +/dts-v1/; + +#include "sa8775p-ride-r3.dts" +/ { + model =3D "Qualcomm QCS9100 Ride Rev3"; + compatible =3D "qcom,qcs9100-ride-r3", "qcom,qcs9100", "qcom,sa8775p"; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs9100-ride.dts b/arch/arm64/boot/dt= s/qcom/qcs9100-ride.dts new file mode 100644 index 000000000000..979462dfec30 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs9100-ride.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ +/dts-v1/; + +#include "sa8775p-ride.dts" +/ { + model =3D "Qualcomm QCS9100 Ride"; + compatible =3D "qcom,qcs9100-ride", "qcom,qcs9100", "qcom,sa8775p"; +}; --=20 2.25.1