From nobody Sat Nov 30 10:53:03 2024 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2E3F170A2B for ; Tue, 10 Sep 2024 18:16:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.203.77.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725992203; cv=none; b=HGxA4pqFZdsYqXoXBsiDjWisPjmqvRyK4Bi5scLIrN9GSf6CKwX7oK746OKL/SWO0tx4YwbbuMvD+AjwTQ2+CNbMWkPABn3EeoUBYwlHvmwS/Cr6XtrNPgCoa6QjOko7VLKKvUelZYSzqP+E63xFsykGj7ZjYwlWy4ZkK8O2KxU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725992203; c=relaxed/simple; bh=iPI9JMCgSWWidI+HW82ggnJaGnrlOTN4Ozvuwagp7u8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gQJwXO1RA4pJ9CdpT8y+tD6oK8yD9zArT9Z5Oy6Y7fX0xTSpwRVStUvOXh5lsezv5YMTs/P/P6TTV+GhrvtZMu7C+RnoGOF+fJ+7rGS/xCIITs0qsF35Ow5pQJXBIROQQcTy1xIUfJlL0ILXt7ZUZ5rHB/H0fWlf2NJfUDgqF4o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de; spf=fail smtp.mailfrom=fris.de; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b=En0VR6cK; arc=none smtp.client-ip=116.203.77.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=fris.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="En0VR6cK" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 01198BFB09; Tue, 10 Sep 2024 20:16:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1725992199; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=lRrN4PAU2l7OJC8sxx1hbjfmdyyjIZeE6QJ3Tin7hsU=; b=En0VR6cKYZksf0bzopn3Ltb94zOS4gvpoEwQsGyQBrzn499j1x4jVquVdwkxqcnxXvIdFN syIch3T7psqbftlssn//KosSt0dkEZO0eQD45rN3yPb0MRThKePfYibAB21kh8c7KzGfi8 M2Zk5qREdyjV5zUkW8wibCLTlTXQNF+/E5SKP7QYHcacaY+o/s/qbetMDE2Hjh5zn6Aa80 3E6C4l/aTSUMljfvzHUYfQhHl6p2y+b6vuULgK57xlQUGr4uc8ABSv7nX1gftTMcZjNU95 U9kJTHymbBeSO1hnFasHyLZwbDLJIFuHrJZ7Yt7CWm/hEPhw5e3xCYRuUbD+8w== From: Frieder Schrempf To: Kishon Vijay Abraham I , linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Vinod Koul Cc: Dominique Martinet , Frieder Schrempf , Adam Ford , Lucas Stach , Marco Felsch , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Subject: [PATCH 2/2] phy: freescale: fsl-samsung-hdmi: Add PLL LUT entries for some non-CEA-861 modes Date: Tue, 10 Sep 2024 20:14:53 +0200 Message-ID: <20240910181544.214797-3-frieder@fris.de> In-Reply-To: <20240910181544.214797-1-frieder@fris.de> References: <20240910181544.214797-1-frieder@fris.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" In order to support some pixel clock values not specified in CEA-861 and not achievable by the integer PLL algorithm, we add some new LUT entries. This allows to use the fractional-N PLL to achieve pixel clocks of 75 MHz, 88.75 MHz and 296.703 MHz with high accuracy. Signed-off-by: Frieder Schrempf --- drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/fre= escale/phy-fsl-samsung-hdmi.c index 401178bfcdda..6b36318630b2 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -156,6 +156,9 @@ static const struct phy_config phy_pll_cfg[] =3D { }, { .pixclk =3D 74250000, .pll_div_regs =3D { 0xd1, 0x5c, 0x52, 0x90, 0x0d, 0x84, 0x41 }, + }, { + .pixclk =3D 75000000, + .pll_div_regs =3D { 0xD1, 0x3E, 0x30, 0x9F, 0x0E, 0x82, 0x41 }, }, { .pixclk =3D 78500000, .pll_div_regs =3D { 0xd1, 0x62, 0x54, 0x87, 0x01, 0x80, 0x40 }, @@ -165,6 +168,9 @@ static const struct phy_config phy_pll_cfg[] =3D { }, { .pixclk =3D 82500000, .pll_div_regs =3D { 0xd1, 0x67, 0x54, 0x88, 0x01, 0x90, 0x49 }, + }, { + .pixclk =3D 88750000, + .pll_div_regs =3D { 0xD1, 0x6E, 0x50, 0x8B, 0x06, 0x81, 0x40 }, }, { .pixclk =3D 89000000, .pll_div_regs =3D { 0xd1, 0x70, 0x54, 0x84, 0x83, 0x80, 0x40 }, @@ -277,6 +283,9 @@ static const struct phy_config phy_pll_cfg[] =3D { .pixclk =3D 277500000, .pll_div_regs =3D { 0xd1, 0x73, 0x15, 0x88, 0x05, 0x90, 0x4d }, }, { + .pixclk =3D 296703000, + .pll_div_regs =3D { 0xd1, 0x7b, 0x18, 0xe0, 0x3d, 0x8a, 0x41 }, + }, { .pixclk =3D 297000000, .pll_div_regs =3D { 0xd1, 0x7b, 0x15, 0x84, 0x03, 0x90, 0x45 }, }, --=20 2.46.0