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Tue, 10 Sep 2024 15:19:18 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id +ObYOHZj4GaxQgAAD6G6ig (envelope-from ); Tue, 10 Sep 2024 15:19:18 +0000 From: Stanimir Varbanov To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Broadcom internal kernel review list Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Jim Quinlan , Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , kw@linux.com, Philipp Zabel , Andrea della Porta , Phil Elwell , Jonathan Bell , Stanimir Varbanov Subject: [PATCH v2 -next 09/11] PCI: brcmstb: Reuse config structure Date: Tue, 10 Sep 2024 18:18:43 +0300 Message-ID: <20240910151845.17308-10-svarbanov@suse.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240910151845.17308-1-svarbanov@suse.de> References: <20240910151845.17308-1-svarbanov@suse.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Level: X-Spamd-Result: default: False [-5.30 / 50.00]; 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Signed-off-by: Stanimir Varbanov Reviewed-by: Florian Fainelil --- drivers/pci/controller/pcie-brcmstb.c | 76 ++++++++++++--------------- 1 file changed, 33 insertions(+), 43 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 43d071d12201..caf2b8b63f75 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -191,11 +191,11 @@ #define SSC_STATUS_PLL_LOCK_MASK 0x800 #define PCIE_BRCM_MAX_MEMC 3 =20 -#define IDX_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_INDEX]) -#define DATA_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_DATA]) -#define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->reg_offsets[RGR1_SW_INIT_1]) -#define HARD_DEBUG(pcie) ((pcie)->reg_offsets[PCIE_HARD_DEBUG]) -#define INTR2_CPU_BASE(pcie) ((pcie)->reg_offsets[PCIE_INTR2_CPU_BASE]) +#define IDX_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_INDEX]) +#define DATA_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_DATA]) +#define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->cfg->offsets[RGR1_SW_INIT_1]) +#define HARD_DEBUG(pcie) ((pcie)->cfg->offsets[PCIE_HARD_DEBUG]) +#define INTR2_CPU_BASE(pcie) ((pcie)->cfg->offsets[PCIE_INTR2_CPU_BASE]) =20 /* Rescal registers */ #define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700 @@ -283,8 +283,6 @@ struct brcm_pcie { int gen; u64 msi_target_addr; struct brcm_msi *msi; - const int *reg_offsets; - enum pcie_soc_base soc_base; struct reset_control *rescal; struct reset_control *perst_reset; struct reset_control *bridge_reset; @@ -292,18 +290,14 @@ struct brcm_pcie { int num_memc; u64 memc_size[PCIE_BRCM_MAX_MEMC]; u32 hw_rev; - int (*perst_set)(struct brcm_pcie *pcie, u32 val); - int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); struct subdev_regulators *sr; bool ep_wakeup_capable; - bool has_phy; - u32 quirks; - u8 num_inbound_wins; + const struct pcie_cfg_data *cfg; }; =20 static inline bool is_bmips(const struct brcm_pcie *pcie) { - return pcie->soc_base =3D=3D BCM7435 || pcie->soc_base =3D=3D BCM7425; + return pcie->cfg->soc_base =3D=3D BCM7435 || pcie->cfg->soc_base =3D=3D B= CM7425; } =20 /* @@ -863,7 +857,7 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie = *pcie, * security considerations, and is not implemented in our modern * SoCs. */ - if (pcie->soc_base !=3D BCM7712) + if (pcie->cfg->soc_base !=3D BCM7712) add_inbound_win(b++, &n, 0, 0, 0); =20 resource_list_for_each_entry(entry, &bridge->dma_ranges) { @@ -880,10 +874,10 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pci= e *pcie, * That being said, each BARs size must still be a power of * two. */ - if (pcie->soc_base =3D=3D BCM7712) + if (pcie->cfg->soc_base =3D=3D BCM7712) add_inbound_win(b++, &n, size, cpu_start, pcie_start); =20 - if (n > pcie->num_inbound_wins) + if (n > pcie->cfg->num_inbound_wins) break; } =20 @@ -897,7 +891,7 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie = *pcie, * that enables multiple memory controllers. As such, it can return * now w/o doing special configuration. */ - if (pcie->soc_base =3D=3D BCM7712) + if (pcie->cfg->soc_base =3D=3D BCM7712) return n; =20 ret =3D of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", p= cie->memc_size, 1, @@ -1020,7 +1014,7 @@ static void set_inbound_win_registers(struct brcm_pci= e *pcie, * 7712: * All of their BARs need to be set. */ - if (pcie->soc_base =3D=3D BCM7712) { + if (pcie->cfg->soc_base =3D=3D BCM7712) { /* BUS remap register settings */ reg_offset =3D brcm_ubus_reg_offset(i); tmp =3D lower_32_bits(cpu_addr) & ~0xfff; @@ -1043,15 +1037,15 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) int memc, ret; =20 /* Reset the bridge */ - ret =3D pcie->bridge_sw_init_set(pcie, 1); + ret =3D pcie->cfg->bridge_sw_init_set(pcie, 1); if (ret) return ret; =20 /* Ensure that PERST# is asserted; some bootloaders may deassert it. */ - if (pcie->soc_base =3D=3D BCM2711) { - ret =3D pcie->perst_set(pcie, 1); + if (pcie->cfg->soc_base =3D=3D BCM2711) { + ret =3D pcie->cfg->perst_set(pcie, 1); if (ret) { - pcie->bridge_sw_init_set(pcie, 0); + pcie->cfg->bridge_sw_init_set(pcie, 0); return ret; } } @@ -1059,7 +1053,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) usleep_range(100, 200); =20 /* Take the bridge out of reset */ - ret =3D pcie->bridge_sw_init_set(pcie, 0); + ret =3D pcie->cfg->bridge_sw_init_set(pcie, 0); if (ret) return ret; =20 @@ -1079,9 +1073,9 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) */ if (is_bmips(pcie)) burst =3D 0x1; /* 256 bytes */ - else if (pcie->soc_base =3D=3D BCM2711) + else if (pcie->cfg->soc_base =3D=3D BCM2711) burst =3D 0x0; /* 128 bytes */ - else if (pcie->soc_base =3D=3D BCM7278) + else if (pcie->cfg->soc_base =3D=3D BCM7278) burst =3D 0x3; /* 512 bytes */ else burst =3D 0x2; /* 512 bytes */ @@ -1206,7 +1200,7 @@ static void brcm_extend_rbus_timeout(struct brcm_pcie= *pcie) u32 timeout_us =3D 4000000; /* 4 seconds, our setting for L1SS */ =20 /* 7712 does not have this (RGR1) timer */ - if (pcie->soc_base =3D=3D BCM7712) + if (pcie->cfg->soc_base =3D=3D BCM7712) return; =20 /* Each unit in timeout register is 1/216,000,000 seconds */ @@ -1284,7 +1278,7 @@ static int brcm_pcie_start_link(struct brcm_pcie *pci= e) int ret, i; =20 /* Unassert the fundamental reset */ - ret =3D pcie->perst_set(pcie, 0); + ret =3D pcie->cfg->perst_set(pcie, 0); if (ret) return ret; =20 @@ -1527,12 +1521,12 @@ static int brcm_phy_cntl(struct brcm_pcie *pcie, co= nst int start) =20 static inline int brcm_phy_start(struct brcm_pcie *pcie) { - return pcie->has_phy ? brcm_phy_cntl(pcie, 1) : 0; + return pcie->cfg->has_phy ? brcm_phy_cntl(pcie, 1) : 0; } =20 static inline int brcm_phy_stop(struct brcm_pcie *pcie) { - return pcie->has_phy ? brcm_phy_cntl(pcie, 0) : 0; + return pcie->cfg->has_phy ? brcm_phy_cntl(pcie, 0) : 0; } =20 static int brcm_pcie_turn_off(struct brcm_pcie *pcie) @@ -1543,7 +1537,7 @@ static int brcm_pcie_turn_off(struct brcm_pcie *pcie) if (brcm_pcie_link_up(pcie)) brcm_pcie_enter_l23(pcie); /* Assert fundamental reset */ - ret =3D pcie->perst_set(pcie, 1); + ret =3D pcie->cfg->perst_set(pcie, 1); if (ret) return ret; =20 @@ -1557,9 +1551,9 @@ static int brcm_pcie_turn_off(struct brcm_pcie *pcie) u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MAS= K); writel(tmp, base + HARD_DEBUG(pcie)); =20 - if (!(pcie->quirks & CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN)) + if (!(pcie->cfg->quirks & CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN)) /* Shutdown PCIe bridge */ - ret =3D pcie->bridge_sw_init_set(pcie, 1); + ret =3D pcie->cfg->bridge_sw_init_set(pcie, 1); =20 return ret; } @@ -1647,7 +1641,7 @@ static int brcm_pcie_resume_noirq(struct device *dev) goto err_reset; =20 /* Take bridge out of reset so we can access the SERDES reg */ - pcie->bridge_sw_init_set(pcie, 0); + pcie->cfg->bridge_sw_init_set(pcie, 0); =20 /* SERDES_IDDQ =3D 0 */ tmp =3D readl(base + HARD_DEBUG(pcie)); @@ -1878,13 +1872,7 @@ static int brcm_pcie_probe(struct platform_device *p= dev) pcie =3D pci_host_bridge_priv(bridge); pcie->dev =3D &pdev->dev; pcie->np =3D np; - pcie->reg_offsets =3D data->offsets; - pcie->soc_base =3D data->soc_base; - pcie->perst_set =3D data->perst_set; - pcie->bridge_sw_init_set =3D data->bridge_sw_init_set; - pcie->has_phy =3D data->has_phy; - pcie->quirks =3D data->quirks; - pcie->num_inbound_wins =3D data->num_inbound_wins; + pcie->cfg =3D data; =20 pcie->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pcie->base)) @@ -1919,7 +1907,7 @@ static int brcm_pcie_probe(struct platform_device *pd= ev) if (ret) return dev_err_probe(&pdev->dev, ret, "could not enable clock\n"); =20 - pcie->bridge_sw_init_set(pcie, 0); + pcie->cfg->bridge_sw_init_set(pcie, 0); =20 if (pcie->swinit_reset) { ret =3D reset_control_assert(pcie->swinit_reset); @@ -1958,7 +1946,8 @@ static int brcm_pcie_probe(struct platform_device *pd= ev) goto fail; =20 pcie->hw_rev =3D readl(pcie->base + PCIE_MISC_REVISION); - if (pcie->soc_base =3D=3D BCM4908 && pcie->hw_rev >=3D BRCM_PCIE_HW_REV_3= _20) { + if (pcie->cfg->soc_base =3D=3D BCM4908 && + pcie->hw_rev >=3D BRCM_PCIE_HW_REV_3_20) { dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n"); ret =3D -ENODEV; goto fail; @@ -1982,7 +1971,8 @@ static int brcm_pcie_probe(struct platform_device *pd= ev) } } =20 - bridge->ops =3D pcie->soc_base =3D=3D BCM7425 ? &brcm7425_pcie_ops : &brc= m_pcie_ops; + bridge->ops =3D pcie->cfg->soc_base =3D=3D BCM7425 ? + &brcm7425_pcie_ops : &brcm_pcie_ops; bridge->sysdata =3D pcie; =20 platform_set_drvdata(pdev, pcie); --=20 2.35.3