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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by BL02EPF0001A101.mail.protection.outlook.com (10.167.241.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Tue, 10 Sep 2024 08:56:19 +0000 Received: from BLR-L-DUGWEKAR.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 10 Sep 2024 03:56:13 -0500 From: Dhananjay Ugwekar To: , , , , , , , , , , , , , , CC: , , , , "Dhananjay Ugwekar" Subject: [PATCH v5] perf/x86/rapl: Fix the energy-pkg event for AMD CPUs Date: Tue, 10 Sep 2024 14:25:05 +0530 Message-ID: <20240910085504.204814-1-Dhananjay.Ugwekar@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A101:EE_|SA1PR12MB6679:EE_ X-MS-Office365-Filtering-Correlation-Id: 83f4ccfd-7d6c-40ce-48a5-08dcd1767022 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|7416014|376014|36860700013|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2024 08:56:19.6627 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83f4ccfd-7d6c-40ce-48a5-08dcd1767022 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A101.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6679 Content-Type: text/plain; charset="utf-8" After commit ("x86/cpu/topology: Add support for the AMD 0x80000026 leaf"), on AMD processors that support extended CPUID leaf 0x80000026, the topology_die_cpumask() and topology_logical_die_id() macros, no longer return the package cpumask and package id, instead they return the CCD (Core Complex Die) mask and id respectively. This leads to the energy-pkg event scope to be modified to CCD instead of package. So, change the PMU scope for AMD and Hygon back to package. On a 12 CCD 1 Package AMD Zen4 Genoa machine: Before: $ cat /sys/devices/power/cpumask 0,8,16,24,32,40,48,56,64,72,80,88. The expected cpumask here is supposed to be just "0", as it is a package scope event, only one CPU will be collecting the event for all the CPUs in the package. After: $ cat /sys/devices/power/cpumask 0 Signed-off-by: Dhananjay Ugwekar --- v4 Link: https://lore.kernel.org/all/20240905153821.3822-1-Dhananjay.Ugweka= r@amd.com/=20 Changes from v4: * Rebase on top of a fix [1] in the PMU scope patchset [2] Base: tip/perf/core + PMU scope patchset [2]=20 [1]: https://lore.kernel.org/all/8c09633c-5bf2-48a2-91a6-a0af9b9f2e8c@linux= .intel.com/ [2]: https://lore.kernel.org/all/20240802151643.1691631-1-kan.liang@linux.i= ntel.com/ --- arch/x86/events/rapl.c | 35 ++++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index 0f8f4eb01278..ce04dc5844c4 100644 --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -139,9 +139,32 @@ static unsigned int rapl_cntr_mask; static u64 rapl_timer_ms; static struct perf_msr *rapl_msrs; =20 +/* + * RAPL Package energy counter scope: + * 1. AMD/HYGON platforms have a per-PKG package energy counter + * 2. For Intel platforms + * 2.1. CLX-AP is multi-die and its RAPL MSRs are die-scope + * 2.2. Other Intel platforms are single die systems so the scope can be + * considered as either pkg-scope or die-scope, and we are considering + * them as die-scope. + */ +#define rapl_pmu_is_pkg_scope() \ + (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD || \ + boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_HYGON) + +/* + * Helper function to get the correct topology id according to the + * RAPL PMU scope. + */ +static inline unsigned int get_rapl_pmu_idx(int cpu) +{ + return rapl_pmu_is_pkg_scope() ? topology_logical_package_id(cpu) : + topology_logical_die_id(cpu); +} + static inline struct rapl_pmu *cpu_to_rapl_pmu(unsigned int cpu) { - unsigned int rapl_pmu_idx =3D topology_logical_die_id(cpu); + unsigned int rapl_pmu_idx =3D get_rapl_pmu_idx(cpu); =20 /* * The unsigned check also catches the '-1' return value for non @@ -617,7 +640,7 @@ static void __init init_rapl_pmu(void) pmu->timer_interval =3D ms_to_ktime(rapl_timer_ms); rapl_hrtimer_init(pmu); =20 - rapl_pmus->pmus[topology_logical_die_id(cpu)] =3D pmu; + rapl_pmus->pmus[get_rapl_pmu_idx(cpu)] =3D pmu; } =20 cpus_read_unlock(); @@ -626,6 +649,12 @@ static void __init init_rapl_pmu(void) static int __init init_rapl_pmus(void) { int nr_rapl_pmu =3D topology_max_packages() * topology_max_dies_per_packa= ge(); + int rapl_pmu_scope =3D PERF_PMU_SCOPE_DIE; + + if (rapl_pmu_is_pkg_scope()) { + nr_rapl_pmu =3D topology_max_packages(); + rapl_pmu_scope =3D PERF_PMU_SCOPE_PKG; + } =20 rapl_pmus =3D kzalloc(struct_size(rapl_pmus, pmus, nr_rapl_pmu), GFP_KERN= EL); if (!rapl_pmus) @@ -641,8 +670,8 @@ static int __init init_rapl_pmus(void) rapl_pmus->pmu.start =3D rapl_pmu_event_start; rapl_pmus->pmu.stop =3D rapl_pmu_event_stop; rapl_pmus->pmu.read =3D rapl_pmu_event_read; + rapl_pmus->pmu.scope =3D rapl_pmu_scope; rapl_pmus->pmu.module =3D THIS_MODULE; - rapl_pmus->pmu.scope =3D PERF_PMU_SCOPE_DIE; rapl_pmus->pmu.capabilities =3D PERF_PMU_CAP_NO_EXCLUDE; =20 init_rapl_pmu(); --=20 2.34.1