From nobody Sat Nov 30 10:39:28 2024 Received: from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D346514EC64; Tue, 10 Sep 2024 08:06:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.35 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725955574; cv=none; b=u/BoNrDrkVFyKpK4cQgC9xW6yLLKtdtmyGPqj/wPpmVWngoO2K58dDMQPgyPMB22vtVd/f0G4tuDz1kEiD4a0tCBAL2DPN68NEWGl8ekvDXNeeRf6V8ZcOA6ytPM8sppEvWnWTdLE6RioGNvHYup4k5PHLTNk3XHAVpmlpvUE2g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725955574; c=relaxed/simple; bh=VtfuuOtBjWUM+HYaURABILrI9PKM8kWk0vh+2zOxNQQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=B3ygc9Wysv1ns4ZMrAC3Sa1UUfsLBDGF7a2zsiMughVw7uIoguCyS73b7p+G83ykgNiyCHL3fnarAzeeIoj1x7WXVCRupiQRzO8oDjwb0lUxjJC7/RmXDd8N3Y0RM9lYMhzx19ZoPTeycfkEM3Uprs1S8ABEqas8avgZyf4Ncc4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.35 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.163]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4X2x8h5zX3z1SB39; Tue, 10 Sep 2024 16:05:40 +0800 (CST) Received: from kwepemm000007.china.huawei.com (unknown [7.193.23.189]) by mail.maildlp.com (Postfix) with ESMTPS id 534FB180044; Tue, 10 Sep 2024 16:06:09 +0800 (CST) Received: from localhost.localdomain (10.90.30.45) by kwepemm000007.china.huawei.com (7.193.23.189) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 10 Sep 2024 16:06:08 +0800 From: Jijie Shao To: , , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH V9 net-next 01/11] net: hibmcge: Add pci table supported in this module Date: Tue, 10 Sep 2024 15:59:32 +0800 Message-ID: <20240910075942.1270054-2-shaojijie@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20240910075942.1270054-1-shaojijie@huawei.com> References: <20240910075942.1270054-1-shaojijie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemm000007.china.huawei.com (7.193.23.189) Add pci table supported in this module, and implement pci_driver function to initialize this driver. hibmcge is a passthrough network device. Its software runs on the host side, and the MAC hardware runs on the BMC side to reduce the host CPU area. The software interacts with the MAC hardware through the PCIe. =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=90 =E2=94=82 HOST CPU network device =E2=94=82 =E2=94=82 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=90 =E2=94=82 =E2=94=82 =E2=94=82hibmcge driver=E2=94=82 =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =AC=E2=94=80=E2=94=AC=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=98 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82HOST =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=B4=E2=94=80=E2= =94=B4=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82 =E2=94=82 =E2=94=82 PCIE RC =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=B4= =E2=94=80=E2=94=80=E2=94=80=E2=94=AC=E2=94=80=E2=94=AC=E2=94=80=E2=94=80=E2= =94=80=E2=94=B4=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=82 PCIE =E2=94=82 =E2=94=82 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=AC= =E2=94=80=E2=94=80=E2=94=80=E2=94=B4=E2=94=80=E2=94=B4=E2=94=80=E2=94=80=E2= =94=80=E2=94=AC=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=90 =E2=94=82 =E2=94=82 PCIE EP =E2=94=82 =E2=94=82 =E2=94=82BMC =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=AC=E2=94=80=E2= =94=AC=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=B4=E2=94=80=E2=94=B4=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2= =94=82 =E2=94=82 =E2=94=82 GE =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=90 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=90 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 MAC =E2=94=82 =E2=94=82 MAC =E2=94=82 = =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80=E2=94=B4=E2=94=80=E2=94=BC=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=BC=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=BC=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=BC=E2=94=80=E2=94=80=E2=94= =B4=E2=94=80=E2=94=98 =E2=94=82 PHY =E2=94=82 =E2=94=82 PHY =E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 = =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 Signed-off-by: Jijie Shao --- ChangeLog: v7 -> v8: - Set netdev->pcpu_stat_type to NETDEV_PCPU_STAT_TSTATS, suggested by Jak= ub v7: https://lore.kernel.org/all/20240905143120.1583460-1-shaojijie@huawei= .com/ v6 -> v7: - Add devm_netdev_alloc_pcpu_stats() to init netdev->tstats, suggested by Paolo. v6: https://lore.kernel.org/all/20240830121604.2250904-2-shaojijie@huawei= .com/ RFC v1 -> RFC v2: - Add the null pointer check on the return value of pcim_iomap_table(), suggested by Jonathan. RFC v1: https://lore.kernel.org/all/20240731094245.1967834-1-shaojijie@hu= awei.com/ --- .../ethernet/hisilicon/hibmcge/hbg_common.h | 16 ++++ .../net/ethernet/hisilicon/hibmcge/hbg_main.c | 89 +++++++++++++++++++ 2 files changed, 105 insertions(+) create mode 100644 drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h create mode 100644 drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h b/drivers/= net/ethernet/hisilicon/hibmcge/hbg_common.h new file mode 100644 index 000000000000..614650e9a71f --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (c) 2024 Hisilicon Limited. */ + +#ifndef __HBG_COMMON_H +#define __HBG_COMMON_H + +#include +#include + +struct hbg_priv { + struct net_device *netdev; + struct pci_dev *pdev; + u8 __iomem *io_base; +}; + +#endif diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c b/drivers/ne= t/ethernet/hisilicon/hibmcge/hbg_main.c new file mode 100644 index 000000000000..30e29362346b --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2024 Hisilicon Limited. + +#include +#include +#include +#include "hbg_common.h" + +static int hbg_pci_init(struct pci_dev *pdev) +{ + struct net_device *netdev =3D pci_get_drvdata(pdev); + struct hbg_priv *priv =3D netdev_priv(netdev); + struct device *dev =3D &pdev->dev; + int ret; + + ret =3D pcim_enable_device(pdev); + if (ret) + return dev_err_probe(dev, ret, "failed to enable PCI device\n"); + + ret =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); + if (ret) + return dev_err_probe(dev, ret, "failed to set PCI DMA mask\n"); + + ret =3D pcim_iomap_regions(pdev, BIT(0), dev_driver_string(dev)); + if (ret) + return dev_err_probe(dev, ret, "failed to map PCI bar space\n"); + + priv->io_base =3D pcim_iomap_table(pdev)[0]; + if (!priv->io_base) + return dev_err_probe(dev, -ENOMEM, "failed to get io base\n"); + + pci_set_master(pdev); + return 0; +} + +static int hbg_probe(struct pci_dev *pdev, const struct pci_device_id *ent) +{ + struct device *dev =3D &pdev->dev; + struct net_device *netdev; + struct hbg_priv *priv; + int ret; + + netdev =3D devm_alloc_etherdev_mqs(dev, sizeof(struct hbg_priv), 1, 1); + if (!netdev) + return -ENOMEM; + + pci_set_drvdata(pdev, netdev); + + SET_NETDEV_DEV(netdev, dev); + + priv =3D netdev_priv(netdev); + priv->netdev =3D netdev; + priv->pdev =3D pdev; + + netdev->tstats =3D devm_netdev_alloc_pcpu_stats(&pdev->dev, + struct pcpu_sw_netstats); + if (!netdev->tstats) + return -ENOMEM; + netdev->pcpu_stat_type =3D NETDEV_PCPU_STAT_TSTATS; + + ret =3D hbg_pci_init(pdev); + if (ret) + return ret; + + ret =3D devm_register_netdev(dev, netdev); + if (ret) + return dev_err_probe(dev, ret, "failed to register netdev\n"); + + netif_carrier_off(netdev); + return 0; +} + +static const struct pci_device_id hbg_pci_tbl[] =3D { + {PCI_VDEVICE(HUAWEI, 0x3730), 0}, + { } +}; +MODULE_DEVICE_TABLE(pci, hbg_pci_tbl); + +static struct pci_driver hbg_driver =3D { + .name =3D "hibmcge", + .id_table =3D hbg_pci_tbl, + .probe =3D hbg_probe, +}; +module_pci_driver(hbg_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Huawei Tech. Co., Ltd."); +MODULE_DESCRIPTION("hibmcge driver"); +MODULE_VERSION("1.0"); --=20 2.33.0 From nobody Sat Nov 30 10:39:28 2024 Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CB90187FE8; Tue, 10 Sep 2024 08:06:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.188 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725955579; cv=none; b=Czq5FLuscJ0366rMLnkhFLLkFkmmAc37YxlJrIpqDQOEil5NSBa/kVmNSQsV0jZwrxpUmAWQSgO0eLgLaPbnQbO8pHnvhLxrJCmLsn2I2pJ3MJQw5D6vvuUFIq7JQ2oHlf7Fee62I8dYNjHF2KAZ6KKNjFt6eAQ3wc0VXroqbz4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725955579; c=relaxed/simple; bh=dwdXtEc2C5OasYj5rKSR/DKCShsCmxIMZCY1+/lc4xE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nbyWPTFmLZdfce36W8o1kE10yLfA574sTFZOGzlJdPLoAZWFt9KPXs/xr1koDQejflBfmuThqccQjvyHWGu6s7XXzZXh5wwGCygdar5qOe53vva/+RAJVOFSsOqmrTQuPGkiqj/6ip+jNNcWAqHe8dFdhE4xfyaGNvziLWotmls= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.188 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.105]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4X2x6q4FSlzfc0c; Tue, 10 Sep 2024 16:04:03 +0800 (CST) Received: from kwepemm000007.china.huawei.com (unknown [7.193.23.189]) by mail.maildlp.com (Postfix) with ESMTPS id 241561402E2; Tue, 10 Sep 2024 16:06:10 +0800 (CST) Received: from localhost.localdomain (10.90.30.45) by kwepemm000007.china.huawei.com (7.193.23.189) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 10 Sep 2024 16:06:09 +0800 From: Jijie Shao To: , , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH V9 net-next 02/11] net: hibmcge: Add read/write registers supported through the bar space Date: Tue, 10 Sep 2024 15:59:33 +0800 Message-ID: <20240910075942.1270054-3-shaojijie@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20240910075942.1270054-1-shaojijie@huawei.com> References: <20240910075942.1270054-1-shaojijie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemm000007.china.huawei.com (7.193.23.189) Content-Type: text/plain; charset="utf-8" Add support for to read and write registers through the pic bar space. Some driver parameters, such as mac_id, are determined by the board form. Therefore, these parameters are initialized from the register as device specifications. the device specifications register are initialized and writed by bmc. driver will read these registers when loading. Signed-off-by: Jijie Shao --- ChangeLog: v3 -> v4: - Delete INITED_STATE in priv, suggested by Andrew. v3: https://lore.kernel.org/all/20240822093334.1687011-1-shaojijie@huawei= .com/ --- .../ethernet/hisilicon/hibmcge/hbg_common.h | 26 +++++++ .../net/ethernet/hisilicon/hibmcge/hbg_hw.c | 76 +++++++++++++++++++ .../net/ethernet/hisilicon/hibmcge/hbg_hw.h | 34 +++++++++ .../net/ethernet/hisilicon/hibmcge/hbg_main.c | 16 ++++ .../net/ethernet/hisilicon/hibmcge/hbg_reg.h | 20 +++++ 5 files changed, 172 insertions(+) create mode 100644 drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c create mode 100644 drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h create mode 100644 drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h b/drivers/= net/ethernet/hisilicon/hibmcge/hbg_common.h index 614650e9a71f..6fbc24803942 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h @@ -7,10 +7,36 @@ #include #include =20 +enum hbg_nic_state { + HBG_NIC_STATE_EVENT_HANDLING =3D 0, +}; + +enum hbg_hw_event_type { + HBG_HW_EVENT_NONE =3D 0, + HBG_HW_EVENT_INIT, /* driver is loading */ +}; + +struct hbg_dev_specs { + u32 mac_id; + struct sockaddr mac_addr; + u32 phy_addr; + u32 mdio_frequency; + u32 rx_fifo_num; + u32 tx_fifo_num; + u32 vlan_layers; + u32 max_mtu; + u32 min_mtu; + + u32 max_frame_len; + u32 rx_buf_size; +}; + struct hbg_priv { struct net_device *netdev; struct pci_dev *pdev; u8 __iomem *io_base; + struct hbg_dev_specs dev_specs; + unsigned long state; }; =20 #endif diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c b/drivers/net/= ethernet/hisilicon/hibmcge/hbg_hw.c new file mode 100644 index 000000000000..23efbf0bf34f --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2024 Hisilicon Limited. + +#include +#include +#include +#include +#include "hbg_common.h" +#include "hbg_hw.h" +#include "hbg_reg.h" + +#define HBG_HW_EVENT_WAIT_TIMEOUT_US (2 * 1000 * 1000) +#define HBG_HW_EVENT_WAIT_INTERVAL_US (10 * 1000) + +static bool hbg_hw_spec_is_valid(struct hbg_priv *priv) +{ + return hbg_reg_read(priv, HBG_REG_SPEC_VALID_ADDR) && + !hbg_reg_read(priv, HBG_REG_EVENT_REQ_ADDR); +} + +int hbg_hw_event_notify(struct hbg_priv *priv, + enum hbg_hw_event_type event_type) +{ + bool is_valid; + int ret; + + if (test_and_set_bit(HBG_NIC_STATE_EVENT_HANDLING, &priv->state)) + return -EBUSY; + + /* notify */ + hbg_reg_write(priv, HBG_REG_EVENT_REQ_ADDR, event_type); + + ret =3D read_poll_timeout(hbg_hw_spec_is_valid, is_valid, is_valid, + HBG_HW_EVENT_WAIT_INTERVAL_US, + HBG_HW_EVENT_WAIT_TIMEOUT_US, + HBG_HW_EVENT_WAIT_INTERVAL_US, priv); + + clear_bit(HBG_NIC_STATE_EVENT_HANDLING, &priv->state); + + if (ret) + dev_err(&priv->pdev->dev, "event %d wait timeout\n", event_type); + + return ret; +} + +static int hbg_hw_dev_specs_init(struct hbg_priv *priv) +{ + struct hbg_dev_specs *dev_specs =3D &priv->dev_specs; + u64 mac_addr; + + if (!hbg_hw_spec_is_valid(priv)) { + dev_err(&priv->pdev->dev, "dev_specs not init\n"); + return -EINVAL; + } + + dev_specs->mac_id =3D hbg_reg_read(priv, HBG_REG_MAC_ID_ADDR); + dev_specs->phy_addr =3D hbg_reg_read(priv, HBG_REG_PHY_ID_ADDR); + dev_specs->mdio_frequency =3D hbg_reg_read(priv, HBG_REG_MDIO_FREQ_ADDR); + dev_specs->max_mtu =3D hbg_reg_read(priv, HBG_REG_MAX_MTU_ADDR); + dev_specs->min_mtu =3D hbg_reg_read(priv, HBG_REG_MIN_MTU_ADDR); + dev_specs->vlan_layers =3D hbg_reg_read(priv, HBG_REG_VLAN_LAYERS_ADDR); + dev_specs->rx_fifo_num =3D hbg_reg_read(priv, HBG_REG_RX_FIFO_NUM_ADDR); + dev_specs->tx_fifo_num =3D hbg_reg_read(priv, HBG_REG_TX_FIFO_NUM_ADDR); + mac_addr =3D hbg_reg_read64(priv, HBG_REG_MAC_ADDR_ADDR); + u64_to_ether_addr(mac_addr, (u8 *)dev_specs->mac_addr.sa_data); + + if (!is_valid_ether_addr((u8 *)dev_specs->mac_addr.sa_data)) + return -EADDRNOTAVAIL; + + return 0; +} + +int hbg_hw_init(struct hbg_priv *priv) +{ + return hbg_hw_dev_specs_init(priv); +} diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h b/drivers/net/= ethernet/hisilicon/hibmcge/hbg_hw.h new file mode 100644 index 000000000000..4a62d1a610ea --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (c) 2024 Hisilicon Limited. */ + +#ifndef __HBG_HW_H +#define __HBG_HW_H + +#include +#include + +static inline u32 hbg_reg_read(struct hbg_priv *priv, u32 addr) +{ + return readl(priv->io_base + addr); +} + +static inline void hbg_reg_write(struct hbg_priv *priv, u32 addr, u32 valu= e) +{ + writel(value, priv->io_base + addr); +} + +static inline u64 hbg_reg_read64(struct hbg_priv *priv, u32 addr) +{ + return lo_hi_readq(priv->io_base + addr); +} + +static inline void hbg_reg_write64(struct hbg_priv *priv, u32 addr, u64 va= lue) +{ + lo_hi_writeq(value, priv->io_base + addr); +} + +int hbg_hw_event_notify(struct hbg_priv *priv, + enum hbg_hw_event_type event_type); +int hbg_hw_init(struct hbg_priv *priv); + +#endif diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c b/drivers/ne= t/ethernet/hisilicon/hibmcge/hbg_main.c index 30e29362346b..b0df3559929f 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c @@ -5,6 +5,18 @@ #include #include #include "hbg_common.h" +#include "hbg_hw.h" + +static int hbg_init(struct hbg_priv *priv) +{ + int ret; + + ret =3D hbg_hw_event_notify(priv, HBG_HW_EVENT_INIT); + if (ret) + return ret; + + return hbg_hw_init(priv); +} =20 static int hbg_pci_init(struct pci_dev *pdev) { @@ -62,6 +74,10 @@ static int hbg_probe(struct pci_dev *pdev, const struct = pci_device_id *ent) if (ret) return ret; =20 + ret =3D hbg_init(priv); + if (ret) + return ret; + ret =3D devm_register_netdev(dev, netdev); if (ret) return dev_err_probe(dev, ret, "failed to register netdev\n"); diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h b/drivers/net= /ethernet/hisilicon/hibmcge/hbg_reg.h new file mode 100644 index 000000000000..77153f1132fd --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (c) 2024 Hisilicon Limited. */ + +#ifndef __HBG_REG_H +#define __HBG_REG_H + +/* DEV SPEC */ +#define HBG_REG_SPEC_VALID_ADDR 0x0000 +#define HBG_REG_EVENT_REQ_ADDR 0x0004 +#define HBG_REG_MAC_ID_ADDR 0x0008 +#define HBG_REG_PHY_ID_ADDR 0x000C +#define HBG_REG_MAC_ADDR_ADDR 0x0010 +#define HBG_REG_MDIO_FREQ_ADDR 0x0024 +#define HBG_REG_MAX_MTU_ADDR 0x0028 +#define HBG_REG_MIN_MTU_ADDR 0x002C +#define HBG_REG_TX_FIFO_NUM_ADDR 0x0030 +#define HBG_REG_RX_FIFO_NUM_ADDR 0x0034 +#define HBG_REG_VLAN_LAYERS_ADDR 0x0038 + +#endif --=20 2.33.0 From nobody Sat Nov 30 10:39:28 2024 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8809188591; 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dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.252]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4X2x8V2PTJzyRl8; Tue, 10 Sep 2024 16:05:30 +0800 (CST) Received: from kwepemm000007.china.huawei.com (unknown [7.193.23.189]) by mail.maildlp.com (Postfix) with ESMTPS id D8677180AE8; Tue, 10 Sep 2024 16:06:10 +0800 (CST) Received: from localhost.localdomain (10.90.30.45) by kwepemm000007.china.huawei.com (7.193.23.189) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 10 Sep 2024 16:06:09 +0800 From: Jijie Shao To: , , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH V9 net-next 03/11] net: hibmcge: Add mdio and hardware configuration supported in this module Date: Tue, 10 Sep 2024 15:59:34 +0800 Message-ID: <20240910075942.1270054-4-shaojijie@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20240910075942.1270054-1-shaojijie@huawei.com> References: <20240910075942.1270054-1-shaojijie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemm000007.china.huawei.com (7.193.23.189) Content-Type: text/plain; charset="utf-8" this driver using phy through genphy device. Implements the C22 read and write PHY registers interfaces. Some hardware interfaces related to the PHY are also implemented in this patch. Signed-off-by: Jijie Shao --- ChangeLog: v6 -> v7: - Move the define inside the function body to the top of the .c file, suggested by Paolo and Andrew. - Respect the reverse x-mas tree order, suggested by Paolo. v6: https://lore.kernel.org/all/20240830121604.2250904-4-shaojijie@huawei= .com/ v3 -> v4: - Delete unnecessary defensive code in hbg_phy_start() and hbg_phy_stop(), suggested by Andrew. v3: https://lore.kernel.org/all/20240822093334.1687011-1-shaojijie@huawei= .com/ RFC v2 -> v1: - Use FIELD_PREP/FIELD_GET instead of union, suggested by Andrew. - Delete unnecessary defensive code, suggested by Andrew. RFC v2: https://lore.kernel.org/all/20240813135640.1694993-1-shaojijie@hu= awei.com/ RFC v1 -> RFC v2: - Replace linkmode_copy() with phy_remove_link_mode() to simplify the PHY configuration process, suggested by Andrew. - Delete hbg_get_link_status() from the scheduled task, suggested by Andr= ew. - Add the check on the return value of phy_connect_direct(), suggested by Jonathan. - Adjusted the layout to place the fields and register definitions in one place, suggested by Jonathan. - Use macro instead of inline to fix the warning about compile-time const= ant in FIELD_PREP(), reported by Simon Horman. RFC v1: https://lore.kernel.org/all/20240731094245.1967834-1-shaojijie@hu= awei.com/ --- .../ethernet/hisilicon/hibmcge/hbg_common.h | 19 ++ .../net/ethernet/hisilicon/hibmcge/hbg_hw.c | 83 +++++- .../net/ethernet/hisilicon/hibmcge/hbg_hw.h | 15 ++ .../net/ethernet/hisilicon/hibmcge/hbg_main.c | 7 +- .../net/ethernet/hisilicon/hibmcge/hbg_mdio.c | 244 ++++++++++++++++++ .../net/ethernet/hisilicon/hibmcge/hbg_mdio.h | 12 + .../net/ethernet/hisilicon/hibmcge/hbg_reg.h | 55 ++++ 7 files changed, 433 insertions(+), 2 deletions(-) create mode 100644 drivers/net/ethernet/hisilicon/hibmcge/hbg_mdio.c create mode 100644 drivers/net/ethernet/hisilicon/hibmcge/hbg_mdio.h diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h b/drivers/= net/ethernet/hisilicon/hibmcge/hbg_common.h index 6fbc24803942..e047539a407a 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h @@ -6,6 +6,13 @@ =20 #include #include +#include "hbg_reg.h" + +#define HBG_STATUS_DISABLE 0x0 +#define HBG_STATUS_ENABLE 0x1 +#define HBG_DEFAULT_MTU_SIZE 1500 +#define HBG_RX_SKIP1 0x00 +#define HBG_RX_SKIP2 0x01 =20 enum hbg_nic_state { HBG_NIC_STATE_EVENT_HANDLING =3D 0, @@ -31,12 +38,24 @@ struct hbg_dev_specs { u32 rx_buf_size; }; =20 +struct hbg_mac { + struct mii_bus *mdio_bus; + struct phy_device *phydev; + u8 phy_addr; + + u32 speed; + u32 duplex; + u32 autoneg; + u32 link_status; +}; + struct hbg_priv { struct net_device *netdev; struct pci_dev *pdev; u8 __iomem *io_base; struct hbg_dev_specs dev_specs; unsigned long state; + struct hbg_mac mac; }; =20 #endif diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c b/drivers/net/= ethernet/hisilicon/hibmcge/hbg_hw.c index 23efbf0bf34f..b1281b206f2f 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c @@ -11,6 +11,10 @@ =20 #define HBG_HW_EVENT_WAIT_TIMEOUT_US (2 * 1000 * 1000) #define HBG_HW_EVENT_WAIT_INTERVAL_US (10 * 1000) +/* little endian or big endian. + * ctrl means packet description, data means skb packet data + */ +#define HBG_ENDIAN_CTRL_LE_DATA_BE 0x0 =20 static bool hbg_hw_spec_is_valid(struct hbg_priv *priv) { @@ -70,7 +74,84 @@ static int hbg_hw_dev_specs_init(struct hbg_priv *priv) return 0; } =20 +void hbg_hw_adjust_link(struct hbg_priv *priv, u32 speed, u32 duplex) +{ + hbg_reg_write_field(priv, HBG_REG_PORT_MODE_ADDR, + HBG_REG_PORT_MODE_M, speed); + hbg_reg_write_field(priv, HBG_REG_DUPLEX_TYPE_ADDR, + HBG_REG_DUPLEX_B, duplex); +} + +static void hbg_hw_init_transmit_control(struct hbg_priv *priv) +{ + u32 control =3D 0; + + control |=3D FIELD_PREP(HBG_REG_TRANSMIT_CONTROL_AN_EN_B, HBG_STATUS_ENAB= LE); + control |=3D FIELD_PREP(HBG_REG_TRANSMIT_CONTROL_CRC_ADD_B, HBG_STATUS_EN= ABLE); + control |=3D FIELD_PREP(HBG_REG_TRANSMIT_CONTROL_PAD_EN_B, HBG_STATUS_ENA= BLE); + + hbg_reg_write(priv, HBG_REG_TRANSMIT_CONTROL_ADDR, control); +} + +static void hbg_hw_init_rx_ctrl(struct hbg_priv *priv) +{ + u32 ctrl =3D 0; + + ctrl |=3D FIELD_PREP(HBG_REG_RX_CTRL_RX_GET_ADDR_MODE_B, HBG_STATUS_ENABL= E); + ctrl |=3D FIELD_PREP(HBG_REG_RX_CTRL_TIME_INF_EN_B, HBG_STATUS_DISABLE); + ctrl |=3D FIELD_PREP(HBG_REG_RX_CTRL_RXBUF_1ST_SKIP_SIZE_M, HBG_RX_SKIP1); + ctrl |=3D FIELD_PREP(HBG_REG_RX_CTRL_RXBUF_1ST_SKIP_SIZE2_M, HBG_RX_SKIP2= ); + ctrl |=3D FIELD_PREP(HBG_REG_RX_CTRL_RX_ALIGN_NUM_M, NET_IP_ALIGN); + ctrl |=3D FIELD_PREP(HBG_REG_RX_CTRL_PORT_NUM, priv->dev_specs.mac_id); + + hbg_reg_write(priv, HBG_REG_RX_CTRL_ADDR, ctrl); +} + +static void hbg_hw_init_rx_pkt_mode(struct hbg_priv *priv) +{ + u32 mode =3D 0; + + /* parse from L2 layer */ + mode |=3D FIELD_PREP(HBG_REG_RX_PKT_MODE_PARSE_MODE_M, 0x1); + + hbg_reg_write(priv, HBG_REG_RX_PKT_MODE_ADDR, mode); +} + +static void hbg_hw_init_recv_ctrl(struct hbg_priv *priv) +{ + u32 ctrl =3D 0; + + ctrl |=3D FIELD_PREP(HBG_REG_RECV_CONTROL_STRIP_PAD_EN_B, HBG_STATUS_ENAB= LE); + + hbg_reg_write(priv, HBG_REG_RECV_CONTROL_ADDR, ctrl); +} + +static void hbg_hw_init_rx_control(struct hbg_priv *priv) +{ + hbg_hw_init_rx_ctrl(priv); + hbg_hw_init_rx_pkt_mode(priv); + hbg_hw_init_recv_ctrl(priv); + hbg_reg_write_field(priv, HBG_REG_RX_BUF_SIZE_ADDR, + HBG_REG_RX_BUF_SIZE_M, priv->dev_specs.rx_buf_size); + hbg_reg_write_field(priv, HBG_REG_CF_CRC_STRIP_ADDR, + HBG_REG_CF_CRC_STRIP_B, HBG_STATUS_DISABLE); +} + int hbg_hw_init(struct hbg_priv *priv) { - return hbg_hw_dev_specs_init(priv); + int ret; + + ret =3D hbg_hw_dev_specs_init(priv); + if (ret) + return ret; + + hbg_reg_write_field(priv, HBG_REG_BUS_CTRL_ADDR, + HBG_REG_BUS_CTRL_ENDIAN_M, + HBG_ENDIAN_CTRL_LE_DATA_BE); + hbg_reg_write_field(priv, HBG_REG_MODE_CHANGE_EN_ADDR, + HBG_REG_MODE_CHANGE_EN_B, HBG_STATUS_ENABLE); + + hbg_hw_init_rx_control(priv); + hbg_hw_init_transmit_control(priv); + return 0; } diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h b/drivers/net/= ethernet/hisilicon/hibmcge/hbg_hw.h index 4a62d1a610ea..47df597b885f 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h @@ -27,8 +27,23 @@ static inline void hbg_reg_write64(struct hbg_priv *priv= , u32 addr, u64 value) lo_hi_writeq(value, priv->io_base + addr); } =20 +#define hbg_reg_read_field(priv, addr, mask) \ + FIELD_GET(mask, hbg_reg_read(priv, addr)) + +#define hbg_field_modify(reg_value, mask, value) ({ \ + (reg_value) &=3D ~(mask); \ + (reg_value) |=3D FIELD_PREP(mask, value); }) + +#define hbg_reg_write_field(priv, addr, mask, val) ({ \ + typeof(priv) _priv =3D (priv); \ + typeof(addr) _addr =3D (addr); \ + u32 _value =3D hbg_reg_read(_priv, _addr); \ + hbg_field_modify(_value, mask, val); \ + hbg_reg_write(_priv, _addr, _value); }) + int hbg_hw_event_notify(struct hbg_priv *priv, enum hbg_hw_event_type event_type); int hbg_hw_init(struct hbg_priv *priv); +void hbg_hw_adjust_link(struct hbg_priv *priv, u32 speed, u32 duplex); =20 #endif diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c b/drivers/ne= t/ethernet/hisilicon/hibmcge/hbg_main.c index b0df3559929f..22b6557247c4 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c @@ -6,6 +6,7 @@ #include #include "hbg_common.h" #include "hbg_hw.h" +#include "hbg_mdio.h" =20 static int hbg_init(struct hbg_priv *priv) { @@ -15,7 +16,11 @@ static int hbg_init(struct hbg_priv *priv) if (ret) return ret; =20 - return hbg_hw_init(priv); + ret =3D hbg_hw_init(priv); + if (ret) + return ret; + + return hbg_mdio_init(priv); } =20 static int hbg_pci_init(struct pci_dev *pdev) diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_mdio.c b/drivers/ne= t/ethernet/hisilicon/hibmcge/hbg_mdio.c new file mode 100644 index 000000000000..e8938f82234c --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_mdio.c @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2024 Hisilicon Limited. + +#include +#include "hbg_common.h" +#include "hbg_hw.h" +#include "hbg_mdio.h" +#include "hbg_reg.h" + +#define HBG_MAC_GET_PRIV(mac) ((struct hbg_priv *)(mac)->mdio_bus->priv) +#define HBG_MII_BUS_GET_MAC(bus) (&((struct hbg_priv *)(bus)->priv)->mac) + +#define HBG_MDIO_C22_MODE 0x1 +#define HBG_MDIO_C22_REG_WRITE 0x1 +#define HBG_MDIO_C22_REG_READ 0x2 + +#define HBG_MDIO_OP_TIMEOUT_US (1 * 1000 * 1000) +#define HBG_MDIO_OP_INTERVAL_US (5 * 1000) + +static void hbg_mdio_set_command(struct hbg_mac *mac, u32 cmd) +{ + hbg_reg_write(HBG_MAC_GET_PRIV(mac), HBG_REG_MDIO_COMMAND_ADDR, cmd); +} + +static void hbg_mdio_get_command(struct hbg_mac *mac, u32 *cmd) +{ + *cmd =3D hbg_reg_read(HBG_MAC_GET_PRIV(mac), HBG_REG_MDIO_COMMAND_ADDR); +} + +static void hbg_mdio_set_wdata_reg(struct hbg_mac *mac, u16 wdata_value) +{ + hbg_reg_write_field(HBG_MAC_GET_PRIV(mac), HBG_REG_MDIO_WDATA_ADDR, + HBG_REG_MDIO_WDATA_M, wdata_value); +} + +static u32 hbg_mdio_get_rdata_reg(struct hbg_mac *mac) +{ + return hbg_reg_read_field(HBG_MAC_GET_PRIV(mac), + HBG_REG_MDIO_RDATA_ADDR, + HBG_REG_MDIO_WDATA_M); +} + +static int hbg_mdio_check_op_status(struct hbg_mac *mac) +{ + struct hbg_priv *priv =3D HBG_MAC_GET_PRIV(mac); + + return hbg_reg_read(priv, HBG_REG_MDIO_STA_ADDR) ? -EBUSY : 0; +} + +static int hbg_mdio_wait_ready(struct hbg_mac *mac) +{ + struct hbg_priv *priv =3D HBG_MAC_GET_PRIV(mac); + u32 cmd; + + return readl_poll_timeout(priv->io_base + HBG_REG_MDIO_COMMAND_ADDR, cmd, + !FIELD_GET(HBG_REG_MDIO_COMMAND_START_B, cmd), + HBG_MDIO_OP_INTERVAL_US, + HBG_MDIO_OP_TIMEOUT_US); +} + +static int hbg_mdio_check_send_result(struct hbg_mac *mac) +{ + int ret; + + ret =3D hbg_mdio_wait_ready(mac); + if (ret) + return ret; + + return hbg_mdio_check_op_status(mac); +} + +static int hbg_mdio_cmd_send(struct hbg_mac *mac, u32 prt_addr, u32 dev_ad= dr, + u32 type, u32 op_code) +{ + u32 cmd =3D 0; + + hbg_mdio_get_command(mac, &cmd); + hbg_field_modify(cmd, HBG_REG_MDIO_COMMAND_ST_M, type); + hbg_field_modify(cmd, HBG_REG_MDIO_COMMAND_OP_M, op_code); + hbg_field_modify(cmd, HBG_REG_MDIO_COMMAND_PRTAD_M, prt_addr); + hbg_field_modify(cmd, HBG_REG_MDIO_COMMAND_DEVAD_M, dev_addr); + + /* if auto scan enabled, this value need fix to 0 */ + hbg_field_modify(cmd, HBG_REG_MDIO_COMMAND_START_B, 0x1); + + hbg_mdio_set_command(mac, cmd); + + /* wait operation complete and check the result */ + return hbg_mdio_check_send_result(mac); +} + +static int hbg_mdio_read22(struct mii_bus *bus, int phy_addr, int regnum) +{ + struct hbg_mac *mac =3D HBG_MII_BUS_GET_MAC(bus); + int ret; + + ret =3D hbg_mdio_check_op_status(mac); + if (ret) + return ret; + + ret =3D hbg_mdio_cmd_send(mac, phy_addr, regnum, HBG_MDIO_C22_MODE, + HBG_MDIO_C22_REG_READ); + if (ret) + return ret; + + return hbg_mdio_get_rdata_reg(mac); +} + +static int hbg_mdio_write22(struct mii_bus *bus, int phy_addr, int regnum, + u16 val) +{ + struct hbg_mac *mac =3D HBG_MII_BUS_GET_MAC(bus); + int ret; + + ret =3D hbg_mdio_check_op_status(mac); + if (ret) + return ret; + + hbg_mdio_set_wdata_reg(mac, val); + return hbg_mdio_cmd_send(mac, phy_addr, regnum, HBG_MDIO_C22_MODE, + HBG_MDIO_C22_REG_WRITE); +} + +static int hbg_mdio_init_hw(struct hbg_priv *priv) +{ + u32 freq =3D priv->dev_specs.mdio_frequency; + struct hbg_mac *mac =3D &priv->mac; + u32 cmd =3D 0; + + cmd |=3D FIELD_PREP(HBG_REG_MDIO_COMMAND_ST_M, HBG_MDIO_C22_MODE); + cmd |=3D FIELD_PREP(HBG_REG_MDIO_COMMAND_AUTO_SCAN_B, HBG_STATUS_DISABLE); + + /* freq use two bits, which are stored in clk_sel and clk_sel_exp */ + cmd |=3D FIELD_PREP(HBG_REG_MDIO_COMMAND_CLK_SEL_B, freq & 0x1); + cmd |=3D FIELD_PREP(HBG_REG_MDIO_COMMAND_CLK_SEL_EXP_B, (freq >> 1) & 0x1= ); + + hbg_mdio_set_command(mac, cmd); + return 0; +} + +static void hbg_phy_adjust_link(struct net_device *netdev) +{ + struct hbg_priv *priv =3D netdev_priv(netdev); + struct phy_device *phydev =3D netdev->phydev; + u32 speed; + + if (phydev->link !=3D priv->mac.link_status) { + if (phydev->link) { + switch (phydev->speed) { + case SPEED_10: + speed =3D HBG_PORT_MODE_SGMII_10M; + break; + case SPEED_100: + speed =3D HBG_PORT_MODE_SGMII_100M; + break; + case SPEED_1000: + speed =3D HBG_PORT_MODE_SGMII_1000M; + break; + default: + return; + } + + priv->mac.speed =3D speed; + priv->mac.duplex =3D phydev->duplex; + priv->mac.autoneg =3D phydev->autoneg; + hbg_hw_adjust_link(priv, speed, phydev->duplex); + } + + priv->mac.link_status =3D phydev->link; + phy_print_status(phydev); + } +} + +static void hbg_phy_disconnect(void *data) +{ + phy_disconnect((struct phy_device *)data); +} + +static int hbg_phy_connect(struct hbg_priv *priv) +{ + struct phy_device *phydev =3D priv->mac.phydev; + struct device *dev =3D &priv->pdev->dev; + int ret; + + ret =3D phy_connect_direct(priv->netdev, phydev, hbg_phy_adjust_link, + PHY_INTERFACE_MODE_SGMII); + if (ret) + return dev_err_probe(dev, ret, "failed to connect phy\n"); + + ret =3D devm_add_action_or_reset(dev, hbg_phy_disconnect, phydev); + if (ret) + return ret; + + phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); + phy_attached_info(phydev); + + return 0; +} + +void hbg_phy_start(struct hbg_priv *priv) +{ + phy_start(priv->mac.phydev); +} + +void hbg_phy_stop(struct hbg_priv *priv) +{ + phy_stop(priv->mac.phydev); +} + +int hbg_mdio_init(struct hbg_priv *priv) +{ + struct device *dev =3D &priv->pdev->dev; + struct hbg_mac *mac =3D &priv->mac; + struct phy_device *phydev; + struct mii_bus *mdio_bus; + int ret; + + mac->phy_addr =3D priv->dev_specs.phy_addr; + mdio_bus =3D devm_mdiobus_alloc(dev); + if (!mdio_bus) + return dev_err_probe(dev, -ENOMEM, "failed to alloc MDIO bus\n"); + + mdio_bus->parent =3D dev; + mdio_bus->priv =3D priv; + mdio_bus->phy_mask =3D ~(1 << mac->phy_addr); + mdio_bus->name =3D "hibmcge mii bus"; + mac->mdio_bus =3D mdio_bus; + + mdio_bus->read =3D hbg_mdio_read22; + mdio_bus->write =3D hbg_mdio_write22; + snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s-%s", "mii", dev_name(dev)); + + ret =3D devm_mdiobus_register(dev, mdio_bus); + if (ret) + return dev_err_probe(dev, ret, "failed to register MDIO bus\n"); + + phydev =3D mdiobus_get_phy(mdio_bus, mac->phy_addr); + if (!phydev) + return dev_err_probe(dev, -ENODEV, "failed to get phy device\n"); + + mac->phydev =3D phydev; + hbg_mdio_init_hw(priv); + return hbg_phy_connect(priv); +} diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_mdio.h b/drivers/ne= t/ethernet/hisilicon/hibmcge/hbg_mdio.h new file mode 100644 index 000000000000..febd02a309c7 --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_mdio.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (c) 2024 Hisilicon Limited. */ + +#ifndef __HBG_MDIO_H +#define __HBG_MDIO_H + +#include "hbg_common.h" + +int hbg_mdio_init(struct hbg_priv *priv); +void hbg_phy_start(struct hbg_priv *priv); +void hbg_phy_stop(struct hbg_priv *priv); +#endif diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h b/drivers/net= /ethernet/hisilicon/hibmcge/hbg_reg.h index 77153f1132fd..81e6d6e9a429 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h @@ -17,4 +17,59 @@ #define HBG_REG_RX_FIFO_NUM_ADDR 0x0034 #define HBG_REG_VLAN_LAYERS_ADDR 0x0038 =20 +/* MDIO */ +#define HBG_REG_MDIO_BASE 0x8000 +#define HBG_REG_MDIO_COMMAND_ADDR (HBG_REG_MDIO_BASE + 0x0000) +#define HBG_REG_MDIO_COMMAND_CLK_SEL_EXP_B BIT(17) +#define HBG_REG_MDIO_COMMAND_AUTO_SCAN_B BIT(16) +#define HBG_REG_MDIO_COMMAND_CLK_SEL_B BIT(15) +#define HBG_REG_MDIO_COMMAND_START_B BIT(14) +#define HBG_REG_MDIO_COMMAND_ST_M GENMASK(13, 12) +#define HBG_REG_MDIO_COMMAND_OP_M GENMASK(11, 10) +#define HBG_REG_MDIO_COMMAND_PRTAD_M GENMASK(9, 5) +#define HBG_REG_MDIO_COMMAND_DEVAD_M GENMASK(4, 0) +#define HBG_REG_MDIO_WDATA_ADDR (HBG_REG_MDIO_BASE + 0x0008) +#define HBG_REG_MDIO_WDATA_M GENMASK(15, 0) +#define HBG_REG_MDIO_RDATA_ADDR (HBG_REG_MDIO_BASE + 0x000C) +#define HBG_REG_MDIO_STA_ADDR (HBG_REG_MDIO_BASE + 0x0010) + +/* GMAC */ +#define HBG_REG_SGMII_BASE 0x10000 +#define HBG_REG_DUPLEX_TYPE_ADDR (HBG_REG_SGMII_BASE + 0x0008) +#define HBG_REG_DUPLEX_B BIT(0) +#define HBG_REG_PORT_MODE_ADDR (HBG_REG_SGMII_BASE + 0x0040) +#define HBG_REG_PORT_MODE_M GENMASK(3, 0) +#define HBG_REG_TRANSMIT_CONTROL_ADDR (HBG_REG_SGMII_BASE + 0x0060) +#define HBG_REG_TRANSMIT_CONTROL_PAD_EN_B BIT(7) +#define HBG_REG_TRANSMIT_CONTROL_CRC_ADD_B BIT(6) +#define HBG_REG_TRANSMIT_CONTROL_AN_EN_B BIT(5) +#define HBG_REG_CF_CRC_STRIP_ADDR (HBG_REG_SGMII_BASE + 0x01B0) +#define HBG_REG_CF_CRC_STRIP_B BIT(0) +#define HBG_REG_MODE_CHANGE_EN_ADDR (HBG_REG_SGMII_BASE + 0x01B4) +#define HBG_REG_MODE_CHANGE_EN_B BIT(0) +#define HBG_REG_RECV_CONTROL_ADDR (HBG_REG_SGMII_BASE + 0x01E0) +#define HBG_REG_RECV_CONTROL_STRIP_PAD_EN_B BIT(3) + +/* PCU */ +#define HBG_REG_RX_BUF_SIZE_ADDR (HBG_REG_SGMII_BASE + 0x04E4) +#define HBG_REG_RX_BUF_SIZE_M GENMASK(15, 0) +#define HBG_REG_BUS_CTRL_ADDR (HBG_REG_SGMII_BASE + 0x04E8) +#define HBG_REG_BUS_CTRL_ENDIAN_M GENMASK(2, 1) +#define HBG_REG_RX_CTRL_ADDR (HBG_REG_SGMII_BASE + 0x04F0) +#define HBG_REG_RX_CTRL_RXBUF_1ST_SKIP_SIZE_M GENMASK(31, 28) +#define HBG_REG_RX_CTRL_TIME_INF_EN_B BIT(23) +#define HBG_REG_RX_CTRL_RX_ALIGN_NUM_M GENMASK(18, 17) +#define HBG_REG_RX_CTRL_PORT_NUM GENMASK(16, 13) +#define HBG_REG_RX_CTRL_RX_GET_ADDR_MODE_B BIT(12) +#define HBG_REG_RX_CTRL_RXBUF_1ST_SKIP_SIZE2_M GENMASK(3, 0) +#define HBG_REG_RX_PKT_MODE_ADDR (HBG_REG_SGMII_BASE + 0x04F4) +#define HBG_REG_RX_PKT_MODE_PARSE_MODE_M GENMASK(22, 21) + +enum hbg_port_mode { + /* 0x0 ~ 0x5 are reserved */ + HBG_PORT_MODE_SGMII_10M =3D 0x6, + HBG_PORT_MODE_SGMII_100M =3D 0x7, + HBG_PORT_MODE_SGMII_1000M =3D 0x8, +}; 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charset="utf-8" The driver supports four interrupts: TX interrupt, RX interrupt, mdio interrupt, and error interrupt. Actually, the driver does not use the mdio interrupt. Therefore, the driver does not request the mdio interrupt. The error interrupt distinguishes different error information by using different masks. To distinguish different errors, the statistics count is added for each error. To ensure the consistency of the code process, masks are added for the TX interrupt and RX interrupt. This patch implements interrupt request, and provides a unified entry for the interrupt handler function. However, the specific interrupt handler function of each interrupt is not implemented currently. Because of pcim_enable_device(), the interrupt vector is already device managed and does not need to be free actively. Signed-off-by: Jijie Shao --- ChangeLog: RFC v1 -> RFC v2: - Replace request_irq with devm_request_irq, suggested by Jonathan. - Replace BIT_MASK() with BIT(), suggested by Jonathan. - Introduce irq_handle in struct hbg_irq_info in advance to reduce code c= hanges, suggested by Jonathan. RFC v1: https://lore.kernel.org/all/20240731094245.1967834-1-shaojijie@hu= awei.com/ --- .../ethernet/hisilicon/hibmcge/hbg_common.h | 18 +++ .../net/ethernet/hisilicon/hibmcge/hbg_hw.c | 55 +++++++++ .../net/ethernet/hisilicon/hibmcge/hbg_hw.h | 4 + .../net/ethernet/hisilicon/hibmcge/hbg_irq.c | 113 ++++++++++++++++++ .../net/ethernet/hisilicon/hibmcge/hbg_irq.h | 11 ++ .../net/ethernet/hisilicon/hibmcge/hbg_main.c | 5 + .../net/ethernet/hisilicon/hibmcge/hbg_reg.h | 27 +++++ 7 files changed, 233 insertions(+) create mode 100644 drivers/net/ethernet/hisilicon/hibmcge/hbg_irq.c create mode 100644 drivers/net/ethernet/hisilicon/hibmcge/hbg_irq.h diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h b/drivers/= net/ethernet/hisilicon/hibmcge/hbg_common.h index e047539a407a..e94ae2be5c4c 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h @@ -13,6 +13,7 @@ #define HBG_DEFAULT_MTU_SIZE 1500 #define HBG_RX_SKIP1 0x00 #define HBG_RX_SKIP2 0x01 +#define HBG_VECTOR_NUM 4 =20 enum hbg_nic_state { HBG_NIC_STATE_EVENT_HANDLING =3D 0, @@ -38,6 +39,22 @@ struct hbg_dev_specs { u32 rx_buf_size; }; =20 +struct hbg_irq_info { + const char *name; + u32 mask; + bool reenable; + bool need_print; + u64 count; + + void (*irq_handle)(struct hbg_priv *priv, struct hbg_irq_info *irq_info); +}; + +struct hbg_vector { + char name[HBG_VECTOR_NUM][32]; + struct hbg_irq_info *info_array; + u32 info_array_len; +}; + struct hbg_mac { struct mii_bus *mdio_bus; struct phy_device *phydev; @@ -56,6 +73,7 @@ struct hbg_priv { struct hbg_dev_specs dev_specs; unsigned long state; struct hbg_mac mac; + struct hbg_vector vectors; }; =20 #endif diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c b/drivers/net/= ethernet/hisilicon/hibmcge/hbg_hw.c index b1281b206f2f..8e971e9f62a0 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c @@ -74,6 +74,61 @@ static int hbg_hw_dev_specs_init(struct hbg_priv *priv) return 0; } =20 +u32 hbg_hw_get_irq_status(struct hbg_priv *priv) +{ + u32 status; + + status =3D hbg_reg_read(priv, HBG_REG_CF_INTRPT_STAT_ADDR); + + status |=3D FIELD_PREP(HBG_INT_MSK_TX_B, + hbg_reg_read(priv, HBG_REG_CF_IND_TXINT_STAT_ADDR)); + status |=3D FIELD_PREP(HBG_INT_MSK_RX_B, + hbg_reg_read(priv, HBG_REG_CF_IND_RXINT_STAT_ADDR)); + + return status; +} + +void hbg_hw_irq_clear(struct hbg_priv *priv, u32 mask) +{ + if (FIELD_GET(HBG_INT_MSK_TX_B, mask)) + return hbg_reg_write(priv, HBG_REG_CF_IND_TXINT_CLR_ADDR, 0x1); + + if (FIELD_GET(HBG_INT_MSK_RX_B, mask)) + return hbg_reg_write(priv, HBG_REG_CF_IND_RXINT_CLR_ADDR, 0x1); + + return hbg_reg_write(priv, HBG_REG_CF_INTRPT_CLR_ADDR, mask); +} + +bool hbg_hw_irq_is_enabled(struct hbg_priv *priv, u32 mask) +{ + if (FIELD_GET(HBG_INT_MSK_TX_B, mask)) + return hbg_reg_read(priv, HBG_REG_CF_IND_TXINT_MSK_ADDR); + + if (FIELD_GET(HBG_INT_MSK_RX_B, mask)) + return hbg_reg_read(priv, HBG_REG_CF_IND_RXINT_MSK_ADDR); + + return hbg_reg_read(priv, HBG_REG_CF_INTRPT_MSK_ADDR) & mask; +} + +void hbg_hw_irq_enable(struct hbg_priv *priv, u32 mask, bool enable) +{ + u32 value; + + if (FIELD_GET(HBG_INT_MSK_TX_B, mask)) + return hbg_reg_write(priv, HBG_REG_CF_IND_TXINT_MSK_ADDR, enable); + + if (FIELD_GET(HBG_INT_MSK_RX_B, mask)) + return hbg_reg_write(priv, HBG_REG_CF_IND_RXINT_MSK_ADDR, enable); + + value =3D hbg_reg_read(priv, HBG_REG_CF_INTRPT_MSK_ADDR); + if (enable) + value |=3D mask; + else + value &=3D ~mask; + + hbg_reg_write(priv, HBG_REG_CF_INTRPT_MSK_ADDR, value); +} + void hbg_hw_adjust_link(struct hbg_priv *priv, u32 speed, u32 duplex) { hbg_reg_write_field(priv, HBG_REG_PORT_MODE_ADDR, diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h b/drivers/net/= ethernet/hisilicon/hibmcge/hbg_hw.h index 47df597b885f..4d09bdd41c76 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h @@ -45,5 +45,9 @@ int hbg_hw_event_notify(struct hbg_priv *priv, enum hbg_hw_event_type event_type); int hbg_hw_init(struct hbg_priv *priv); void hbg_hw_adjust_link(struct hbg_priv *priv, u32 speed, u32 duplex); +u32 hbg_hw_get_irq_status(struct hbg_priv *priv); +void hbg_hw_irq_clear(struct hbg_priv *priv, u32 mask); +bool hbg_hw_irq_is_enabled(struct hbg_priv *priv, u32 mask); +void hbg_hw_irq_enable(struct hbg_priv *priv, u32 mask, bool enable); =20 #endif diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_irq.c b/drivers/net= /ethernet/hisilicon/hibmcge/hbg_irq.c new file mode 100644 index 000000000000..0a70853a4928 --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_irq.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2024 Hisilicon Limited. + +#include +#include "hbg_irq.h" +#include "hbg_hw.h" + +static void hbg_irq_handle_err(struct hbg_priv *priv, + struct hbg_irq_info *irq_info) +{ + if (irq_info->need_print) + dev_err(&priv->pdev->dev, + "receive error interrupt: %s\n", irq_info->name); +} + +#define HBG_TXRX_IRQ_I(name, handle) \ + {#name, HBG_INT_MSK_##name##_B, false, false, 0, handle} +#define HBG_ERR_IRQ_I(name, need_print) \ + {#name, HBG_INT_MSK_##name##_B, true, need_print, 0, hbg_irq_handle_err} + +static struct hbg_irq_info hbg_irqs[] =3D { + HBG_TXRX_IRQ_I(RX, NULL), + HBG_TXRX_IRQ_I(TX, NULL), + HBG_ERR_IRQ_I(MAC_MII_FIFO_ERR, true), + HBG_ERR_IRQ_I(MAC_PCS_RX_FIFO_ERR, true), + HBG_ERR_IRQ_I(MAC_PCS_TX_FIFO_ERR, true), + HBG_ERR_IRQ_I(MAC_APP_RX_FIFO_ERR, true), + HBG_ERR_IRQ_I(MAC_APP_TX_FIFO_ERR, true), + HBG_ERR_IRQ_I(SRAM_PARITY_ERR, true), + HBG_ERR_IRQ_I(TX_AHB_ERR, true), + HBG_ERR_IRQ_I(RX_BUF_AVL, false), + HBG_ERR_IRQ_I(REL_BUF_ERR, true), + HBG_ERR_IRQ_I(TXCFG_AVL, false), + HBG_ERR_IRQ_I(TX_DROP, false), + HBG_ERR_IRQ_I(RX_DROP, false), + HBG_ERR_IRQ_I(RX_AHB_ERR, true), + HBG_ERR_IRQ_I(MAC_FIFO_ERR, false), + HBG_ERR_IRQ_I(RBREQ_ERR, false), + HBG_ERR_IRQ_I(WE_ERR, false), +}; + +static irqreturn_t hbg_irq_handle(int irq_num, void *p) +{ + struct hbg_irq_info *info; + struct hbg_priv *priv =3D p; + u32 status; + u32 i; + + status =3D hbg_hw_get_irq_status(priv); + for (i =3D 0; i < priv->vectors.info_array_len; i++) { + info =3D &priv->vectors.info_array[i]; + if (status & info->mask) { + if (!hbg_hw_irq_is_enabled(priv, info->mask)) + continue; + + hbg_hw_irq_enable(priv, info->mask, false); + hbg_hw_irq_clear(priv, info->mask); + + info->count++; + if (info->irq_handle) + info->irq_handle(priv, info); + + if (info->reenable) + hbg_hw_irq_enable(priv, info->mask, true); + } + } + + return IRQ_HANDLED; +} + +static const char *irq_names_map[HBG_VECTOR_NUM] =3D { "tx", "rx", "err", = "mdio" }; + +int hbg_irq_init(struct hbg_priv *priv) +{ + struct hbg_vector *vectors =3D &priv->vectors; + struct device *dev =3D &priv->pdev->dev; + int ret, id; + u32 i; + + /* used pcim_enable_device(), so the vectors become device managed */ + ret =3D pci_alloc_irq_vectors(priv->pdev, HBG_VECTOR_NUM, HBG_VECTOR_NUM, + PCI_IRQ_MSI | PCI_IRQ_MSIX); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to allocate MSI vectors\n"); + + if (ret !=3D HBG_VECTOR_NUM) + return dev_err_probe(dev, -EINVAL, + "requested %u MSI, but allocated %d MSI\n", + HBG_VECTOR_NUM, ret); + + /* mdio irq not request, so the number of requested interrupts + * is HBG_VECTOR_NUM - 1. + */ + for (i =3D 0; i < HBG_VECTOR_NUM - 1; i++) { + id =3D pci_irq_vector(priv->pdev, i); + if (id < 0) + return dev_err_probe(dev, id, "failed to get irq number\n"); + + snprintf(vectors->name[i], sizeof(vectors->name[i]), "%s-%s-%s", + dev_driver_string(dev), pci_name(priv->pdev), + irq_names_map[i]); + + ret =3D devm_request_irq(dev, id, hbg_irq_handle, 0, + vectors->name[i], priv); + if (ret) + return dev_err_probe(dev, ret, + "failed to requset irq(%d)\n", id); + } + + vectors->info_array =3D hbg_irqs; + vectors->info_array_len =3D ARRAY_SIZE(hbg_irqs); + return 0; +} diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_irq.h b/drivers/net= /ethernet/hisilicon/hibmcge/hbg_irq.h new file mode 100644 index 000000000000..5c5323cfc751 --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_irq.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (c) 2024 Hisilicon Limited. */ + +#ifndef __HBG_IRQ_H +#define __HBG_IRQ_H + +#include "hbg_common.h" + +int hbg_irq_init(struct hbg_priv *priv); + +#endif diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c b/drivers/ne= t/ethernet/hisilicon/hibmcge/hbg_main.c index 22b6557247c4..29e0513fa836 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c @@ -6,6 +6,7 @@ #include #include "hbg_common.h" #include "hbg_hw.h" +#include "hbg_irq.h" #include "hbg_mdio.h" =20 static int hbg_init(struct hbg_priv *priv) @@ -20,6 +21,10 @@ static int hbg_init(struct hbg_priv *priv) if (ret) return ret; =20 + ret =3D hbg_irq_init(priv); + if (ret) + return ret; + return hbg_mdio_init(priv); } =20 diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h b/drivers/net= /ethernet/hisilicon/hibmcge/hbg_reg.h index 81e6d6e9a429..b0991063ccba 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h @@ -51,6 +51,27 @@ #define HBG_REG_RECV_CONTROL_STRIP_PAD_EN_B BIT(3) =20 /* PCU */ +#define HBG_REG_CF_INTRPT_MSK_ADDR (HBG_REG_SGMII_BASE + 0x042C) +#define HBG_INT_MSK_WE_ERR_B BIT(31) +#define HBG_INT_MSK_RBREQ_ERR_B BIT(30) +#define HBG_INT_MSK_MAC_FIFO_ERR_B BIT(29) +#define HBG_INT_MSK_RX_AHB_ERR_B BIT(28) +#define HBG_INT_MSK_RX_DROP_B BIT(26) +#define HBG_INT_MSK_TX_DROP_B BIT(25) +#define HBG_INT_MSK_TXCFG_AVL_B BIT(24) +#define HBG_INT_MSK_REL_BUF_ERR_B BIT(23) +#define HBG_INT_MSK_RX_BUF_AVL_B BIT(22) +#define HBG_INT_MSK_TX_AHB_ERR_B BIT(21) +#define HBG_INT_MSK_SRAM_PARITY_ERR_B BIT(20) +#define HBG_INT_MSK_MAC_APP_TX_FIFO_ERR_B BIT(19) +#define HBG_INT_MSK_MAC_APP_RX_FIFO_ERR_B BIT(18) +#define HBG_INT_MSK_MAC_PCS_TX_FIFO_ERR_B BIT(17) +#define HBG_INT_MSK_MAC_PCS_RX_FIFO_ERR_B BIT(16) +#define HBG_INT_MSK_MAC_MII_FIFO_ERR_B BIT(15) +#define HBG_INT_MSK_TX_B BIT(1) /* just used in driver */ +#define HBG_INT_MSK_RX_B BIT(0) /* just used in driver */ +#define HBG_REG_CF_INTRPT_STAT_ADDR (HBG_REG_SGMII_BASE + 0x0434) +#define HBG_REG_CF_INTRPT_CLR_ADDR (HBG_REG_SGMII_BASE + 0x0438) #define HBG_REG_RX_BUF_SIZE_ADDR (HBG_REG_SGMII_BASE + 0x04E4) #define HBG_REG_RX_BUF_SIZE_M GENMASK(15, 0) #define HBG_REG_BUS_CTRL_ADDR (HBG_REG_SGMII_BASE + 0x04E8) @@ -64,6 +85,12 @@ #define HBG_REG_RX_CTRL_RXBUF_1ST_SKIP_SIZE2_M GENMASK(3, 0) #define HBG_REG_RX_PKT_MODE_ADDR (HBG_REG_SGMII_BASE + 0x04F4) #define HBG_REG_RX_PKT_MODE_PARSE_MODE_M GENMASK(22, 21) +#define HBG_REG_CF_IND_TXINT_MSK_ADDR (HBG_REG_SGMII_BASE + 0x0694) +#define HBG_REG_CF_IND_TXINT_STAT_ADDR (HBG_REG_SGMII_BASE + 0x0698) +#define HBG_REG_CF_IND_TXINT_CLR_ADDR (HBG_REG_SGMII_BASE + 0x069C) +#define HBG_REG_CF_IND_RXINT_MSK_ADDR (HBG_REG_SGMII_BASE + 0x06a0) +#define HBG_REG_CF_IND_RXINT_STAT_ADDR (HBG_REG_SGMII_BASE + 0x06a4) +#define HBG_REG_CF_IND_RXINT_CLR_ADDR (HBG_REG_SGMII_BASE + 0x06a8) =20 enum hbg_port_mode { /* 0x0 ~ 0x5 are reserved */ --=20 2.33.0 From nobody Sat Nov 30 10:39:28 2024 Received: from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99E44174EFC; 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dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.163]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4X2x8l66Mrz1SB5t; Tue, 10 Sep 2024 16:05:43 +0800 (CST) Received: from kwepemm000007.china.huawei.com (unknown [7.193.23.189]) by mail.maildlp.com (Postfix) with ESMTPS id 57879180041; Tue, 10 Sep 2024 16:06:12 +0800 (CST) Received: from localhost.localdomain (10.90.30.45) by kwepemm000007.china.huawei.com (7.193.23.189) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 10 Sep 2024 16:06:11 +0800 From: Jijie Shao To: , , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH V9 net-next 05/11] net: hibmcge: Implement some .ndo functions Date: Tue, 10 Sep 2024 15:59:36 +0800 Message-ID: <20240910075942.1270054-6-shaojijie@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20240910075942.1270054-1-shaojijie@huawei.com> References: <20240910075942.1270054-1-shaojijie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemm000007.china.huawei.com (7.193.23.189) Content-Type: text/plain; charset="utf-8" Implement the .ndo_open() .ndo_stop() .ndo_set_mac_address() .ndo_change_mtu functions() and ndo.get_stats64() And .ndo_validate_addr calls the eth_validate_addr function directly Signed-off-by: Jijie Shao Reviewed-by: Kalesh AP --- ChangeLog: v8 -> v9: - Remove HBG_NIC_STATE_OPEN in ndo.open() and ndo.stop(), suggested by Kalesh and Andrew. - Use netif_running() instead of hbg_nic_is_open() in ndo.change_mtu(), suggested by Kalesh and Andrew v8: https://lore.kernel.org/all/20240909023141.3234567-1-shaojijie@huawei= .com/ v6 -> v7: - Add implement ndo.get_stats64(), suggested by Paolo. v6: https://lore.kernel.org/all/20240830121604.2250904-6-shaojijie@huawei= .com/ v5 -> v6: - Delete netif_carrier_off() in .ndo_open() and .ndo_stop(), suggested by Jakub and Andrew. v5: https://lore.kernel.org/all/20240827131455.2919051-1-shaojijie@huawei.= com/ v3 -> v4: - Delete INITED_STATE in priv, suggested by Andrew. - Delete unnecessary defensive code in hbg_phy_start() and hbg_phy_stop(), suggested by Andrew. v3: https://lore.kernel.org/all/20240822093334.1687011-1-shaojijie@huawei= .com/ RFC v1 -> RFC v2: - Delete validation for mtu in hbg_net_change_mtu(), suggested by Andrew. - Delete validation for mac address in hbg_net_set_mac_address(), suggested by Andrew. - Add a patch to add is_valid_ether_addr check in dev_set_mac_address, suggested by Andrew. RFC v1: https://lore.kernel.org/all/20240731094245.1967834-1-shaojijie@hu= awei.com/ --- .../net/ethernet/hisilicon/hibmcge/hbg_hw.c | 39 ++++++++ .../net/ethernet/hisilicon/hibmcge/hbg_hw.h | 3 + .../net/ethernet/hisilicon/hibmcge/hbg_main.c | 97 +++++++++++++++++++ .../net/ethernet/hisilicon/hibmcge/hbg_reg.h | 11 ++- 4 files changed, 149 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c b/drivers/net/= ethernet/hisilicon/hibmcge/hbg_hw.c index 8e971e9f62a0..97fee714155a 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c @@ -15,6 +15,7 @@ * ctrl means packet description, data means skb packet data */ #define HBG_ENDIAN_CTRL_LE_DATA_BE 0x0 +#define HBG_PCU_FRAME_LEN_PLUS 4 =20 static bool hbg_hw_spec_is_valid(struct hbg_priv *priv) { @@ -129,6 +130,44 @@ void hbg_hw_irq_enable(struct hbg_priv *priv, u32 mask= , bool enable) hbg_reg_write(priv, HBG_REG_CF_INTRPT_MSK_ADDR, value); } =20 +void hbg_hw_set_uc_addr(struct hbg_priv *priv, u64 mac_addr) +{ + hbg_reg_write64(priv, HBG_REG_STATION_ADDR_LOW_2_ADDR, mac_addr); +} + +static void hbg_hw_set_pcu_max_frame_len(struct hbg_priv *priv, + u16 max_frame_len) +{ + max_frame_len =3D max_t(u32, max_frame_len, HBG_DEFAULT_MTU_SIZE); + + /* lower two bits of value must be set to 0. Otherwise, the value is igno= red */ + max_frame_len =3D round_up(max_frame_len, HBG_PCU_FRAME_LEN_PLUS); + + hbg_reg_write_field(priv, HBG_REG_MAX_FRAME_LEN_ADDR, + HBG_REG_MAX_FRAME_LEN_M, max_frame_len); +} + +static void hbg_hw_set_mac_max_frame_len(struct hbg_priv *priv, + u16 max_frame_size) +{ + hbg_reg_write_field(priv, HBG_REG_MAX_FRAME_SIZE_ADDR, + HBG_REG_MAX_FRAME_LEN_M, max_frame_size); +} + +void hbg_hw_set_mtu(struct hbg_priv *priv, u16 mtu) +{ + hbg_hw_set_pcu_max_frame_len(priv, mtu); + hbg_hw_set_mac_max_frame_len(priv, mtu); +} + +void hbg_hw_mac_enable(struct hbg_priv *priv, u32 enable) +{ + hbg_reg_write_field(priv, HBG_REG_PORT_ENABLE_ADDR, + HBG_REG_PORT_ENABLE_TX_B, enable); + hbg_reg_write_field(priv, HBG_REG_PORT_ENABLE_ADDR, + HBG_REG_PORT_ENABLE_RX_B, enable); +} + void hbg_hw_adjust_link(struct hbg_priv *priv, u32 speed, u32 duplex) { hbg_reg_write_field(priv, HBG_REG_PORT_MODE_ADDR, diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h b/drivers/net/= ethernet/hisilicon/hibmcge/hbg_hw.h index 4d09bdd41c76..0ce500e907b3 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h @@ -49,5 +49,8 @@ u32 hbg_hw_get_irq_status(struct hbg_priv *priv); void hbg_hw_irq_clear(struct hbg_priv *priv, u32 mask); bool hbg_hw_irq_is_enabled(struct hbg_priv *priv, u32 mask); void hbg_hw_irq_enable(struct hbg_priv *priv, u32 mask, bool enable); +void hbg_hw_set_mtu(struct hbg_priv *priv, u16 mtu); +void hbg_hw_mac_enable(struct hbg_priv *priv, u32 enable); +void hbg_hw_set_uc_addr(struct hbg_priv *priv, u64 mac_addr); =20 #endif diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c b/drivers/ne= t/ethernet/hisilicon/hibmcge/hbg_main.c index 29e0513fa836..d882a7822299 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c @@ -2,6 +2,7 @@ // Copyright (c) 2024 Hisilicon Limited. =20 #include +#include #include #include #include "hbg_common.h" @@ -9,6 +10,97 @@ #include "hbg_irq.h" #include "hbg_mdio.h" =20 +static void hbg_all_irq_enable(struct hbg_priv *priv, bool enabled) +{ + struct hbg_irq_info *info; + u32 i; + + for (i =3D 0; i < priv->vectors.info_array_len; i++) { + info =3D &priv->vectors.info_array[i]; + hbg_hw_irq_enable(priv, info->mask, enabled); + } +} + +static int hbg_net_open(struct net_device *netdev) +{ + struct hbg_priv *priv =3D netdev_priv(netdev); + + hbg_all_irq_enable(priv, true); + hbg_hw_mac_enable(priv, HBG_STATUS_ENABLE); + netif_start_queue(netdev); + hbg_phy_start(priv); + + return 0; +} + +static int hbg_net_stop(struct net_device *netdev) +{ + struct hbg_priv *priv =3D netdev_priv(netdev); + + hbg_phy_stop(priv); + netif_stop_queue(netdev); + hbg_hw_mac_enable(priv, HBG_STATUS_DISABLE); + hbg_all_irq_enable(priv, false); + + return 0; +} + +static int hbg_net_set_mac_address(struct net_device *netdev, void *addr) +{ + struct hbg_priv *priv =3D netdev_priv(netdev); + u8 *mac_addr; + + mac_addr =3D ((struct sockaddr *)addr)->sa_data; + + hbg_hw_set_uc_addr(priv, ether_addr_to_u64(mac_addr)); + dev_addr_set(netdev, mac_addr); + + return 0; +} + +static void hbg_change_mtu(struct hbg_priv *priv, int new_mtu) +{ + u32 frame_len; + + frame_len =3D new_mtu + VLAN_HLEN * priv->dev_specs.vlan_layers + + ETH_HLEN + ETH_FCS_LEN; + hbg_hw_set_mtu(priv, frame_len); +} + +static int hbg_net_change_mtu(struct net_device *netdev, int new_mtu) +{ + struct hbg_priv *priv =3D netdev_priv(netdev); + bool is_running =3D netif_running(netdev); + + if (is_running) + hbg_net_stop(netdev); + + hbg_change_mtu(priv, new_mtu); + WRITE_ONCE(netdev->mtu, new_mtu); + + dev_dbg(&priv->pdev->dev, + "change mtu from %u to %u\n", netdev->mtu, new_mtu); + if (is_running) + hbg_net_open(netdev); + return 0; +} + +static void hbg_net_get_stats64(struct net_device *netdev, + struct rtnl_link_stats64 *stats) +{ + netdev_stats_to_stats64(stats, &netdev->stats); + dev_fetch_sw_netstats(stats, netdev->tstats); +} + +static const struct net_device_ops hbg_netdev_ops =3D { + .ndo_open =3D hbg_net_open, + .ndo_stop =3D hbg_net_stop, + .ndo_validate_addr =3D eth_validate_addr, + .ndo_set_mac_address =3D hbg_net_set_mac_address, + .ndo_change_mtu =3D hbg_net_change_mtu, + .ndo_get_stats64 =3D hbg_net_get_stats64, +}; + static int hbg_init(struct hbg_priv *priv) { int ret; @@ -73,6 +165,7 @@ static int hbg_probe(struct pci_dev *pdev, const struct = pci_device_id *ent) priv =3D netdev_priv(netdev); priv->netdev =3D netdev; priv->pdev =3D pdev; + netdev->netdev_ops =3D &hbg_netdev_ops; =20 netdev->tstats =3D devm_netdev_alloc_pcpu_stats(&pdev->dev, struct pcpu_sw_netstats); @@ -88,6 +181,10 @@ static int hbg_probe(struct pci_dev *pdev, const struct= pci_device_id *ent) if (ret) return ret; =20 + netdev->max_mtu =3D priv->dev_specs.max_mtu; + netdev->min_mtu =3D priv->dev_specs.min_mtu; + hbg_change_mtu(priv, HBG_DEFAULT_MTU_SIZE); + hbg_net_set_mac_address(priv->netdev, &priv->dev_specs.mac_addr); ret =3D devm_register_netdev(dev, netdev); if (ret) return dev_err_probe(dev, ret, "failed to register netdev\n"); diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h b/drivers/net= /ethernet/hisilicon/hibmcge/hbg_reg.h index b0991063ccba..63bb1bead8c0 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h @@ -37,18 +37,24 @@ #define HBG_REG_SGMII_BASE 0x10000 #define HBG_REG_DUPLEX_TYPE_ADDR (HBG_REG_SGMII_BASE + 0x0008) #define HBG_REG_DUPLEX_B BIT(0) +#define HBG_REG_MAX_FRAME_SIZE_ADDR (HBG_REG_SGMII_BASE + 0x003C) #define HBG_REG_PORT_MODE_ADDR (HBG_REG_SGMII_BASE + 0x0040) #define HBG_REG_PORT_MODE_M GENMASK(3, 0) +#define HBG_REG_PORT_ENABLE_ADDR (HBG_REG_SGMII_BASE + 0x0044) +#define HBG_REG_PORT_ENABLE_RX_B BIT(1) +#define HBG_REG_PORT_ENABLE_TX_B BIT(2) #define HBG_REG_TRANSMIT_CONTROL_ADDR (HBG_REG_SGMII_BASE + 0x0060) #define HBG_REG_TRANSMIT_CONTROL_PAD_EN_B BIT(7) #define HBG_REG_TRANSMIT_CONTROL_CRC_ADD_B BIT(6) #define HBG_REG_TRANSMIT_CONTROL_AN_EN_B BIT(5) #define HBG_REG_CF_CRC_STRIP_ADDR (HBG_REG_SGMII_BASE + 0x01B0) -#define HBG_REG_CF_CRC_STRIP_B BIT(0) +#define HBG_REG_CF_CRC_STRIP_B BIT(1) #define HBG_REG_MODE_CHANGE_EN_ADDR (HBG_REG_SGMII_BASE + 0x01B4) #define HBG_REG_MODE_CHANGE_EN_B BIT(0) #define HBG_REG_RECV_CONTROL_ADDR (HBG_REG_SGMII_BASE + 0x01E0) #define HBG_REG_RECV_CONTROL_STRIP_PAD_EN_B BIT(3) +#define HBG_REG_STATION_ADDR_LOW_2_ADDR (HBG_REG_SGMII_BASE + 0x0210) +#define HBG_REG_STATION_ADDR_HIGH_2_ADDR (HBG_REG_SGMII_BASE + 0x0214) =20 /* PCU */ #define HBG_REG_CF_INTRPT_MSK_ADDR (HBG_REG_SGMII_BASE + 0x042C) @@ -72,6 +78,8 @@ #define HBG_INT_MSK_RX_B BIT(0) /* just used in driver */ #define HBG_REG_CF_INTRPT_STAT_ADDR (HBG_REG_SGMII_BASE + 0x0434) #define HBG_REG_CF_INTRPT_CLR_ADDR (HBG_REG_SGMII_BASE + 0x0438) +#define HBG_REG_MAX_FRAME_LEN_ADDR (HBG_REG_SGMII_BASE + 0x0444) +#define HBG_REG_MAX_FRAME_LEN_M GENMASK(15, 0) #define HBG_REG_RX_BUF_SIZE_ADDR (HBG_REG_SGMII_BASE + 0x04E4) #define HBG_REG_RX_BUF_SIZE_M GENMASK(15, 0) #define HBG_REG_BUS_CTRL_ADDR (HBG_REG_SGMII_BASE + 0x04E8) @@ -86,6 +94,7 @@ #define HBG_REG_RX_PKT_MODE_ADDR (HBG_REG_SGMII_BASE + 0x04F4) #define HBG_REG_RX_PKT_MODE_PARSE_MODE_M GENMASK(22, 21) #define HBG_REG_CF_IND_TXINT_MSK_ADDR (HBG_REG_SGMII_BASE + 0x0694) +#define HBG_REG_IND_INTR_MASK_B BIT(0) #define HBG_REG_CF_IND_TXINT_STAT_ADDR (HBG_REG_SGMII_BASE + 0x0698) #define HBG_REG_CF_IND_TXINT_CLR_ADDR (HBG_REG_SGMII_BASE + 0x069C) #define HBG_REG_CF_IND_RXINT_MSK_ADDR (HBG_REG_SGMII_BASE + 0x06a0) --=20 2.33.0 From nobody Sat Nov 30 10:39:28 2024 Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CD5D186618; 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dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.162.112]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4X2x8n2wMTz1j8Qy; Tue, 10 Sep 2024 16:05:45 +0800 (CST) Received: from kwepemm000007.china.huawei.com (unknown [7.193.23.189]) by mail.maildlp.com (Postfix) with ESMTPS id 2290E1401F3; Tue, 10 Sep 2024 16:06:13 +0800 (CST) Received: from localhost.localdomain (10.90.30.45) by kwepemm000007.china.huawei.com (7.193.23.189) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 10 Sep 2024 16:06:12 +0800 From: Jijie Shao To: , , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH V9 net-next 06/11] net: hibmcge: Implement .ndo_start_xmit function Date: Tue, 10 Sep 2024 15:59:37 +0800 Message-ID: <20240910075942.1270054-7-shaojijie@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20240910075942.1270054-1-shaojijie@huawei.com> References: <20240910075942.1270054-1-shaojijie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemm000007.china.huawei.com (7.193.23.189) Content-Type: text/plain; charset="utf-8" Implement .ndo_start_xmit function to fill the information of the packet to be transmitted into the tx descriptor, and then the hardware will transmit the packet using the information in the tx descriptor. In addition, we also implemented the tx_handler function to enable the tx descriptor to be reused, and .ndo_tx_timeout function to print some information when the hardware is busy. Signed-off-by: Jijie Shao --- ChangeLog: v8 -> v9: - Remove hbg_nic_is_open() judgment from ndo.xmit() v8: https://lore.kernel.org/all/20240909023141.3234567-1-shaojijie@huawei= .com/ v6 -> v7: - Add check for netif_txq_maybe_stop(), suggested by Paolo. - Use dev_sw_netstats_tx_add() instead of dev->stats, suggested by Paolo. v6: https://lore.kernel.org/all/20240830121604.2250904-7-shaojijie@huawei= .com/ v5 -> v6: - Remove hbg_txrx_init() from probe path, alloc ring buffer in .ndo_open(= ), and release ring buffer in .ndo_stop(), suggested by Jakub and Andrew. v5: https://lore.kernel.org/all/20240827131455.2919051-1-shaojijie@huawei= .com/ v4 -> v5: - Delete unnecessary semicolon, suggested by Jakub. v4: https://lore.kernel.org/all/20240826081258.1881385-1-shaojijie@huawei= .com/ RFC v1 -> RFC v2: - Use napi_complete_done() to simplify the process, suggested by Joe Dama= to. RFC v1: https://lore.kernel.org/all/20240731094245.1967834-1-shaojijie@hu= awei.com/ --- .../ethernet/hisilicon/hibmcge/hbg_common.h | 50 ++++ .../net/ethernet/hisilicon/hibmcge/hbg_hw.c | 18 ++ .../net/ethernet/hisilicon/hibmcge/hbg_hw.h | 2 + .../net/ethernet/hisilicon/hibmcge/hbg_irq.c | 8 +- .../net/ethernet/hisilicon/hibmcge/hbg_main.c | 54 +++- .../net/ethernet/hisilicon/hibmcge/hbg_reg.h | 19 ++ .../net/ethernet/hisilicon/hibmcge/hbg_txrx.c | 261 ++++++++++++++++++ .../net/ethernet/hisilicon/hibmcge/hbg_txrx.h | 37 +++ 8 files changed, 446 insertions(+), 3 deletions(-) create mode 100644 drivers/net/ethernet/hisilicon/hibmcge/hbg_txrx.c create mode 100644 drivers/net/ethernet/hisilicon/hibmcge/hbg_txrx.h diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h b/drivers/= net/ethernet/hisilicon/hibmcge/hbg_common.h index e94ae2be5c4c..31fb03f75d31 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h @@ -14,14 +14,63 @@ #define HBG_RX_SKIP1 0x00 #define HBG_RX_SKIP2 0x01 #define HBG_VECTOR_NUM 4 +#define HBG_PCU_CACHE_LINE_SIZE 32 +#define HBG_TX_TIMEOUT_BUF_LEN 1024 + +enum hbg_dir { + HBG_DIR_TX =3D 1 << 0, + HBG_DIR_RX =3D 1 << 1, + HBG_DIR_TX_RX =3D HBG_DIR_TX | HBG_DIR_RX, +}; + +enum hbg_tx_state { + HBG_TX_STATE_COMPLETE =3D 0, /* clear state, must fix to 0 */ + HBG_TX_STATE_START, +}; =20 enum hbg_nic_state { HBG_NIC_STATE_EVENT_HANDLING =3D 0, }; =20 +struct hbg_priv; +struct hbg_ring; +struct hbg_buffer { + u32 state; + dma_addr_t state_dma; + + struct sk_buff *skb; + dma_addr_t skb_dma; + u32 skb_len; + + enum hbg_dir dir; + struct hbg_ring *ring; + struct hbg_priv *priv; +}; + +struct hbg_ring { + struct hbg_buffer *queue; + dma_addr_t queue_dma; + + union { + u32 head; + u32 ntc; + }; + union { + u32 tail; + u32 ntu; + }; + u32 len; + + enum hbg_dir dir; + struct hbg_priv *priv; + struct napi_struct napi; + char *tout_log_buf; /* tx timeout log buffer */ +}; + enum hbg_hw_event_type { HBG_HW_EVENT_NONE =3D 0, HBG_HW_EVENT_INIT, /* driver is loading */ + HBG_HW_EVENT_RESET, }; =20 struct hbg_dev_specs { @@ -74,6 +123,7 @@ struct hbg_priv { unsigned long state; struct hbg_mac mac; struct hbg_vector vectors; + struct hbg_ring tx_ring; }; =20 #endif diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c b/drivers/net/= ethernet/hisilicon/hibmcge/hbg_hw.c index 97fee714155a..61e02811c165 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c @@ -72,6 +72,7 @@ static int hbg_hw_dev_specs_init(struct hbg_priv *priv) if (!is_valid_ether_addr((u8 *)dev_specs->mac_addr.sa_data)) return -EADDRNOTAVAIL; =20 + dev_specs->max_frame_len =3D HBG_PCU_CACHE_LINE_SIZE + dev_specs->max_mtu; return 0; } =20 @@ -168,6 +169,23 @@ void hbg_hw_mac_enable(struct hbg_priv *priv, u32 enab= le) HBG_REG_PORT_ENABLE_RX_B, enable); } =20 +u32 hbg_hw_get_fifo_used_num(struct hbg_priv *priv, enum hbg_dir dir) +{ + if (dir & HBG_DIR_TX) + return hbg_reg_read_field(priv, HBG_REG_CF_CFF_DATA_NUM_ADDR, + HBG_REG_CF_CFF_DATA_NUM_ADDR_TX_M); + + return 0; +} + +void hbg_hw_set_tx_desc(struct hbg_priv *priv, struct hbg_tx_desc *tx_desc) +{ + hbg_reg_write(priv, HBG_REG_TX_CFF_ADDR_0_ADDR, tx_desc->word0); + hbg_reg_write(priv, HBG_REG_TX_CFF_ADDR_1_ADDR, tx_desc->word1); + hbg_reg_write(priv, HBG_REG_TX_CFF_ADDR_2_ADDR, tx_desc->word2); + hbg_reg_write(priv, HBG_REG_TX_CFF_ADDR_3_ADDR, tx_desc->word3); +} + void hbg_hw_adjust_link(struct hbg_priv *priv, u32 speed, u32 duplex) { hbg_reg_write_field(priv, HBG_REG_PORT_MODE_ADDR, diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h b/drivers/net/= ethernet/hisilicon/hibmcge/hbg_hw.h index 0ce500e907b3..508e41cce41e 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h @@ -52,5 +52,7 @@ void hbg_hw_irq_enable(struct hbg_priv *priv, u32 mask, b= ool enable); void hbg_hw_set_mtu(struct hbg_priv *priv, u16 mtu); void hbg_hw_mac_enable(struct hbg_priv *priv, u32 enable); void hbg_hw_set_uc_addr(struct hbg_priv *priv, u64 mac_addr); +u32 hbg_hw_get_fifo_used_num(struct hbg_priv *priv, enum hbg_dir dir); +void hbg_hw_set_tx_desc(struct hbg_priv *priv, struct hbg_tx_desc *tx_desc= ); =20 #endif diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_irq.c b/drivers/net= /ethernet/hisilicon/hibmcge/hbg_irq.c index 0a70853a4928..bf5bfedd8a8c 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_irq.c +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_irq.c @@ -13,6 +13,12 @@ static void hbg_irq_handle_err(struct hbg_priv *priv, "receive error interrupt: %s\n", irq_info->name); } =20 +static void hbg_irq_handle_tx(struct hbg_priv *priv, + struct hbg_irq_info *irq_info) +{ + napi_schedule(&priv->tx_ring.napi); +} + #define HBG_TXRX_IRQ_I(name, handle) \ {#name, HBG_INT_MSK_##name##_B, false, false, 0, handle} #define HBG_ERR_IRQ_I(name, need_print) \ @@ -20,7 +26,7 @@ static void hbg_irq_handle_err(struct hbg_priv *priv, =20 static struct hbg_irq_info hbg_irqs[] =3D { HBG_TXRX_IRQ_I(RX, NULL), - HBG_TXRX_IRQ_I(TX, NULL), + HBG_TXRX_IRQ_I(TX, hbg_irq_handle_tx), HBG_ERR_IRQ_I(MAC_MII_FIFO_ERR, true), HBG_ERR_IRQ_I(MAC_PCS_RX_FIFO_ERR, true), HBG_ERR_IRQ_I(MAC_PCS_TX_FIFO_ERR, true), diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c b/drivers/ne= t/ethernet/hisilicon/hibmcge/hbg_main.c index d882a7822299..a8d0e951633b 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c @@ -9,6 +9,9 @@ #include "hbg_hw.h" #include "hbg_irq.h" #include "hbg_mdio.h" +#include "hbg_txrx.h" + +static void hbg_change_mtu(struct hbg_priv *priv, int new_mtu); =20 static void hbg_all_irq_enable(struct hbg_priv *priv, bool enabled) { @@ -24,6 +27,11 @@ static void hbg_all_irq_enable(struct hbg_priv *priv, bo= ol enabled) static int hbg_net_open(struct net_device *netdev) { struct hbg_priv *priv =3D netdev_priv(netdev); + int ret; + + ret =3D hbg_txrx_init(priv); + if (ret) + return ret; =20 hbg_all_irq_enable(priv, true); hbg_hw_mac_enable(priv, HBG_STATUS_ENABLE); @@ -33,6 +41,26 @@ static int hbg_net_open(struct net_device *netdev) return 0; } =20 +/* This function only can be called after hbg_txrx_uninit() */ +static int hbg_hw_txrx_clear(struct hbg_priv *priv) +{ + int ret; + + /* After ring buffers have been released, + * do a reset to release hw fifo rx ring buffer + */ + ret =3D hbg_hw_event_notify(priv, HBG_HW_EVENT_RESET); + if (ret) + return ret; + + /* After reset, regs need to be reconfigured */ + hbg_hw_init(priv); + hbg_hw_set_uc_addr(priv, ether_addr_to_u64(priv->netdev->dev_addr)); + hbg_change_mtu(priv, priv->netdev->mtu); + + return 0; +} + static int hbg_net_stop(struct net_device *netdev) { struct hbg_priv *priv =3D netdev_priv(netdev); @@ -41,8 +69,8 @@ static int hbg_net_stop(struct net_device *netdev) netif_stop_queue(netdev); hbg_hw_mac_enable(priv, HBG_STATUS_DISABLE); hbg_all_irq_enable(priv, false); - - return 0; + hbg_txrx_uninit(priv); + return hbg_hw_txrx_clear(priv); } =20 static int hbg_net_set_mac_address(struct net_device *netdev, void *addr) @@ -92,13 +120,34 @@ static void hbg_net_get_stats64(struct net_device *net= dev, dev_fetch_sw_netstats(stats, netdev->tstats); } =20 +static void hbg_net_tx_timeout(struct net_device *netdev, unsigned int txq= ueue) +{ + struct hbg_priv *priv =3D netdev_priv(netdev); + struct hbg_ring *ring =3D &priv->tx_ring; + char *buf =3D ring->tout_log_buf; + u32 pos =3D 0; + + pos +=3D scnprintf(buf + pos, HBG_TX_TIMEOUT_BUF_LEN - pos, + "ring used num: %u, fifo used num: %u\n", + hbg_get_queue_used_num(ring), + hbg_hw_get_fifo_used_num(priv, HBG_DIR_TX)); + pos +=3D scnprintf(buf + pos, HBG_TX_TIMEOUT_BUF_LEN - pos, + "ntc: %u, ntu: %u, irq enabled: %u\n", + ring->ntc, ring->ntu, + hbg_hw_irq_is_enabled(priv, HBG_INT_MSK_TX_B)); + + netdev_info(netdev, "%s", buf); +} + static const struct net_device_ops hbg_netdev_ops =3D { .ndo_open =3D hbg_net_open, .ndo_stop =3D hbg_net_stop, + .ndo_start_xmit =3D hbg_net_start_xmit, .ndo_validate_addr =3D eth_validate_addr, .ndo_set_mac_address =3D hbg_net_set_mac_address, .ndo_change_mtu =3D hbg_net_change_mtu, .ndo_get_stats64 =3D hbg_net_get_stats64, + .ndo_tx_timeout =3D hbg_net_tx_timeout, }; =20 static int hbg_init(struct hbg_priv *priv) @@ -181,6 +230,7 @@ static int hbg_probe(struct pci_dev *pdev, const struct= pci_device_id *ent) if (ret) return ret; =20 + netdev->watchdog_timeo =3D 5 * HZ; netdev->max_mtu =3D priv->dev_specs.max_mtu; netdev->min_mtu =3D priv->dev_specs.min_mtu; hbg_change_mtu(priv, HBG_DEFAULT_MTU_SIZE); diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h b/drivers/net= /ethernet/hisilicon/hibmcge/hbg_reg.h index 63bb1bead8c0..0abfcd84e56b 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h @@ -80,6 +80,12 @@ #define HBG_REG_CF_INTRPT_CLR_ADDR (HBG_REG_SGMII_BASE + 0x0438) #define HBG_REG_MAX_FRAME_LEN_ADDR (HBG_REG_SGMII_BASE + 0x0444) #define HBG_REG_MAX_FRAME_LEN_M GENMASK(15, 0) +#define HBG_REG_CF_CFF_DATA_NUM_ADDR (HBG_REG_SGMII_BASE + 0x045C) +#define HBG_REG_CF_CFF_DATA_NUM_ADDR_TX_M GENMASK(8, 0) +#define HBG_REG_TX_CFF_ADDR_0_ADDR (HBG_REG_SGMII_BASE + 0x0488) +#define HBG_REG_TX_CFF_ADDR_1_ADDR (HBG_REG_SGMII_BASE + 0x048C) +#define HBG_REG_TX_CFF_ADDR_2_ADDR (HBG_REG_SGMII_BASE + 0x0490) +#define HBG_REG_TX_CFF_ADDR_3_ADDR (HBG_REG_SGMII_BASE + 0x0494) #define HBG_REG_RX_BUF_SIZE_ADDR (HBG_REG_SGMII_BASE + 0x04E4) #define HBG_REG_RX_BUF_SIZE_M GENMASK(15, 0) #define HBG_REG_BUS_CTRL_ADDR (HBG_REG_SGMII_BASE + 0x04E8) @@ -108,4 +114,17 @@ enum hbg_port_mode { HBG_PORT_MODE_SGMII_1000M =3D 0x8, }; =20 +struct hbg_tx_desc { + u32 word0; + u32 word1; + u32 word2; /* pkt_addr */ + u32 word3; /* clear_addr */ +}; + +#define HBG_TX_DESC_W0_IP_OFF_M GENMASK(30, 26) +#define HBG_TX_DESC_W0_l3_CS_B BIT(2) +#define HBG_TX_DESC_W0_WB_B BIT(1) +#define HBG_TX_DESC_W0_l4_CS_B BIT(0) +#define HBG_TX_DESC_W1_SEND_LEN_M GENMASK(19, 4) + #endif diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_txrx.c b/drivers/ne= t/ethernet/hisilicon/hibmcge/hbg_txrx.c new file mode 100644 index 000000000000..8ef13ce06ca0 --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_txrx.c @@ -0,0 +1,261 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2024 Hisilicon Limited. + +#include +#include "hbg_common.h" +#include "hbg_irq.h" +#include "hbg_reg.h" +#include "hbg_txrx.h" + +#define netdev_get_tx_ring(netdev) (&(((struct hbg_priv *)netdev_priv(net= dev))->tx_ring)) + +#define buffer_to_dma_dir(buffer) (((buffer)->dir =3D=3D HBG_DIR_RX) ? \ + DMA_FROM_DEVICE : DMA_TO_DEVICE) + +#define hbg_queue_used_num(head, tail, ring) ({ \ + typeof(ring) _ring =3D (ring); \ + ((tail) + _ring->len - (head)) % _ring->len; }) +#define hbg_queue_left_num(head, tail, ring) \ + ((ring)->len - hbg_queue_used_num((head), (tail), (ring)) - 1) +#define hbg_queue_is_empty(head, tail, ring) \ + (hbg_queue_used_num((head), (tail), (ring)) =3D=3D 0) +#define hbg_queue_next_prt(p, ring) (((p) + 1) % (ring)->len) + +#define HBG_TX_STOP_THRS 2 +#define HBG_TX_START_THRS (2 * HBG_TX_STOP_THRS) + +static int hbg_dma_map(struct hbg_buffer *buffer) +{ + struct hbg_priv *priv =3D buffer->priv; + + buffer->skb_dma =3D dma_map_single(&priv->pdev->dev, + buffer->skb->data, buffer->skb_len, + buffer_to_dma_dir(buffer)); + if (unlikely(dma_mapping_error(&priv->pdev->dev, buffer->skb_dma))) + return -ENOMEM; + + return 0; +} + +static void hbg_dma_unmap(struct hbg_buffer *buffer) +{ + struct hbg_priv *priv =3D buffer->priv; + + if (unlikely(!buffer->skb_dma)) + return; + + dma_unmap_single(&priv->pdev->dev, buffer->skb_dma, buffer->skb_len, + buffer_to_dma_dir(buffer)); + buffer->skb_dma =3D 0; +} + +static void hbg_init_tx_desc(struct hbg_buffer *buffer, + struct hbg_tx_desc *tx_desc) +{ + u32 ip_offset =3D buffer->skb->network_header - buffer->skb->mac_header; + u32 word0 =3D 0; + + word0 |=3D FIELD_PREP(HBG_TX_DESC_W0_WB_B, HBG_STATUS_ENABLE); + word0 |=3D FIELD_PREP(HBG_TX_DESC_W0_IP_OFF_M, ip_offset); + if (likely(buffer->skb->ip_summed =3D=3D CHECKSUM_PARTIAL)) { + word0 |=3D FIELD_PREP(HBG_TX_DESC_W0_l3_CS_B, HBG_STATUS_ENABLE); + word0 |=3D FIELD_PREP(HBG_TX_DESC_W0_l4_CS_B, HBG_STATUS_ENABLE); + } + + tx_desc->word0 =3D word0; + tx_desc->word1 =3D FIELD_PREP(HBG_TX_DESC_W1_SEND_LEN_M, buffer->skb->len= ); + tx_desc->word2 =3D buffer->skb_dma; + tx_desc->word3 =3D buffer->state_dma; +} + +netdev_tx_t hbg_net_start_xmit(struct sk_buff *skb, struct net_device *net= dev) +{ + struct hbg_ring *ring =3D netdev_get_tx_ring(netdev); + struct hbg_priv *priv =3D netdev_priv(netdev); + /* This smp_load_acquire() pairs with smp_store_release() in + * hbg_tx_buffer_recycle() called in tx interrupt handle process. + */ + u32 ntc =3D smp_load_acquire(&ring->ntc); + struct hbg_buffer *buffer; + struct hbg_tx_desc tx_desc; + u32 ntu =3D ring->ntu; + + if (unlikely(!skb->len || + skb->len > hbg_spec_max_frame_len(priv, HBG_DIR_TX))) { + dev_kfree_skb_any(skb); + netdev->stats.tx_errors++; + return NETDEV_TX_OK; + } + + if (!netif_subqueue_maybe_stop(netdev, 0, + hbg_queue_left_num(ntc, ntu, ring), + HBG_TX_STOP_THRS, HBG_TX_START_THRS)) + return NETDEV_TX_BUSY; + + buffer =3D &ring->queue[ntu]; + buffer->skb =3D skb; + buffer->skb_len =3D skb->len; + if (unlikely(hbg_dma_map(buffer))) { + dev_kfree_skb_any(skb); + return NETDEV_TX_OK; + } + + buffer->state =3D HBG_TX_STATE_START; + hbg_init_tx_desc(buffer, &tx_desc); + hbg_hw_set_tx_desc(priv, &tx_desc); + + /* This smp_store_release() pairs with smp_load_acquire() in + * hbg_tx_buffer_recycle() called in tx interrupt handle process. + */ + smp_store_release(&ring->ntu, hbg_queue_next_prt(ntu, ring)); + dev_sw_netstats_tx_add(netdev, 1, skb->len); + return NETDEV_TX_OK; +} + +static void hbg_buffer_free_skb(struct hbg_buffer *buffer) +{ + if (unlikely(!buffer->skb)) + return; + + dev_kfree_skb_any(buffer->skb); + buffer->skb =3D NULL; +} + +static void hbg_buffer_free(struct hbg_buffer *buffer) +{ + hbg_dma_unmap(buffer); + hbg_buffer_free_skb(buffer); +} + +static int hbg_napi_tx_recycle(struct napi_struct *napi, int budget) +{ + struct hbg_ring *ring =3D container_of(napi, struct hbg_ring, napi); + /* This smp_load_acquire() pairs with smp_store_release() in + * hbg_start_xmit() called in xmit process. + */ + u32 ntu =3D smp_load_acquire(&ring->ntu); + struct hbg_priv *priv =3D ring->priv; + struct hbg_buffer *buffer; + u32 ntc =3D ring->ntc; + int packet_done =3D 0; + + while (packet_done < budget) { + if (unlikely(hbg_queue_is_empty(ntc, ntu, ring))) + break; + + /* make sure HW write desc complete */ + dma_rmb(); + + buffer =3D &ring->queue[ntc]; + if (buffer->state !=3D HBG_TX_STATE_COMPLETE) + break; + + hbg_buffer_free(buffer); + ntc =3D hbg_queue_next_prt(ntc, ring); + packet_done++; + } + + /* This smp_store_release() pairs with smp_load_acquire() in + * hbg_start_xmit() called in xmit process. + */ + smp_store_release(&ring->ntc, ntc); + netif_wake_queue(priv->netdev); + + if (likely(napi_complete_done(napi, packet_done))) + hbg_hw_irq_enable(priv, HBG_INT_MSK_TX_B, true); + + return packet_done; +} + +static void hbg_ring_uninit(struct hbg_ring *ring) +{ + struct hbg_buffer *buffer; + u32 i; + + if (!ring->queue) + return; + + napi_disable(&ring->napi); + netif_napi_del(&ring->napi); + + for (i =3D 0; i < ring->len; i++) { + buffer =3D &ring->queue[i]; + hbg_buffer_free(buffer); + buffer->ring =3D NULL; + buffer->priv =3D NULL; + } + + dma_free_coherent(&ring->priv->pdev->dev, + ring->len * sizeof(*ring->queue), + ring->queue, ring->queue_dma); + ring->queue =3D NULL; + ring->queue_dma =3D 0; + ring->len =3D 0; + ring->priv =3D NULL; +} + +static int hbg_ring_init(struct hbg_priv *priv, struct hbg_ring *ring, + int (*napi_poll)(struct napi_struct *, int), + enum hbg_dir dir) +{ + struct hbg_buffer *buffer; + u32 i, len; + + len =3D hbg_get_spec_fifo_max_num(priv, dir) + 1; + ring->queue =3D dma_alloc_coherent(&priv->pdev->dev, + len * sizeof(*ring->queue), + &ring->queue_dma, GFP_KERNEL); + if (!ring->queue) + return -ENOMEM; + + for (i =3D 0; i < len; i++) { + buffer =3D &ring->queue[i]; + buffer->skb_len =3D 0; + buffer->dir =3D dir; + buffer->ring =3D ring; + buffer->priv =3D priv; + buffer->state_dma =3D ring->queue_dma + (i * sizeof(*buffer)); + } + + ring->dir =3D dir; + ring->priv =3D priv; + ring->ntc =3D 0; + ring->ntu =3D 0; + ring->len =3D len; + + netif_napi_add_tx(priv->netdev, &ring->napi, napi_poll); + napi_enable(&ring->napi); + return 0; +} + +static int hbg_tx_ring_init(struct hbg_priv *priv) +{ + struct hbg_ring *tx_ring =3D &priv->tx_ring; + + if (!tx_ring->tout_log_buf) + tx_ring->tout_log_buf =3D devm_kzalloc(&priv->pdev->dev, + HBG_TX_TIMEOUT_BUF_LEN, + GFP_KERNEL); + + if (!tx_ring->tout_log_buf) + return -ENOMEM; + + return hbg_ring_init(priv, tx_ring, hbg_napi_tx_recycle, HBG_DIR_TX); +} + +int hbg_txrx_init(struct hbg_priv *priv) +{ + int ret; + + ret =3D hbg_tx_ring_init(priv); + if (ret) + dev_err(&priv->pdev->dev, + "failed to init tx ring, ret =3D %d\n", ret); + + return ret; +} + +void hbg_txrx_uninit(struct hbg_priv *priv) +{ + hbg_ring_uninit(&priv->tx_ring); +} diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_txrx.h b/drivers/ne= t/ethernet/hisilicon/hibmcge/hbg_txrx.h new file mode 100644 index 000000000000..73aca4b850a8 --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_txrx.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (c) 2024 Hisilicon Limited. */ + +#ifndef __HBG_TXRX_H +#define __HBG_TXRX_H + +#include +#include "hbg_hw.h" + +static inline u32 hbg_spec_max_frame_len(struct hbg_priv *priv, enum hbg_d= ir dir) +{ + return (dir =3D=3D HBG_DIR_TX) ? priv->dev_specs.max_frame_len : + priv->dev_specs.rx_buf_size; +} + +static inline u32 hbg_get_spec_fifo_max_num(struct hbg_priv *priv, enum hb= g_dir dir) +{ + return (dir =3D=3D HBG_DIR_TX) ? priv->dev_specs.tx_fifo_num : + priv->dev_specs.rx_fifo_num; +} + +static inline bool hbg_fifo_is_full(struct hbg_priv *priv, enum hbg_dir di= r) +{ + return hbg_hw_get_fifo_used_num(priv, dir) >=3D + hbg_get_spec_fifo_max_num(priv, dir); +} + +static inline u32 hbg_get_queue_used_num(struct hbg_ring *ring) +{ + return (ring->ntu + ring->len - ring->ntc) % ring->len; +} + +netdev_tx_t hbg_net_start_xmit(struct sk_buff *skb, struct net_device *net= dev); +int hbg_txrx_init(struct hbg_priv *priv); +void hbg_txrx_uninit(struct hbg_priv *priv); + +#endif --=20 2.33.0 From nobody Sat Nov 30 10:39:28 2024 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61C2E186608; Tue, 10 Sep 2024 08:06:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725955578; cv=none; b=tJGc4S7z0BgEHOb8wbbo6YHAXJUCC174vsAhGnoRIOWpeXZo9ElawUXlGNBIyzNVBdmFiVix8tK7kmek0mp8wSh+b/9T5JmCGn5DnvRuHnROyM/ZoE9l5IN83hwLoDMh2eVl90xolnaD0H+zuI5pz4FPeYyiSkHw6lWgK8TPYds= ARC-Message-Signature: i=1; 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Tue, 10 Sep 2024 16:06:13 +0800 (CST) Received: from localhost.localdomain (10.90.30.45) by kwepemm000007.china.huawei.com (7.193.23.189) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 10 Sep 2024 16:06:12 +0800 From: Jijie Shao To: , , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH V9 net-next 07/11] net: hibmcge: Implement rx_poll function to receive packets Date: Tue, 10 Sep 2024 15:59:38 +0800 Message-ID: <20240910075942.1270054-8-shaojijie@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20240910075942.1270054-1-shaojijie@huawei.com> References: <20240910075942.1270054-1-shaojijie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemm000007.china.huawei.com (7.193.23.189) Content-Type: text/plain; charset="utf-8" Implement rx_poll function to read the rx descriptor after receiving the rx interrupt. Adjust the skb based on the descriptor to complete the reception of the packet. Signed-off-by: Jijie Shao --- ChangeLog: v8 -> v9: - Remove hbg_nic_is_open() judgment from hbg_napi_rx_poll() v8: https://lore.kernel.org/all/20240909023141.3234567-1-shaojijie@huawei= .com/ v6 -> v7: - Use dev_sw_netstats_rx_add() instead of dev->stats, suggested by Paolo. v6: https://lore.kernel.org/all/20240830121604.2250904-8-shaojijie@huawei= .com/ --- .../ethernet/hisilicon/hibmcge/hbg_common.h | 5 + .../net/ethernet/hisilicon/hibmcge/hbg_hw.c | 10 ++ .../net/ethernet/hisilicon/hibmcge/hbg_hw.h | 1 + .../net/ethernet/hisilicon/hibmcge/hbg_irq.c | 8 +- .../net/ethernet/hisilicon/hibmcge/hbg_reg.h | 13 ++ .../net/ethernet/hisilicon/hibmcge/hbg_txrx.c | 163 +++++++++++++++++- 6 files changed, 197 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h b/drivers/= net/ethernet/hisilicon/hibmcge/hbg_common.h index 31fb03f75d31..f59c817ab3c8 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h @@ -16,6 +16,10 @@ #define HBG_VECTOR_NUM 4 #define HBG_PCU_CACHE_LINE_SIZE 32 #define HBG_TX_TIMEOUT_BUF_LEN 1024 +#define HBG_RX_DESCR 0x01 + +#define HBG_PACKET_HEAD_SIZE ((HBG_RX_SKIP1 + HBG_RX_SKIP2 + HBG_RX_DESCR)= * \ + HBG_PCU_CACHE_LINE_SIZE) =20 enum hbg_dir { HBG_DIR_TX =3D 1 << 0, @@ -124,6 +128,7 @@ struct hbg_priv { struct hbg_mac mac; struct hbg_vector vectors; struct hbg_ring tx_ring; + struct hbg_ring rx_ring; }; =20 #endif diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c b/drivers/net/= ethernet/hisilicon/hibmcge/hbg_hw.c index 61e02811c165..c4df7a56004e 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c @@ -73,6 +73,7 @@ static int hbg_hw_dev_specs_init(struct hbg_priv *priv) return -EADDRNOTAVAIL; =20 dev_specs->max_frame_len =3D HBG_PCU_CACHE_LINE_SIZE + dev_specs->max_mtu; + dev_specs->rx_buf_size =3D HBG_PACKET_HEAD_SIZE + dev_specs->max_frame_le= n; return 0; } =20 @@ -175,6 +176,10 @@ u32 hbg_hw_get_fifo_used_num(struct hbg_priv *priv, en= um hbg_dir dir) return hbg_reg_read_field(priv, HBG_REG_CF_CFF_DATA_NUM_ADDR, HBG_REG_CF_CFF_DATA_NUM_ADDR_TX_M); =20 + if (dir & HBG_DIR_RX) + return hbg_reg_read_field(priv, HBG_REG_CF_CFF_DATA_NUM_ADDR, + HBG_REG_CF_CFF_DATA_NUM_ADDR_RX_M); + return 0; } =20 @@ -186,6 +191,11 @@ void hbg_hw_set_tx_desc(struct hbg_priv *priv, struct = hbg_tx_desc *tx_desc) hbg_reg_write(priv, HBG_REG_TX_CFF_ADDR_3_ADDR, tx_desc->word3); } =20 +void hbg_hw_fill_buffer(struct hbg_priv *priv, u32 buffer_dma_addr) +{ + hbg_reg_write(priv, HBG_REG_RX_CFF_ADDR_ADDR, buffer_dma_addr); +} + void hbg_hw_adjust_link(struct hbg_priv *priv, u32 speed, u32 duplex) { hbg_reg_write_field(priv, HBG_REG_PORT_MODE_ADDR, diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h b/drivers/net/= ethernet/hisilicon/hibmcge/hbg_hw.h index 508e41cce41e..14fb39241c93 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h @@ -54,5 +54,6 @@ void hbg_hw_mac_enable(struct hbg_priv *priv, u32 enable); void hbg_hw_set_uc_addr(struct hbg_priv *priv, u64 mac_addr); u32 hbg_hw_get_fifo_used_num(struct hbg_priv *priv, enum hbg_dir dir); void hbg_hw_set_tx_desc(struct hbg_priv *priv, struct hbg_tx_desc *tx_desc= ); +void hbg_hw_fill_buffer(struct hbg_priv *priv, u32 buffer_dma_addr); =20 #endif diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_irq.c b/drivers/net= /ethernet/hisilicon/hibmcge/hbg_irq.c index bf5bfedd8a8c..90857711fafe 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_irq.c +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_irq.c @@ -19,13 +19,19 @@ static void hbg_irq_handle_tx(struct hbg_priv *priv, napi_schedule(&priv->tx_ring.napi); } =20 +static void hbg_irq_handle_rx(struct hbg_priv *priv, + struct hbg_irq_info *irq_info) +{ + napi_schedule(&priv->rx_ring.napi); +} + #define HBG_TXRX_IRQ_I(name, handle) \ {#name, HBG_INT_MSK_##name##_B, false, false, 0, handle} #define HBG_ERR_IRQ_I(name, need_print) \ {#name, HBG_INT_MSK_##name##_B, true, need_print, 0, hbg_irq_handle_err} =20 static struct hbg_irq_info hbg_irqs[] =3D { - HBG_TXRX_IRQ_I(RX, NULL), + HBG_TXRX_IRQ_I(RX, hbg_irq_handle_rx), HBG_TXRX_IRQ_I(TX, hbg_irq_handle_tx), HBG_ERR_IRQ_I(MAC_MII_FIFO_ERR, true), HBG_ERR_IRQ_I(MAC_PCS_RX_FIFO_ERR, true), diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h b/drivers/net= /ethernet/hisilicon/hibmcge/hbg_reg.h index 0abfcd84e56b..410081d01acf 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h @@ -82,10 +82,12 @@ #define HBG_REG_MAX_FRAME_LEN_M GENMASK(15, 0) #define HBG_REG_CF_CFF_DATA_NUM_ADDR (HBG_REG_SGMII_BASE + 0x045C) #define HBG_REG_CF_CFF_DATA_NUM_ADDR_TX_M GENMASK(8, 0) +#define HBG_REG_CF_CFF_DATA_NUM_ADDR_RX_M GENMASK(24, 16) #define HBG_REG_TX_CFF_ADDR_0_ADDR (HBG_REG_SGMII_BASE + 0x0488) #define HBG_REG_TX_CFF_ADDR_1_ADDR (HBG_REG_SGMII_BASE + 0x048C) #define HBG_REG_TX_CFF_ADDR_2_ADDR (HBG_REG_SGMII_BASE + 0x0490) #define HBG_REG_TX_CFF_ADDR_3_ADDR (HBG_REG_SGMII_BASE + 0x0494) +#define HBG_REG_RX_CFF_ADDR_ADDR (HBG_REG_SGMII_BASE + 0x04A0) #define HBG_REG_RX_BUF_SIZE_ADDR (HBG_REG_SGMII_BASE + 0x04E4) #define HBG_REG_RX_BUF_SIZE_M GENMASK(15, 0) #define HBG_REG_BUS_CTRL_ADDR (HBG_REG_SGMII_BASE + 0x04E8) @@ -127,4 +129,15 @@ struct hbg_tx_desc { #define HBG_TX_DESC_W0_l4_CS_B BIT(0) #define HBG_TX_DESC_W1_SEND_LEN_M GENMASK(19, 4) =20 +struct hbg_rx_desc { + u32 word0; + u32 word1; /* tag */ + u32 word2; + u32 word3; + u32 word4; + u32 word5; +}; + +#define HBG_RX_DESC_W2_PKT_LEN_M GENMASK(31, 16) + #endif diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_txrx.c b/drivers/ne= t/ethernet/hisilicon/hibmcge/hbg_txrx.c index 8ef13ce06ca0..c6fbd55a115b 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_txrx.c +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_txrx.c @@ -19,7 +19,12 @@ ((ring)->len - hbg_queue_used_num((head), (tail), (ring)) - 1) #define hbg_queue_is_empty(head, tail, ring) \ (hbg_queue_used_num((head), (tail), (ring)) =3D=3D 0) +#define hbg_queue_is_full(head, tail, ring) \ + (hbg_queue_left_num((head), (tail), (ring)) =3D=3D 0) #define hbg_queue_next_prt(p, ring) (((p) + 1) % (ring)->len) +#define hbg_queue_move_next(p, ring) ({ \ + typeof(ring) _ring =3D (ring); \ + _ring->p =3D hbg_queue_next_prt(_ring->p, _ring); }) =20 #define HBG_TX_STOP_THRS 2 #define HBG_TX_START_THRS (2 * HBG_TX_STOP_THRS) @@ -121,6 +126,20 @@ static void hbg_buffer_free_skb(struct hbg_buffer *buf= fer) buffer->skb =3D NULL; } =20 +static int hbg_buffer_alloc_skb(struct hbg_buffer *buffer) +{ + u32 len =3D hbg_spec_max_frame_len(buffer->priv, buffer->dir); + struct hbg_priv *priv =3D buffer->priv; + + buffer->skb =3D netdev_alloc_skb(priv->netdev, len); + if (unlikely(!buffer->skb)) + return -ENOMEM; + + buffer->skb_len =3D len; + memset(buffer->skb->data, 0, HBG_PACKET_HEAD_SIZE); + return 0; +} + static void hbg_buffer_free(struct hbg_buffer *buffer) { hbg_dma_unmap(buffer); @@ -167,6 +186,114 @@ static int hbg_napi_tx_recycle(struct napi_struct *na= pi, int budget) return packet_done; } =20 +static int hbg_rx_fill_one_buffer(struct hbg_priv *priv) +{ + struct hbg_ring *ring =3D &priv->rx_ring; + struct hbg_buffer *buffer; + int ret; + + if (hbg_queue_is_full(ring->ntc, ring->ntu, ring)) + return 0; + + buffer =3D &ring->queue[ring->ntu]; + ret =3D hbg_buffer_alloc_skb(buffer); + if (unlikely(ret)) + return ret; + + ret =3D hbg_dma_map(buffer); + if (unlikely(ret)) { + hbg_buffer_free_skb(buffer); + return ret; + } + + hbg_hw_fill_buffer(priv, buffer->skb_dma); + hbg_queue_move_next(ntu, ring); + return 0; +} + +static int hbg_rx_fill_buffers(struct hbg_priv *priv) +{ + struct hbg_ring *ring =3D &priv->rx_ring; + u32 fifo_left; + int ret; + + if (hbg_fifo_is_full(priv, ring->dir)) + return 0; + + fifo_left =3D hbg_get_spec_fifo_max_num(priv, ring->dir) - + hbg_hw_get_fifo_used_num(priv, ring->dir); + while (fifo_left) { + ret =3D hbg_rx_fill_one_buffer(priv); + if (ret) + return ret; + + fifo_left--; + } + + return 0; +} + +static bool hbg_sync_data_from_hw(struct hbg_priv *priv, + struct hbg_buffer *buffer) +{ + struct hbg_rx_desc *rx_desc; + + /* make sure HW write desc complete */ + dma_rmb(); + + dma_sync_single_for_cpu(&priv->pdev->dev, buffer->skb_dma, + buffer->skb_len, DMA_FROM_DEVICE); + + rx_desc =3D (struct hbg_rx_desc *)buffer->skb->data; + return FIELD_GET(HBG_RX_DESC_W2_PKT_LEN_M, rx_desc->word2) !=3D 0; +} + +static int hbg_napi_rx_poll(struct napi_struct *napi, int budget) +{ + struct hbg_ring *ring =3D container_of(napi, struct hbg_ring, napi); + struct hbg_priv *priv =3D ring->priv; + struct hbg_rx_desc *rx_desc; + struct hbg_buffer *buffer; + u32 packet_done =3D 0; + u32 pkt_len; + + while (packet_done < budget) { + if (unlikely(hbg_queue_is_empty(ring->ntc, ring->ntu, ring))) + break; + + buffer =3D &ring->queue[ring->ntc]; + if (unlikely(!buffer->skb)) + goto next_buffer; + + if (unlikely(!hbg_sync_data_from_hw(priv, buffer))) + break; + + hbg_dma_unmap(buffer); + + skb_reserve(buffer->skb, HBG_PACKET_HEAD_SIZE + NET_IP_ALIGN); + + rx_desc =3D (struct hbg_rx_desc *)buffer->skb->data; + pkt_len =3D FIELD_GET(HBG_RX_DESC_W2_PKT_LEN_M, rx_desc->word2); + skb_put(buffer->skb, pkt_len); + buffer->skb->protocol =3D eth_type_trans(buffer->skb, priv->netdev); + + dev_sw_netstats_rx_add(priv->netdev, pkt_len); + netif_receive_skb(buffer->skb); + buffer->skb =3D NULL; + hbg_rx_fill_one_buffer(priv); + +next_buffer: + hbg_queue_move_next(ntc, ring); + packet_done++; + } + + hbg_rx_fill_buffers(priv); + if (likely(napi_complete_done(napi, packet_done))) + hbg_hw_irq_enable(priv, HBG_INT_MSK_RX_B, true); + + return packet_done; +} + static void hbg_ring_uninit(struct hbg_ring *ring) { struct hbg_buffer *buffer; @@ -223,7 +350,11 @@ static int hbg_ring_init(struct hbg_priv *priv, struct= hbg_ring *ring, ring->ntu =3D 0; ring->len =3D len; =20 - netif_napi_add_tx(priv->netdev, &ring->napi, napi_poll); + if (dir =3D=3D HBG_DIR_TX) + netif_napi_add_tx(priv->netdev, &ring->napi, napi_poll); + else + netif_napi_add(priv->netdev, &ring->napi, napi_poll); + napi_enable(&ring->napi); return 0; } @@ -243,19 +374,47 @@ static int hbg_tx_ring_init(struct hbg_priv *priv) return hbg_ring_init(priv, tx_ring, hbg_napi_tx_recycle, HBG_DIR_TX); } =20 +static int hbg_rx_ring_init(struct hbg_priv *priv) +{ + return hbg_ring_init(priv, &priv->rx_ring, hbg_napi_rx_poll, HBG_DIR_RX); +} + int hbg_txrx_init(struct hbg_priv *priv) { int ret; =20 ret =3D hbg_tx_ring_init(priv); - if (ret) + if (ret) { dev_err(&priv->pdev->dev, "failed to init tx ring, ret =3D %d\n", ret); + return ret; + } =20 + ret =3D hbg_rx_ring_init(priv); + if (ret) { + dev_err(&priv->pdev->dev, + "failed to init rx ring, ret =3D %d\n", ret); + goto err_uninit_tx; + } + + ret =3D hbg_rx_fill_buffers(priv); + if (ret) { + dev_err(&priv->pdev->dev, + "failed to fill rx buffers, ret =3D %d\n", ret); + goto err_uninit_rx; + } + + return 0; + +err_uninit_rx: + hbg_ring_uninit(&priv->rx_ring); +err_uninit_tx: + hbg_ring_uninit(&priv->tx_ring); return ret; } =20 void hbg_txrx_uninit(struct hbg_priv *priv) { hbg_ring_uninit(&priv->tx_ring); + hbg_ring_uninit(&priv->rx_ring); } --=20 2.33.0 From nobody Sat Nov 30 10:39:28 2024 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 568B71865E1; Tue, 10 Sep 2024 08:06:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Tue, 10 Sep 2024 16:05:09 +0800 (CST) Received: from kwepemm000007.china.huawei.com (unknown [7.193.23.189]) by mail.maildlp.com (Postfix) with ESMTPS id 8D042180113; Tue, 10 Sep 2024 16:06:14 +0800 (CST) Received: from localhost.localdomain (10.90.30.45) by kwepemm000007.china.huawei.com (7.193.23.189) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 10 Sep 2024 16:06:13 +0800 From: Jijie Shao To: , , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH V9 net-next 08/11] net: hibmcge: Implement some ethtool_ops functions Date: Tue, 10 Sep 2024 15:59:39 +0800 Message-ID: <20240910075942.1270054-9-shaojijie@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20240910075942.1270054-1-shaojijie@huawei.com> References: <20240910075942.1270054-1-shaojijie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemm000007.china.huawei.com (7.193.23.189) Content-Type: text/plain; charset="utf-8" Implement the .get_drvinfo .get_link .get_link_ksettings to get the basic information and working status of the driver. Implement the .set_link_ksettings to modify the rate, duplex, and auto-negotiation status. Signed-off-by: Jijie Shao Reviewed-by: Andrew Lunn Reviewed-by: Kalesh AP --- ChangeLog: RFC v1 -> RFC v2: - Use ethtool_op_get_link(), phy_ethtool_get_link_ksettings(), and phy_ethtool_set_link_ksettings() to simplify the code, suggested by= Andrew. - Delete workqueue for this patch set, suggested by Jonathan. RFC v1: https://lore.kernel.org/all/20240731094245.1967834-1-shaojijie@hu= awei.com/ --- .../ethernet/hisilicon/hibmcge/hbg_ethtool.c | 17 +++++++++++++++++ .../ethernet/hisilicon/hibmcge/hbg_ethtool.h | 11 +++++++++++ .../net/ethernet/hisilicon/hibmcge/hbg_main.c | 2 ++ 3 files changed, 30 insertions(+) create mode 100644 drivers/net/ethernet/hisilicon/hibmcge/hbg_ethtool.c create mode 100644 drivers/net/ethernet/hisilicon/hibmcge/hbg_ethtool.h diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_ethtool.c b/drivers= /net/ethernet/hisilicon/hibmcge/hbg_ethtool.c new file mode 100644 index 000000000000..c3370114aef3 --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_ethtool.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2024 Hisilicon Limited. + +#include +#include +#include "hbg_ethtool.h" + +static const struct ethtool_ops hbg_ethtool_ops =3D { + .get_link =3D ethtool_op_get_link, + .get_link_ksettings =3D phy_ethtool_get_link_ksettings, + .set_link_ksettings =3D phy_ethtool_set_link_ksettings, +}; + +void hbg_ethtool_set_ops(struct net_device *netdev) +{ + netdev->ethtool_ops =3D &hbg_ethtool_ops; +} diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_ethtool.h b/drivers= /net/ethernet/hisilicon/hibmcge/hbg_ethtool.h new file mode 100644 index 000000000000..628707ec2686 --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_ethtool.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (c) 2024 Hisilicon Limited. */ + +#ifndef __HBG_ETHTOOL_H +#define __HBG_ETHTOOL_H + +#include + +void hbg_ethtool_set_ops(struct net_device *netdev); + +#endif diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c b/drivers/ne= t/ethernet/hisilicon/hibmcge/hbg_main.c index a8d0e951633b..b06524c336e2 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c @@ -6,6 +6,7 @@ #include #include #include "hbg_common.h" +#include "hbg_ethtool.h" #include "hbg_hw.h" #include "hbg_irq.h" #include "hbg_mdio.h" @@ -235,6 +236,7 @@ static int hbg_probe(struct pci_dev *pdev, const struct= pci_device_id *ent) netdev->min_mtu =3D priv->dev_specs.min_mtu; hbg_change_mtu(priv, HBG_DEFAULT_MTU_SIZE); hbg_net_set_mac_address(priv->netdev, &priv->dev_specs.mac_addr); + hbg_ethtool_set_ops(netdev); ret =3D devm_register_netdev(dev, netdev); if (ret) return dev_err_probe(dev, ret, "failed to register netdev\n"); --=20 2.33.0 From nobody Sat Nov 30 10:39:28 2024 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D69D51885A9; Tue, 10 Sep 2024 08:06:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725955581; cv=none; b=Ohu9BGdCAU8cFlUZyh95QCXXX2+aAkExX+X579hMJ7C1n/KPWLCgs5wUtcHahUKqs3GeLRIZeYE9rvOfPZWHESz4Bn7fqA4ty1CP+PSFAbiOUgDG8mohDRK+J5AL0y5knoIev2XlaoZ4xsAPN4w83mlNIjEtz5Fs7bEVU0f7TD8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Tue, 10 Sep 2024 16:06:15 +0800 (CST) Received: from localhost.localdomain (10.90.30.45) by kwepemm000007.china.huawei.com (7.193.23.189) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 10 Sep 2024 16:06:14 +0800 From: Jijie Shao To: , , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH V9 net-next 09/11] net: hibmcge: Add a Makefile and update Kconfig for hibmcge Date: Tue, 10 Sep 2024 15:59:40 +0800 Message-ID: <20240910075942.1270054-10-shaojijie@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20240910075942.1270054-1-shaojijie@huawei.com> References: <20240910075942.1270054-1-shaojijie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemm000007.china.huawei.com (7.193.23.189) Content-Type: text/plain; charset="utf-8" Add a Makefile and update Kconfig to build hibmcge driver. Signed-off-by: Jijie Shao --- ChangeLog: v2 -> v3: - Add "select PHYLIB" in Kconfig, reported by Jakub. v2: https://lore.kernel.org/all/20240820140154.137876-1-shaojijie@huawei.= com/ v1 -> v2: - fix build errors reported by kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202408192219.zrGff7n1-lkp= @intel.com/ Closes: https://lore.kernel.org/oe-kbuild-all/202408200026.q20EuSHC-lkp= @intel.com/ v1: https://lore.kernel.org/all/20240819071229.2489506-1-shaojijie@huawei= .com/ RFC v1 -> RFC v2: - Support to compile this driver on all arch in Kconfig, suggested by Andrew and Jonathan. RFC v1: https://lore.kernel.org/all/20240731094245.1967834-1-shaojijie@hu= awei.com/ --- drivers/net/ethernet/hisilicon/Kconfig | 16 +++++++++++++++- drivers/net/ethernet/hisilicon/Makefile | 1 + drivers/net/ethernet/hisilicon/hibmcge/Makefile | 10 ++++++++++ 3 files changed, 26 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/hisilicon/hibmcge/Makefile diff --git a/drivers/net/ethernet/hisilicon/Kconfig b/drivers/net/ethernet/= hisilicon/Kconfig index 3312e1d93c3b..66444794ce86 100644 --- a/drivers/net/ethernet/hisilicon/Kconfig +++ b/drivers/net/ethernet/hisilicon/Kconfig @@ -7,7 +7,6 @@ config NET_VENDOR_HISILICON bool "Hisilicon devices" default y depends on OF || ACPI - depends on ARM || ARM64 || COMPILE_TEST help If you have a network (Ethernet) card belonging to this class, say Y. =20 @@ -18,6 +17,8 @@ config NET_VENDOR_HISILICON =20 if NET_VENDOR_HISILICON =20 +if ARM || ARM64 || COMPILE_TEST + config HIX5HD2_GMAC tristate "Hisilicon HIX5HD2 Family Network Device Support" select PHYLIB @@ -141,4 +142,17 @@ config HNS3_ENET =20 endif #HNS3 =20 +endif # ARM || ARM64 || COMPILE_TEST + +config HIBMCGE + tristate "Hisilicon BMC Gigabit Ethernet Device Support" + depends on PCI && PCI_MSI + select PHYLIB + help + If you wish to compile a kernel for a BMC with HIBMC-xx_gmac + then you should answer Y to this. This makes this driver suitable for u= se + on certain boards such as the HIBMC-210. + + If you are unsure, say N. + endif # NET_VENDOR_HISILICON diff --git a/drivers/net/ethernet/hisilicon/Makefile b/drivers/net/ethernet= /hisilicon/Makefile index 7f76d412047a..0e2cadfea8ff 100644 --- a/drivers/net/ethernet/hisilicon/Makefile +++ b/drivers/net/ethernet/hisilicon/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_HNS_MDIO) +=3D hns_mdio.o obj-$(CONFIG_HNS) +=3D hns/ obj-$(CONFIG_HNS3) +=3D hns3/ obj-$(CONFIG_HISI_FEMAC) +=3D hisi_femac.o +obj-$(CONFIG_HIBMCGE) +=3D hibmcge/ diff --git a/drivers/net/ethernet/hisilicon/hibmcge/Makefile b/drivers/net/= ethernet/hisilicon/hibmcge/Makefile new file mode 100644 index 000000000000..ea223b7207af --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hibmcge/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Makefile for the HISILICON BMC GE network device drivers. +# + +ccflags-y +=3D -I$(src) + +obj-$(CONFIG_HIBMCGE) +=3D hibmcge.o + +hibmcge-objs =3D hbg_main.o hbg_hw.o hbg_mdio.o hbg_irq.o hbg_txrx.o hbg_e= thtool.o --=20 2.33.0 From nobody Sat Nov 30 10:39:28 2024 Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C52B188014; Tue, 10 Sep 2024 08:06:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.191 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725955580; cv=none; b=tXhQ6uLL4wc24sUKlKxgB0dRrGhkqK6NmuCFrZQMGnqIxZHQ3SDNFyrKemBpuBUSp+FXK4dn5wpOu1IAmJhEvGLsieMNZJf0IJuRBt2fWc0PLsGWgypDidLAPHN+bLTofDgDZGpXe5DS9f86VdKqTvmDQvTzpsqQ0YudF48/A0c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725955580; c=relaxed/simple; bh=IEtEWjsuShD8FJcsKMs/Yj9xZ5lZZr8ZrDfvneql7kY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NT51qlKmkILfacZbRYf8hkBBZu6YUP0PWLviWLb+dBndgcsgYGzWxfXE1Facg90GFMXHloZ2o/PggUf5yNu98usr7jIGo+HwnNi76lQL/1QeMthfKzeNVwWYeqsSR1bXZ3zOw4IvqHAQkFsRIJ9RsG7wjIaxS3u6ZXAITyNMVVg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.191 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.44]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4X2x5G1Hqjz1HJVG; Tue, 10 Sep 2024 16:02:42 +0800 (CST) Received: from kwepemm000007.china.huawei.com (unknown [7.193.23.189]) by mail.maildlp.com (Postfix) with ESMTPS id 1DC4A1402DE; Tue, 10 Sep 2024 16:06:16 +0800 (CST) Received: from localhost.localdomain (10.90.30.45) by kwepemm000007.china.huawei.com (7.193.23.189) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 10 Sep 2024 16:06:15 +0800 From: Jijie Shao To: , , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH V9 net-next 10/11] net: hibmcge: Add maintainer for hibmcge Date: Tue, 10 Sep 2024 15:59:41 +0800 Message-ID: <20240910075942.1270054-11-shaojijie@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20240910075942.1270054-1-shaojijie@huawei.com> References: <20240910075942.1270054-1-shaojijie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemm000007.china.huawei.com (7.193.23.189) Content-Type: text/plain; charset="utf-8" Add myself as the maintainer for the hibmcge ethernet driver. Signed-off-by: Jijie Shao --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index ca1469d52076..703ecc5b50b8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10149,6 +10149,13 @@ S: Maintained W: http://www.hisilicon.com F: drivers/net/ethernet/hisilicon/hns3/ =20 +HISILICON NETWORK HIBMCGE DRIVER +M: Jijie Shao +L: netdev@vger.kernel.org +S: Maintained +W: http://www.hisilicon.com +F: drivers/net/ethernet/hisilicon/hibmcge/ + HISILICON NETWORK SUBSYSTEM DRIVER M: Yisen Zhuang M: Salil Mehta --=20 2.33.0 From nobody Sat Nov 30 10:39:28 2024 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50410188A3A; Tue, 10 Sep 2024 08:06:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.190 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725955581; cv=none; b=ckgxY4DZm/RZIiLBdpuKPSXQeu7vfBdjyb/e0cHrZbF8Szi6Vr7nApqcFAplWcl2qJpwysNvp0oI2JekcWHIy0TNl9lSz321H8gg5WTWBB21xZ+4o4Vx9GT9BHOM3+iT+ov2BjB8f5noAMWgV+SwSI/FwJb46UrEwJF24xbrepc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725955581; c=relaxed/simple; bh=AzWTqf9mgdhH51glUN+Q5u9Y9J9MonZTUf7E4KxwEHY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dHW8BIWW3zxnIqr0ZQ5o2eBAsUvDtnU/w7iiGCapq9fN/MwZIO7STYPRbQ6+x1nB9qTsFh4/MAQZqK+8lmY1LSg6yL381blu/fvAPV4gV+OyIpewPrQgYOiWSvXWU5pWWXNjal7dbriQg1SidRCOCHID682CjojORsf9QsPfJyw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.190 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.17]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4X2x8r6xypz2Dc3f; Tue, 10 Sep 2024 16:05:48 +0800 (CST) Received: from kwepemm000007.china.huawei.com (unknown [7.193.23.189]) by mail.maildlp.com (Postfix) with ESMTPS id D7EC61A0188; Tue, 10 Sep 2024 16:06:16 +0800 (CST) Received: from localhost.localdomain (10.90.30.45) by kwepemm000007.china.huawei.com (7.193.23.189) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 10 Sep 2024 16:06:15 +0800 From: Jijie Shao To: , , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH V9 net-next 11/11] net: add ndo_validate_addr check in dev_set_mac_address Date: Tue, 10 Sep 2024 15:59:42 +0800 Message-ID: <20240910075942.1270054-12-shaojijie@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20240910075942.1270054-1-shaojijie@huawei.com> References: <20240910075942.1270054-1-shaojijie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemm000007.china.huawei.com (7.193.23.189) Content-Type: text/plain; charset="utf-8" If driver implements ndo_validate_addr, core should check the mac address before ndo_set_mac_address. Signed-off-by: Jijie Shao Reviewed-by: Andrew Lunn --- ChangeLog: v2 -> v3: - Use ndo_validate_addr() instead of is_valid_ether_addr() in dev_set_mac_address(), suggested by Jakub and Andrew. v2: https://lore.kernel.org/all/20240820140154.137876-1-shaojijie@huawei.= com/ --- net/core/dev.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/net/core/dev.c b/net/core/dev.c index 22c3f14d9287..00e0f473ed44 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -9087,6 +9087,11 @@ int dev_set_mac_address(struct net_device *dev, stru= ct sockaddr *sa, return -EOPNOTSUPP; if (sa->sa_family !=3D dev->type) return -EINVAL; + if (ops->ndo_validate_addr) { + err =3D ops->ndo_validate_addr(dev); + if (err) + return err; + } if (!netif_device_present(dev)) return -ENODEV; err =3D dev_pre_changeaddr_notify(dev, sa->sa_data, extack); --=20 2.33.0