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[88.10.59.201]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42cc01cae3asm5516055e9.0.2024.09.09.21.40.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Sep 2024 21:40:28 -0700 (PDT) From: Sergio Paracuellos To: linux-clk@vger.kernel.org Cc: sboyd@kernel.org, mturquette@baylibre.com, tsbogend@alpha.franken.de, yangshiji66@outlook.com, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] clk: ralink: mtmips: add mmc related clocks for SoCs MT7620, MT7628 and MT7688 Date: Tue, 10 Sep 2024 06:40:24 +0200 Message-Id: <20240910044024.120009-4-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240910044024.120009-1-sergio.paracuellos@gmail.com> References: <20240910044024.120009-1-sergio.paracuellos@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Original architecture clock code from where this driver was derived did not include nothing related to mmc clocks. OpenWRT people started to use mtk-sd upstream driver recently and they were forced to use a dts 'fixed-clock' node with 48 MHz clock: - https://github.com/openwrt/openwrt/pull/15896 The proper thing to do to avoid that is to add the mmc related clocks to the driver to avoid a dts with fixed clocks nodes. The minimal documentation in the mt7620 programming guide says that there is a BBP_PLL clock of 480 MHz derived from the 40 MHz XTAL and from there a clock divider by ten produces the desired SDHC clock of 48 MHz for the mmc. Hence add a fixed clock 'bbpp= ll' and factor clock 'sdhc' ten divider child to properly set the 'mmc' periphe= ral clock with the desired 48 Mhz rate. Signed-off-by: Sergio Paracuellos --- drivers/clk/ralink/clk-mtmips.c | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/drivers/clk/ralink/clk-mtmips.c b/drivers/clk/ralink/clk-mtmip= s.c index 76285fbbdeaa..97b8ca0f9181 100644 --- a/drivers/clk/ralink/clk-mtmips.c +++ b/drivers/clk/ralink/clk-mtmips.c @@ -207,6 +207,7 @@ static struct mtmips_clk mt7620_pherip_clks[] =3D { { CLK_PERIPH("10000b00.spi", "bus") }, { CLK_PERIPH("10000b40.spi", "bus") }, { CLK_PERIPH("10000c00.uartlite", "periph") }, + { CLK_PERIPH("10130000.mmc", "sdhc") }, { CLK_PERIPH("10180000.wmac", "xtal") } }; =20 @@ -220,6 +221,7 @@ static struct mtmips_clk mt76x8_pherip_clks[] =3D { { CLK_PERIPH("10000c00.uart0", "periph") }, { CLK_PERIPH("10000d00.uart1", "periph") }, { CLK_PERIPH("10000e00.uart2", "periph") }, + { CLK_PERIPH("10130000.mmc", "sdhc") }, { CLK_PERIPH("10300000.wmac", "xtal") } }; =20 @@ -272,8 +274,13 @@ static struct mtmips_clk_fixed rt3352_fixed_clocks[] = =3D { CLK_FIXED("periph", "xtal", 40000000) }; =20 +static struct mtmips_clk_fixed mt7620_fixed_clocks[] =3D { + CLK_FIXED("bbppll", "xtal", 480000000) +}; + static struct mtmips_clk_fixed mt76x8_fixed_clocks[] =3D { - CLK_FIXED("pcmi2s", "xtal", 480000000), + CLK_FIXED("bbppll", "xtal", 480000000), + CLK_FIXED("pcmi2s", "bbppll", 480000000), CLK_FIXED("periph", "xtal", 40000000) }; =20 @@ -328,6 +335,15 @@ static struct mtmips_clk_factor rt305x_factor_clocks[]= =3D { CLK_FACTOR("bus", "cpu", 1, 3) }; =20 +static struct mtmips_clk_factor mt7620_factor_clocks[] =3D { + CLK_FACTOR("sdhc", "bbppll", 1, 10) +}; + +static struct mtmips_clk_factor mt76x8_factor_clocks[] =3D { + CLK_FACTOR("bus", "cpu", 1, 3), + CLK_FACTOR("sdhc", "bbppll", 1, 10) +}; + static int mtmips_register_factor_clocks(struct clk_hw_onecell_data *clk_d= ata, struct mtmips_clk_priv *priv) { @@ -811,10 +827,10 @@ static const struct mtmips_clk_data rt5350_clk_data = =3D { static const struct mtmips_clk_data mt7620_clk_data =3D { .clk_base =3D mt7620_clks_base, .num_clk_base =3D ARRAY_SIZE(mt7620_clks_base), - .clk_fixed =3D NULL, - .num_clk_fixed =3D 0, - .clk_factor =3D NULL, - .num_clk_factor =3D 0, + .clk_fixed =3D mt7620_fixed_clocks, + .num_clk_fixed =3D ARRAY_SIZE(mt7620_fixed_clocks), + .clk_factor =3D mt7620_factor_clocks, + .num_clk_factor =3D ARRAY_SIZE(mt7620_factor_clocks), .clk_periph =3D mt7620_pherip_clks, .num_clk_periph =3D ARRAY_SIZE(mt7620_pherip_clks), }; @@ -824,8 +840,8 @@ static const struct mtmips_clk_data mt76x8_clk_data =3D= { .num_clk_base =3D ARRAY_SIZE(mt76x8_clks_base), .clk_fixed =3D mt76x8_fixed_clocks, .num_clk_fixed =3D ARRAY_SIZE(mt76x8_fixed_clocks), - .clk_factor =3D rt305x_factor_clocks, - .num_clk_factor =3D ARRAY_SIZE(rt305x_factor_clocks), + .clk_factor =3D mt76x8_factor_clocks, + .num_clk_factor =3D ARRAY_SIZE(mt76x8_factor_clocks), .clk_periph =3D mt76x8_pherip_clks, .num_clk_periph =3D ARRAY_SIZE(mt76x8_pherip_clks), }; --=20 2.25.1