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[88.10.59.201]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42cc01cae3asm5516055e9.0.2024.09.09.21.40.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Sep 2024 21:40:27 -0700 (PDT) From: Sergio Paracuellos To: linux-clk@vger.kernel.org Cc: sboyd@kernel.org, mturquette@baylibre.com, tsbogend@alpha.franken.de, yangshiji66@outlook.com, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs Date: Tue, 10 Sep 2024 06:40:23 +0200 Message-Id: <20240910044024.120009-3-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240910044024.120009-1-sergio.paracuellos@gmail.com> References: <20240910044024.120009-1-sergio.paracuellos@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Base clocks are the first in being probed and are real dependencies of the rest of fixed, factor and peripheral clocks. For old ralink SoCs RT2880, RT305x and RT3883 'xtal' must be defined first since in any other case, when fixed clocks are probed they are delayed until 'xtal' is probed so the following warning appears: WARNING: CPU: 0 PID: 0 at drivers/clk/ralink/clk-mtmips.c:499 rt3883_bus_r= ecalc_rate+0x98/0x138 Modules linked in: CPU: 0 PID: 0 Comm: swapper Not tainted 6.6.43 #0 Stack : 805e58d0 00000000 00000004 8004f950 00000000 00000004 00000000 000= 00000 80669c54 80830000 80700000 805ae570 80670068 00000001 80669bf8 00000000 00000000 00000000 805ae570 80669b38 00000020 804db7dc 00000000 00000000 203a6d6d 80669b78 80669e48 70617773 00000000 805ae570 00000000 00000009 00000000 00000001 00000004 00000001 00000000 00000000 83fe43b0 00000000 ... Call Trace: [<800065d0>] show_stack+0x64/0xf4 [<804bca14>] dump_stack_lvl+0x38/0x60 [<800218ac>] __warn+0x94/0xe4 [<8002195c>] warn_slowpath_fmt+0x60/0x94 [<80259ff8>] rt3883_bus_recalc_rate+0x98/0x138 [<80254530>] __clk_register+0x568/0x688 [<80254838>] of_clk_hw_register+0x18/0x2c [<8070b910>] rt2880_clk_of_clk_init_driver+0x18c/0x594 [<8070b628>] of_clk_init+0x1c0/0x23c [<806fc448>] plat_time_init+0x58/0x18c [<806fdaf0>] time_init+0x10/0x6c [<806f9bc4>] start_kernel+0x458/0x67c ---[ end trace 0000000000000000 ]--- When this driver was mainlined we could not find any active users of old ralink SoCs so we cannot perform any real tests for them. Now, one user of a Belkin f9k1109 version 1 device which uses RT3883 SoC appeared and reported some issues in openWRT: - https://github.com/openwrt/openwrt/issues/16054 Thus, define a 'rt2880_xtal_recalc_rate()' just returning the expected frequency 40Mhz and use it along the old ralink SoCs to have a correct boot trace with no warnings and a working clock plan from the beggining. Fixes: 6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS So= Cs") Signed-off-by: Sergio Paracuellos --- drivers/clk/ralink/clk-mtmips.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/clk/ralink/clk-mtmips.c b/drivers/clk/ralink/clk-mtmip= s.c index 62f9801ecd3a..76285fbbdeaa 100644 --- a/drivers/clk/ralink/clk-mtmips.c +++ b/drivers/clk/ralink/clk-mtmips.c @@ -263,10 +263,6 @@ static int mtmips_register_pherip_clocks(struct device= _node *np, .rate =3D _rate \ } =20 -static struct mtmips_clk_fixed rt305x_fixed_clocks[] =3D { - CLK_FIXED("xtal", NULL, 40000000) -}; - static struct mtmips_clk_fixed rt3883_fixed_clocks[] =3D { CLK_FIXED("xtal", NULL, 40000000), CLK_FIXED("periph", "xtal", 40000000) @@ -371,6 +367,12 @@ static inline struct mtmips_clk *to_mtmips_clk(struct = clk_hw *hw) return container_of(hw, struct mtmips_clk, hw); } =20 +static unsigned long rt2880_xtal_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return 40000000; +} + static unsigned long rt5350_xtal_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -682,10 +684,12 @@ static unsigned long mt76x8_cpu_recalc_rate(struct cl= k_hw *hw, } =20 static struct mtmips_clk rt2880_clks_base[] =3D { + { CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) }, { CLK_BASE("cpu", "xtal", rt2880_cpu_recalc_rate) } }; =20 static struct mtmips_clk rt305x_clks_base[] =3D { + { CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) }, { CLK_BASE("cpu", "xtal", rt305x_cpu_recalc_rate) } }; =20 @@ -695,6 +699,7 @@ static struct mtmips_clk rt3352_clks_base[] =3D { }; =20 static struct mtmips_clk rt3883_clks_base[] =3D { + { CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) }, { CLK_BASE("cpu", "xtal", rt3883_cpu_recalc_rate) }, { CLK_BASE("bus", "cpu", rt3883_bus_recalc_rate) } }; @@ -751,8 +756,8 @@ static int mtmips_register_clocks(struct device_node *n= p, static const struct mtmips_clk_data rt2880_clk_data =3D { .clk_base =3D rt2880_clks_base, .num_clk_base =3D ARRAY_SIZE(rt2880_clks_base), - .clk_fixed =3D rt305x_fixed_clocks, - .num_clk_fixed =3D ARRAY_SIZE(rt305x_fixed_clocks), + .clk_fixed =3D NULL, + .num_clk_fixed =3D 0, .clk_factor =3D rt2880_factor_clocks, .num_clk_factor =3D ARRAY_SIZE(rt2880_factor_clocks), .clk_periph =3D rt2880_pherip_clks, @@ -762,8 +767,8 @@ static const struct mtmips_clk_data rt2880_clk_data =3D= { static const struct mtmips_clk_data rt305x_clk_data =3D { .clk_base =3D rt305x_clks_base, .num_clk_base =3D ARRAY_SIZE(rt305x_clks_base), - .clk_fixed =3D rt305x_fixed_clocks, - .num_clk_fixed =3D ARRAY_SIZE(rt305x_fixed_clocks), + .clk_fixed =3D NULL, + .num_clk_fixed =3D 0, .clk_factor =3D rt305x_factor_clocks, .num_clk_factor =3D ARRAY_SIZE(rt305x_factor_clocks), .clk_periph =3D rt305x_pherip_clks, --=20 2.25.1