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[88.10.59.201]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42cc01cae3asm5516055e9.0.2024.09.09.21.40.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Sep 2024 21:40:26 -0700 (PDT) From: Sergio Paracuellos To: linux-clk@vger.kernel.org Cc: sboyd@kernel.org, mturquette@baylibre.com, tsbogend@alpha.franken.de, yangshiji66@outlook.com, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] clk: ralink: mtmips: fix clock plan for Ralink SoC RT3883 Date: Tue, 10 Sep 2024 06:40:22 +0200 Message-Id: <20240910044024.120009-2-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240910044024.120009-1-sergio.paracuellos@gmail.com> References: <20240910044024.120009-1-sergio.paracuellos@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Clock plan for Ralink SoC RT3883 needs an extra 'periph' clock to properly set some peripherals that has this clock as their parent. When this driver was mainlined we could not find any active users of this SoC so we cannot perform any real tests for it. Now, one user of a Belkin f9k1109 version 1 device which uses this SoC appear and reported some issues in openWRT: - https://github.com/openwrt/openwrt/issues/16054 The peripherals that are wrong are 'uart', 'i2c', 'i2s' and 'uartlite' which has a not defined 'periph' clock as parent. Hence, introduce it to have a properly working clock plan for this SoC. Fixes: 6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS So= Cs") Signed-off-by: Sergio Paracuellos --- drivers/clk/ralink/clk-mtmips.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/clk/ralink/clk-mtmips.c b/drivers/clk/ralink/clk-mtmip= s.c index 50a443bf79ec..62f9801ecd3a 100644 --- a/drivers/clk/ralink/clk-mtmips.c +++ b/drivers/clk/ralink/clk-mtmips.c @@ -267,6 +267,11 @@ static struct mtmips_clk_fixed rt305x_fixed_clocks[] = =3D { CLK_FIXED("xtal", NULL, 40000000) }; =20 +static struct mtmips_clk_fixed rt3883_fixed_clocks[] =3D { + CLK_FIXED("xtal", NULL, 40000000), + CLK_FIXED("periph", "xtal", 40000000) +}; + static struct mtmips_clk_fixed rt3352_fixed_clocks[] =3D { CLK_FIXED("periph", "xtal", 40000000) }; @@ -779,8 +784,8 @@ static const struct mtmips_clk_data rt3352_clk_data =3D= { static const struct mtmips_clk_data rt3883_clk_data =3D { .clk_base =3D rt3883_clks_base, .num_clk_base =3D ARRAY_SIZE(rt3883_clks_base), - .clk_fixed =3D rt305x_fixed_clocks, - .num_clk_fixed =3D ARRAY_SIZE(rt305x_fixed_clocks), + .clk_fixed =3D rt3883_fixed_clocks, + .num_clk_fixed =3D ARRAY_SIZE(rt3883_fixed_clocks), .clk_factor =3D NULL, .num_clk_factor =3D 0, .clk_periph =3D rt5350_pherip_clks, --=20 2.25.1