From nobody Sat Nov 30 10:38:18 2024 Received: from www530.your-server.de (www530.your-server.de [188.40.30.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0CE518FDB1; Tue, 10 Sep 2024 10:27:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=188.40.30.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725964047; cv=none; b=l+M/cu92c+Uq8Io4SFHXcMTo/2WIsqsmiWvsJzKuuunVvWUH8yLSRhdy5iFGSkgSoHKTYU3rE6naQi4u/KoN5aqNG0xpii4rYQ3wH7LNRG8X8T1xopni1Kjqyp2WBQxMKMySik7Ek4ect9GdKwvhE4BPvhWGn15Kq59t+lw/Vqc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725964047; c=relaxed/simple; bh=/VCo3XRpUVs+ODdkjbFXah0zX1uRcsm6ZU80nw+Wnkg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=I0tTKzGsvJi2US4bWi17oVdvocp6SmIztoP/9mH+kwdbuDW2FPC4Hkhu7OgzB67YTKeaEyit8m1QOIG5VaBnfG2YZhaz0EZJiS6cddqjr/nQvYpuQJYHBTqc4Hfbm16c3Or8+COqw2PnYeKT1H5P4meChEP981Pg0hq9MNJHsnY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=geanix.com; spf=pass smtp.mailfrom=geanix.com; dkim=pass (2048-bit key) header.d=geanix.com header.i=@geanix.com header.b=KpL+b2K9; arc=none smtp.client-ip=188.40.30.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=geanix.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=geanix.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=geanix.com header.i=@geanix.com header.b="KpL+b2K9" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=geanix.com; s=default2211; h=Cc:To:In-Reply-To:References:Message-Id: Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From:Sender: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID; bh=yt9WoZ0adE82ZlbhbGGDqQ9EFvIA4tp5imjpHwFF5ms=; b=KpL+b2K93gmmywGJkOg6r9b9BK qoTIN4ETEXzXFSeSkmqAGCsTWL5QVhkoReSTvMAcXdG6kr4Q9laOtIxN1jd+G4OOBi59//6LC7WJ+ gQ7+VJZawlnsfBBUX5YttlHel1aaPXXqL2oNTXE8kYweSMQGg6/nGQ3zqvA4jtlhvVWhEJ4U/Jqow l/DtaYZqAvMHDXozfuSC7ubF2EC1g/iAhQiFWBIzrXUirS1HF99pSAwedQdFMKLcuIdzIpupl5HMr 7dhkzcK9cI1y1y2+d85tuYNcwwkBzhv5F5COgFC4qOZvOgm7JgG5+Bsft+Uv7wZoys54kUu1bf0Xe 9ii+DbJQ==; Received: from sslproxy01.your-server.de ([78.46.139.224]) by www530.your-server.de with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1sny5h-000GsJ-I2; Tue, 10 Sep 2024 12:27:21 +0200 Received: from [80.62.117.18] (helo=localhost) by sslproxy01.your-server.de with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1sny5h-000Ml6-2c; Tue, 10 Sep 2024 12:27:21 +0200 From: Esben Haabendal Date: Tue, 10 Sep 2024 12:27:11 +0200 Subject: [PATCH 2/2] rtc: isl12022: Add alarm support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240910-rtc-isl12022-alarm-irq-v1-2-d875cedc997f@geanix.com> References: <20240910-rtc-isl12022-alarm-irq-v1-0-d875cedc997f@geanix.com> In-Reply-To: <20240910-rtc-isl12022-alarm-irq-v1-0-d875cedc997f@geanix.com> To: Alexandre Belloni , Rasmus Villemoes Cc: linux-rtc@vger.kernel.org, linux-kernel@vger.kernel.org, Esben Haabendal X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1725964039; l=10043; i=esben@geanix.com; s=20240523; h=from:subject:message-id; bh=/VCo3XRpUVs+ODdkjbFXah0zX1uRcsm6ZU80nw+Wnkg=; b=iOGDNc8FZHtSZxRt6z7QypzBk2Kc7GZ+wx/kMBEjUPUOyevm45ZHP+SWAsC8SYKXvuB/H89Zd vfJuV8sNOoZDW7hyNd8eAz5h2hj9Hag+ayw6UyehK/+Z7zW5IBfKqv+ X-Developer-Key: i=esben@geanix.com; a=ed25519; pk=PbXoezm+CERhtgVeF/QAgXtEzSkDIahcWfC7RIXNdEk= X-Authenticated-Sender: esben@geanix.com X-Virus-Scanned: Clear (ClamAV 0.103.10/27394/Tue Sep 10 10:30:36 2024) The ISL12022 RTC has a combined INT/fOUT pin, which can be used for alarm interrupt when frequency output is not enabled. The device-tree bindings should ensure that interrupt and clock output is not enabled at the same time. Signed-off-by: Esben Haabendal --- drivers/rtc/rtc-isl12022.c | 244 +++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 241 insertions(+), 3 deletions(-) diff --git a/drivers/rtc/rtc-isl12022.c b/drivers/rtc/rtc-isl12022.c index d82278fdc29b..682b1bf10160 100644 --- a/drivers/rtc/rtc-isl12022.c +++ b/drivers/rtc/rtc-isl12022.c @@ -21,7 +21,7 @@ =20 #include =20 -/* ISL register offsets */ +/* RTC - Real time clock registers */ #define ISL12022_REG_SC 0x00 #define ISL12022_REG_MN 0x01 #define ISL12022_REG_HR 0x02 @@ -30,21 +30,36 @@ #define ISL12022_REG_YR 0x05 #define ISL12022_REG_DW 0x06 =20 +/* CSR - Control and status registers */ #define ISL12022_REG_SR 0x07 #define ISL12022_REG_INT 0x08 - #define ISL12022_REG_PWR_VBAT 0x0a - #define ISL12022_REG_BETA 0x0d + +/* ALARM - Alarm registers */ +#define ISL12022_REG_SCA0 0x10 +#define ISL12022_REG_MNA0 0x11 +#define ISL12022_REG_HRA0 0x12 +#define ISL12022_REG_DTA0 0x13 +#define ISL12022_REG_MOA0 0x14 +#define ISL12022_REG_DWA0 0x15 +#define ISL12022_ALARM_SECTION ISL12022_REG_SCA0 +#define ISL12022_ALARM_SECTION_LEN (ISL12022_REG_DWA0 - ISL12022_REG_SCA0 = + 1) + +/* TEMP - Temperature sensor registers */ #define ISL12022_REG_TEMP_L 0x28 =20 /* ISL register bits */ #define ISL12022_HR_MIL (1 << 7) /* military or 24 hour time */ =20 +#define ISL12022_SR_ALM (1 << 4) #define ISL12022_SR_LBAT85 (1 << 2) #define ISL12022_SR_LBAT75 (1 << 1) =20 +#define ISL12022_INT_ARST (1 << 7) #define ISL12022_INT_WRTC (1 << 6) +#define ISL12022_INT_IM (1 << 5) +#define ISL12022_INT_FOBATB (1 << 4) #define ISL12022_INT_FO_MASK GENMASK(3, 0) #define ISL12022_INT_FO_OFF 0x0 #define ISL12022_INT_FO_32K 0x1 @@ -52,10 +67,18 @@ #define ISL12022_REG_VB85_MASK GENMASK(5, 3) #define ISL12022_REG_VB75_MASK GENMASK(2, 0) =20 +#define ISL12022_ALARM_ENABLE (1 << 7) /* for all ALARM registers */ + #define ISL12022_BETA_TSE (1 << 7) =20 +static struct i2c_driver isl12022_driver; + struct isl12022 { + struct i2c_client *i2c; + struct rtc_device *rtc; struct regmap *regmap; + int irq; + bool irq_enabled; }; =20 static umode_t isl12022_hwmon_is_visible(const void *data, @@ -215,6 +238,208 @@ static int isl12022_rtc_set_time(struct device *dev, = struct rtc_time *tm) return regmap_bulk_write(regmap, ISL12022_REG_SC, buf, sizeof(buf)); } =20 +static int isl12022_rtc_read_alarm(struct device *dev, + struct rtc_wkalrm *alarm) +{ + struct rtc_time *const tm =3D &alarm->time; + struct isl12022 *isl12022 =3D dev_get_drvdata(dev); + struct regmap *regmap =3D isl12022->regmap; + uint8_t buf[ISL12022_ALARM_SECTION_LEN]; + int ret, yr, i; + + ret =3D regmap_bulk_read(regmap, ISL12022_ALARM_SECTION, + buf, sizeof(buf)); + if (ret) { + dev_err(dev, "%s: reading ALARM registers failed\n", + __func__); + return ret; + } + + dev_dbg(dev, + "%s: sc=3D%02x, mn=3D%02x, hr=3D%02x, dt=3D%02x, mo=3D%02x, dw=3D%02x\n", + __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); + + tm->tm_sec =3D bcd2bin(buf[ISL12022_REG_SCA0 - ISL12022_ALARM_SECTION] + & 0x7F); + tm->tm_min =3D bcd2bin(buf[ISL12022_REG_MNA0 - ISL12022_ALARM_SECTION] + & 0x7F); + tm->tm_hour =3D bcd2bin(buf[ISL12022_REG_HRA0 - ISL12022_ALARM_SECTION] + & 0x3F); + tm->tm_mday =3D bcd2bin(buf[ISL12022_REG_DTA0 - ISL12022_ALARM_SECTION] + & 0x3F); + tm->tm_mon =3D bcd2bin(buf[ISL12022_REG_MOA0 - ISL12022_ALARM_SECTION] + & 0x1F) - 1; + tm->tm_wday =3D buf[ISL12022_REG_DWA0 - ISL12022_ALARM_SECTION] & 0x07; + + /* The alarm doesn't store the year so get it from the rtc section */ + ret =3D regmap_read(regmap, ISL12022_REG_YR, &yr); + if (ret) { + dev_err(dev, "%s: reading YR register failed\n", __func__); + return yr; + } + tm->tm_year =3D bcd2bin(yr) + 100; + + for (i =3D 0 ; i < ISL12022_ALARM_SECTION_LEN ; i++) { + if (buf[i] & ISL12022_ALARM_ENABLE) { + alarm->enabled =3D 1; + break; + } + } + + dev_dbg(dev, "%s: %ptR\n", __func__, tm); + + return 0; +} + +static int isl12022_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *a= larm) +{ + struct rtc_time *alarm_tm =3D &alarm->time; + struct isl12022 *isl12022 =3D dev_get_drvdata(dev); + struct regmap *regmap =3D isl12022->regmap; + u8 regs[ISL12022_ALARM_SECTION_LEN] =3D { 0, }; + struct rtc_time rtc_tm; + int ret =3D 0, enable, dw; + + ret =3D isl12022_rtc_read_time(dev, &rtc_tm); + if (ret) + return ret; + + /* If the alarm time is before the current time disable the alarm */ + if (!alarm->enabled || rtc_tm_sub(alarm_tm, &rtc_tm) <=3D 0) + enable =3D 0; + else + enable =3D ISL12022_ALARM_ENABLE; + + /* Set non-matching tm_wday to safeguard against early false matching + * while setting all the alarm registers (this rtc lacks a general + * alarm/irq enable/disable bit). + */ + if (enable) { + ret =3D regmap_read(regmap, ISL12022_REG_DW, &dw); + if (ret) { + dev_err(dev, "%s: reading DW failed\n", __func__); + return ret; + } + /* ~4 days into the future should be enough to avoid match */ + dw =3D ((dw + 4) % 7) | ISL12022_ALARM_ENABLE; + ret =3D regmap_write(regmap, ISL12022_REG_DWA0, dw); + if (ret) { + dev_err(dev, "%s: writing DWA0 failed\n", __func__); + return ret; + } + } + + /* Program the alarm and enable it for each setting */ + regs[ISL12022_REG_SCA0 - ISL12022_ALARM_SECTION] =3D + bin2bcd(alarm_tm->tm_sec) | enable; + regs[ISL12022_REG_MNA0 - ISL12022_ALARM_SECTION] =3D + bin2bcd(alarm_tm->tm_min) | enable; + regs[ISL12022_REG_HRA0 - ISL12022_ALARM_SECTION] =3D + bin2bcd(alarm_tm->tm_hour) | enable; + regs[ISL12022_REG_DTA0 - ISL12022_ALARM_SECTION] =3D + bin2bcd(alarm_tm->tm_mday) | enable; + regs[ISL12022_REG_MOA0 - ISL12022_ALARM_SECTION] =3D + bin2bcd(alarm_tm->tm_mon + 1) | enable; + regs[ISL12022_REG_DWA0 - ISL12022_ALARM_SECTION] =3D + bin2bcd(alarm_tm->tm_wday & 7) | enable; + + /* write ALARM registers */ + ret =3D regmap_bulk_write(regmap, ISL12022_REG_SCA0, + ®s, sizeof(regs)); + if (ret) { + dev_err(dev, "%s: writing ALARM registers failed\n", __func__); + return ret; + } + + return 0; +} + +static irqreturn_t isl12022_rtc_interrupt(int irq, void *data) +{ + struct isl12022 *isl12022 =3D data; + struct rtc_device *rtc =3D isl12022->rtc; + struct device *dev =3D &rtc->dev; + struct regmap *regmap =3D isl12022->regmap; + u32 val =3D 0; + unsigned long events =3D 0; + int ret; + + ret =3D regmap_read(regmap, ISL12022_REG_SR, &val); + if (ret) { + dev_err(dev, "%s: reading SR failed\n", __func__); + return IRQ_HANDLED; + } + + if (val & ISL12022_SR_ALM) + events |=3D RTC_IRQF | RTC_AF; + + if (events & RTC_AF) + dev_dbg(dev, "alarm!\n"); + + if (!events) + return IRQ_NONE; + + rtc_update_irq(rtc, 1, events); + return IRQ_HANDLED; +} + +static int isl12022_rtc_alarm_irq_enable(struct device *dev, + unsigned int enabled) +{ + struct isl12022 *isl12022 =3D dev_get_drvdata(dev); + + if (!isl12022->irq_enabled =3D=3D !enabled) + return 0; + + if (enabled) + enable_irq(isl12022->irq); + else + disable_irq(isl12022->irq); + + isl12022->irq_enabled =3D !!enabled; + + return 0; +} + +static int isl12022_setup_irq(struct isl12022 *isl12022, int irq) +{ + struct device *dev =3D &isl12022->i2c->dev; + struct regmap *regmap =3D isl12022->regmap; + unsigned int reg_mask, reg_val; + u8 buf[ISL12022_ALARM_SECTION_LEN] =3D { 0, }; + int ret; + + /* Clear and disable all alarm registers */ + ret =3D regmap_bulk_write(regmap, ISL12022_ALARM_SECTION, + buf, sizeof(buf)); + if (ret) + return ret; + + /* Enable automatic reset of ALM bit, enable single event interrupt + * mode, and disable IRQ/fOUT pin during battery-backup mode. + */ + reg_mask =3D ISL12022_INT_ARST | ISL12022_INT_IM + | ISL12022_INT_FOBATB | ISL12022_INT_FO_MASK; + reg_val =3D ISL12022_INT_ARST | ISL12022_INT_FOBATB | ISL12022_INT_FO_OFF; + ret =3D regmap_write_bits(regmap, ISL12022_REG_INT, + reg_mask, reg_val); + if (ret) + return ret; + + ret =3D devm_request_threaded_irq(dev, irq, NULL, + isl12022_rtc_interrupt, + IRQF_SHARED | IRQF_ONESHOT, + isl12022_driver.driver.name, + isl12022); + if (ret) { + dev_err(dev, "Unable to request irq %d\n", irq); + return ret; + } + + isl12022->irq =3D irq; + return 0; +} + static int isl12022_rtc_ioctl(struct device *dev, unsigned int cmd, unsign= ed long arg) { struct isl12022 *isl12022 =3D dev_get_drvdata(dev); @@ -246,6 +471,9 @@ static const struct rtc_class_ops isl12022_rtc_ops =3D { .ioctl =3D isl12022_rtc_ioctl, .read_time =3D isl12022_rtc_read_time, .set_time =3D isl12022_rtc_set_time, + .read_alarm =3D isl12022_rtc_read_alarm, + .set_alarm =3D isl12022_rtc_set_alarm, + .alarm_irq_enable =3D isl12022_rtc_alarm_irq_enable, }; =20 static const struct regmap_config regmap_config =3D { @@ -347,6 +575,7 @@ static int isl12022_probe(struct i2c_client *client) isl12022 =3D devm_kzalloc(&client->dev, sizeof(*isl12022), GFP_KERNEL); if (!isl12022) return -ENOMEM; + isl12022->i2c =3D client; =20 regmap =3D devm_regmap_init_i2c(client, ®map_config); if (IS_ERR(regmap)) { @@ -367,11 +596,20 @@ static int isl12022_probe(struct i2c_client *client) rtc =3D devm_rtc_allocate_device(&client->dev); if (IS_ERR(rtc)) return PTR_ERR(rtc); + isl12022->rtc =3D rtc; =20 rtc->ops =3D &isl12022_rtc_ops; rtc->range_min =3D RTC_TIMESTAMP_BEGIN_2000; rtc->range_max =3D RTC_TIMESTAMP_END_2099; =20 + if (client->irq > 0) { + ret =3D isl12022_setup_irq(isl12022, client->irq); + if (ret) + return ret; + } else { + clear_bit(RTC_FEATURE_ALARM, rtc->features); + } + return devm_rtc_register_device(rtc); } =20 --=20 2.46.0