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Tue, 10 Sep 2024 10:26:47 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48AAQkkB008537 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 10 Sep 2024 10:26:46 GMT Received: from lijuang2-gv.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 10 Sep 2024 03:26:40 -0700 From: Lijuan Gao Date: Tue, 10 Sep 2024 18:26:14 +0800 Subject: [PATCH 1/2] dt-bindings: pinctrl: document the QCS615 Top Level Mode Multiplexer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240910-add_qcs615_pinctrl_driver-v1-1-36f4c0d527d8@quicinc.com> References: <20240910-add_qcs615_pinctrl_driver-v1-0-36f4c0d527d8@quicinc.com> In-Reply-To: <20240910-add_qcs615_pinctrl_driver-v1-0-36f4c0d527d8@quicinc.com> To: Bjorn Andersson , Linus Walleij , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley CC: , , , , Lijuan Gao , X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1725963997; l=4593; i=quic_lijuang@quicinc.com; s=20240827; h=from:subject:message-id; bh=p+esQiYKXe8D4SjbEjAgwlRz6vwcmXzChsxGoZ5bohE=; b=4OnbX1XY+8BLMNm5TEZ7kBwxKqDQspQVb3GrLS/PoBD7DQ1dCt5CS7WIuKBBcMGazworKTWlE CPmcbA9XE5oCLPEBa4UHVb3xYUfNSRXa/w/mUm2b29Jkz3OcItvKqqU X-Developer-Key: i=quic_lijuang@quicinc.com; a=ed25519; pk=1zeM8FpQK/J1jSFHn8iXHeb3xt7F/3GvHv7ET2RNJxE= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: zXYnJUIau6Yip01IUl3Lx4c5mmrAyERz X-Proofpoint-ORIG-GUID: zXYnJUIau6Yip01IUl3Lx4c5mmrAyERz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 mlxlogscore=999 bulkscore=0 clxscore=1015 impostorscore=0 phishscore=0 spamscore=0 malwarescore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409100078 Document the Top Level Mode Multiplexer on the QCS615 Platform. It concisely explains the pin multiplexing and configuration in the device tree, and includes simple examples of typical device tree snippets, making it easier for designers to configure and manage chip pins. Signed-off-by: Lijuan Gao Reviewed-by: Rob Herring (Arm) --- .../bindings/pinctrl/qcom,qcs615-tlmm.yaml | 123 +++++++++++++++++= ++++ 1 file changed, 123 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yam= l b/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml new file mode 100644 index 000000000000..2bfb0a453880 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,qcs615-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. QCS615 TLMM block + +maintainers: + - Lijuan Gao + +description: + Top Level Mode Multiplexer pin controller in Qualcomm QCS615 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,qcs615-tlmm + + reg: + maxItems: 3 + + reg-names: + items: + - const: east + - const: west + - const: south + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 62 + + gpio-line-names: + maxItems: 123 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-qcs615-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-qcs615-tlmm-state" + additionalProperties: false + +$defs: + qcom-qcs615-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9]|12[0-2])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, + sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specif= ied + pins. + enum: [ gpio, adsp_ext, agera_pll, aoss_cti, atest_char, atest_tse= ns, + atest_usb, cam_mclk, cci_async, cci_i2c, cci_timer, copy_g= p, + copy_phase, cri_trng, dbg_out_clk, ddr_bist, ddr_pxi, dp_h= ot, + edp_hot, edp_lcd, emac_gcc, emac_phy_intr, forced_usb, gcc= _gp, + gp_pdm, gps_tx, hs0_mi2s, hs1_mi2s, jitter_bist, ldo_en, + ldo_update, m_voc, mclk1, mclk2, mdp_vsync, mdp_vsync0_out, + mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync4= _out, + mdp_vsync5_out, mi2s_1, mss_lte, nav_pps_in, nav_pps_out, + pa_indicator_or, pcie_clk_req, pcie_ep_rst, phase_flag, pl= l_bist, + pll_bypassnl, pll_reset_n, prng_rosc, qdss_cti, qdss_gpio, + qlink_enable, qlink_request, qspi, qup0, qup1, rgmii, + sd_write_protect, sp_cmu, ter_mi2s, tgu_ch, uim1, uim2, us= b0_hs, + usb1_hs, usb_phy_ps, vfr_1, vsense_trigger_mirnat, wlan, w= sa_clk, + wsa_data ] + + required: + - pins + +required: + - compatible + - reg + - reg-names + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@3000000 { + compatible =3D "qcom,qcs615-tlmm"; + reg =3D <0x03100000 0x300000>, + <0x03500000 0x300000>, + <0x03c00000 0x300000>; + reg-names =3D "east", "west", "south"; + interrupts =3D ; + gpio-ranges =3D <&tlmm 0 0 123>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + + qup3-uart2-state { + pins =3D"gpio16", "gpio17"; + function =3D "qup0"; + }; + }; +... --=20 2.46.0