From nobody Sat Nov 30 12:37:34 2024 Received: from out-180.mta1.migadu.com (out-180.mta1.migadu.com [95.215.58.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2EC33190493 for ; Mon, 9 Sep 2024 23:52:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725925948; cv=none; b=bAicz4sbrLq2ig7QVGrYDJcs6m9E/si/1Wm6oz3pTZW1Bo0tQC5LAogN6XXD45UJuv+FzAQAC2B9u3huCZ6rZkgMGzVr/Upr4RM0NVASrMm+foQB1iLMPasT4rkabVxlrOBtcGo7cep9KB7leg/oZP4BqlzybNGgphMbNc/yUJA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725925948; c=relaxed/simple; bh=gr11jDcnAqqsrY+bAIlwgcFY4bYrXpMdGHhMyyqLGKY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HC3RT59Kw587/RiuXyxWHfFvUV6xDxfmdo7DVujmvJ7nltuCcIR2tMQGyU/pB+lijqLdsTHgXDuxErU3oYVAU7+TIuNmaXIRtwYmhDc0yk0tFfhzJAMMaNVUBOm6vOIkWp0V4csRCW/pS4Rfd7UQ9tsjUfLW6Njjb9K0nBIk7SU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=afkAHv+M; arc=none smtp.client-ip=95.215.58.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="afkAHv+M" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1725925942; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RJdpdx91YG1zNlUWl852ey9iK3iuCbq4oAOQKlh44hg=; b=afkAHv+MeQvv+4DUqN76wtutiZ6PDOuK97AQ8aCDiVkc/d7ve9Li4YerTYmk2+s6rAZfVi OYSLrOAwkFJuzl5ou8sFrC6wkBGjMUTnuPtupcqp/lqE0yLNEvKgfsvfBgSjVl8zXh8Hcj W5vL2ipE0dpNz5KIIKZ8fZwtrlgNPDo= From: Sean Anderson To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Radhey Shyam Pandey , netdev@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Michal Simek , linux-kernel@vger.kernel.org, Sean Anderson Subject: [RFC PATCH net-next v2 5/6] net: xilinx: axienet: Get coalesce parameters from driver state Date: Mon, 9 Sep 2024 19:52:07 -0400 Message-Id: <20240909235208.1331065-6-sean.anderson@linux.dev> In-Reply-To: <20240909235208.1331065-1-sean.anderson@linux.dev> References: <20240909235208.1331065-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" The cr variables now contain the same values as the control registers themselves. Extract/calculate the values from the variables instead of saving the user-specified values. This allows us to remove some bookeeping, and also lets the user know what the actual coalesce settings are. Signed-off-by: Sean Anderson --- Changes in v2: - New drivers/net/ethernet/xilinx/xilinx_axienet.h | 8 --- .../net/ethernet/xilinx/xilinx_axienet_main.c | 70 +++++++++++++------ 2 files changed, 47 insertions(+), 31 deletions(-) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/eth= ernet/xilinx/xilinx_axienet.h index f0864cb8defe..33d05e55567e 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h @@ -533,10 +533,6 @@ struct skbuf_dma_descriptor { * @rxmem: Stores rx memory size for jumbo frame handling. * @csum_offload_on_tx_path: Stores the checksum selection on TX side. * @csum_offload_on_rx_path: Stores the checksum selection on RX side. - * @coalesce_count_rx: Store the irq coalesce on RX side. - * @coalesce_usec_rx: IRQ coalesce delay for RX - * @coalesce_count_tx: Store the irq coalesce on TX side. - * @coalesce_usec_tx: IRQ coalesce delay for TX * @use_dmaengine: flag to check dmaengine framework usage. * @tx_chan: TX DMA channel. * @rx_chan: RX DMA channel. @@ -617,10 +613,6 @@ struct axienet_local { int csum_offload_on_tx_path; int csum_offload_on_rx_path; =20 - u32 coalesce_count_rx; - u32 coalesce_usec_rx; - u32 coalesce_count_tx; - u32 coalesce_usec_tx; u8 use_dmaengine; struct dma_chan *tx_chan; struct dma_chan *rx_chan; diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/ne= t/ethernet/xilinx/xilinx_axienet_main.c index 6bcb605aa67e..eb9600417d81 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -223,6 +223,13 @@ static void axienet_dma_bd_release(struct net_device *= ndev) lp->rx_bd_p); } =20 +static u64 axienet_dma_rate(struct axienet_local *lp) +{ + if (lp->axi_clk) + return clk_get_rate(lp->axi_clk); + return 125000000; /* arbitrary guess if no clock rate set */ +} + /** * axienet_calc_cr() - Calculate control register value * @lp: Device private data @@ -243,12 +250,9 @@ static u32 axienet_calc_cr(struct axienet_local *lp, u= 32 count, u32 usec) * the first packet. Otherwise leave at 0 to disable delay interrupt. */ if (count > 1) { - u64 clk_rate =3D 125000000; /* arbitrary guess if no clock rate set */ + u64 clk_rate =3D axienet_dma_rate(lp); u32 timer; =20 - if (lp->axi_clk) - clk_rate =3D clk_get_rate(lp->axi_clk); - /* 1 Timeout Interval =3D 125 * (clock period of SG clock) */ timer =3D DIV64_U64_ROUND_CLOSEST((u64)usec * clk_rate, XAXIDMA_DELAY_SCALE); @@ -261,6 +265,23 @@ static u32 axienet_calc_cr(struct axienet_local *lp, u= 32 count, u32 usec) return cr; } =20 +/** + * axienet_cr_params() - Extract coalesce parameters from the CR + * @lp: Device private data + * @cr: The control register to parse + * @count: Number of packets before an interrupt + * @usec: Idle time (in usec) before an interrupt + */ +static void axienet_coalesce_params(struct axienet_local *lp, u32 cr, + u32 *count, u32 *usec) +{ + u64 clk_rate =3D axienet_dma_rate(lp); + u64 timer =3D FIELD_GET(XAXIDMA_DELAY_MASK, cr); + + *count =3D FIELD_GET(XAXIDMA_COALESCE_MASK, cr); + *usec =3D DIV64_U64_ROUND_CLOSEST(timer * XAXIDMA_DELAY_SCALE, clk_rate); +} + /** * axienet_dma_start - Set up DMA registers and start DMA operation * @lp: Pointer to the axienet_local structure @@ -2095,11 +2116,21 @@ axienet_ethtools_get_coalesce(struct net_device *nd= ev, struct netlink_ext_ack *extack) { struct axienet_local *lp =3D netdev_priv(ndev); + u32 cr; =20 - ecoalesce->rx_max_coalesced_frames =3D lp->coalesce_count_rx; - ecoalesce->rx_coalesce_usecs =3D lp->coalesce_usec_rx; - ecoalesce->tx_max_coalesced_frames =3D lp->coalesce_count_tx; - ecoalesce->tx_coalesce_usecs =3D lp->coalesce_usec_tx; + spin_lock_irq(&lp->rx_cr_lock); + cr =3D lp->rx_dma_cr; + spin_unlock_irq(&lp->rx_cr_lock); + axienet_coalesce_params(lp, cr, + &ecoalesce->rx_max_coalesced_frames, + &ecoalesce->rx_coalesce_usecs); + + spin_lock_irq(&lp->tx_cr_lock); + cr =3D lp->tx_dma_cr; + spin_unlock_irq(&lp->tx_cr_lock); + axienet_coalesce_params(lp, cr, + &ecoalesce->tx_max_coalesced_frames, + &ecoalesce->tx_coalesce_usecs); return 0; } =20 @@ -2140,15 +2171,12 @@ axienet_ethtools_set_coalesce(struct net_device *nd= ev, return -EINVAL; } =20 - lp->coalesce_count_rx =3D ecoalesce->rx_max_coalesced_frames; - lp->coalesce_usec_rx =3D ecoalesce->rx_coalesce_usecs; - lp->coalesce_count_tx =3D ecoalesce->tx_max_coalesced_frames; - lp->coalesce_usec_tx =3D ecoalesce->tx_coalesce_usecs; - - cr =3D axienet_calc_cr(lp, lp->coalesce_count_rx, lp->coalesce_usec_rx); + cr =3D axienet_calc_cr(lp, ecoalesce->rx_max_coalesced_frames, + ecoalesce->rx_coalesce_usecs); axienet_update_coalesce_rx(lp, cr, ~XAXIDMA_CR_RUNSTOP_MASK); =20 - cr =3D axienet_calc_cr(lp, lp->coalesce_count_tx, lp->coalesce_usec_tx); + cr =3D axienet_calc_cr(lp, ecoalesce->tx_max_coalesced_frames, + ecoalesce->tx_coalesce_usecs); axienet_update_coalesce_tx(lp, cr, ~XAXIDMA_CR_RUNSTOP_MASK); return 0; } @@ -2936,14 +2964,10 @@ static int axienet_probe(struct platform_device *pd= ev) =20 spin_lock_init(&lp->rx_cr_lock); spin_lock_init(&lp->tx_cr_lock); - lp->coalesce_count_rx =3D XAXIDMA_DFT_RX_THRESHOLD; - lp->coalesce_count_tx =3D XAXIDMA_DFT_TX_THRESHOLD; - lp->coalesce_usec_rx =3D XAXIDMA_DFT_RX_USEC; - lp->coalesce_usec_tx =3D XAXIDMA_DFT_TX_USEC; - lp->rx_dma_cr =3D axienet_calc_cr(lp, lp->coalesce_count_rx, - lp->coalesce_usec_rx); - lp->tx_dma_cr =3D axienet_calc_cr(lp, lp->coalesce_count_tx, - lp->coalesce_usec_tx); + lp->rx_dma_cr =3D axienet_calc_cr(lp, XAXIDMA_DFT_RX_THRESHOLD, + XAXIDMA_DFT_RX_USEC); + lp->tx_dma_cr =3D axienet_calc_cr(lp, XAXIDMA_DFT_TX_THRESHOLD, + XAXIDMA_DFT_TX_USEC); =20 ret =3D axienet_mdio_setup(lp); if (ret) --=20 2.35.1.1320.gc452695387.dirty