From nobody Sat Nov 30 12:49:27 2024 Received: from mx1.zhaoxin.com (MX1.ZHAOXIN.COM [210.0.225.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 866601B5EC8 for ; Mon, 9 Sep 2024 11:20:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.0.225.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725880843; cv=none; b=K9EQMP5tNLxkInAs1txoU+F/X9r0Lgc4bbZSR0c+xq2wzorIpxpyURZV+Qx4lvnDBSjZE6fiEodzF4LBQ8niKIwzUwzydB/Qu7JO5F6ivYt6t8G/BjFzHUxLlrcqf3+gCwj9QMi7tZbkUHYywCzvBZvZT2mqoPGY5VzKVWLiShM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725880843; c=relaxed/simple; bh=Y4GHECrA4sX/5ytDMOJCJyu0pijH8ibJXwTLjO/w8ok=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aDGBKgwaiVFhCaGSmPWlK+h4Y9aN+HAl5Jll2VhQAuqErcqLWBg+ekJL6XSFndcDn8VPODISbxZ3YT05mTgOHyTr9lqmEtchPbZ1USRwJMWLsvx8ROyswIkhXU6W03zkoLPOfQg2O/DWaOVjLUiBVamKS/OUDqgaU457DK6ela4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com; spf=pass smtp.mailfrom=zhaoxin.com; arc=none smtp.client-ip=210.0.225.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zhaoxin.com X-ASG-Debug-ID: 1725879764-086e23761311ef60001-xx1T2L Received: from ZXSHMBX2.zhaoxin.com (ZXSHMBX2.zhaoxin.com [10.28.252.164]) by mx1.zhaoxin.com with ESMTP id SAdoT31GxFeKHGxr (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Mon, 09 Sep 2024 19:02:44 +0800 (CST) X-Barracuda-Envelope-From: TonyWWang-oc@zhaoxin.com X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.164 Received: from ZXSHMBX2.zhaoxin.com (10.28.252.164) by ZXSHMBX2.zhaoxin.com (10.28.252.164) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Mon, 9 Sep 2024 19:02:43 +0800 Received: from ZXSHMBX2.zhaoxin.com ([fe80::d4e0:880a:d21:684d]) by ZXSHMBX2.zhaoxin.com ([fe80::d4e0:880a:d21:684d%4]) with mapi id 15.01.2507.039; Mon, 9 Sep 2024 19:02:43 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.164 Received: from tony.zhaoxin.com (10.32.65.165) by ZXBJMBX03.zhaoxin.com (10.29.252.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 9 Sep 2024 18:43:51 +0800 From: Tony W Wang-oc To: , , , , , , , , CC: , , , Lyle Li Subject: [PATCH v1 1/3] x86/mce: Add centaur vendor to support Zhaoxin MCA Date: Mon, 9 Sep 2024 18:43:47 +0800 X-ASG-Orig-Subj: [PATCH v1 1/3] x86/mce: Add centaur vendor to support Zhaoxin MCA Message-ID: <20240909104349.3349-2-TonyWWang-oc@zhaoxin.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240909104349.3349-1-TonyWWang-oc@zhaoxin.com> References: <20240909104349.3349-1-TonyWWang-oc@zhaoxin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Moderation-Data: 9/9/2024 7:02:42 PM X-Barracuda-Connect: ZXSHMBX2.zhaoxin.com[10.28.252.164] X-Barracuda-Start-Time: 1725879764 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.35:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 4507 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.130207 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- Content-Type: text/plain; charset="utf-8" From: Lyle Li Zhaoxin consists of two vendors, X86_VENDOR_ZHAOXIN and X86_VENDOR_CENTAUR, so add the centaur vendor to support Zhaoxin MCA in mce/core.c and mce/intel.c. Signed-off-by: Lyle Li Reviewed-by: Tony W Wang-oc --- arch/x86/kernel/cpu/mce/core.c | 42 ++++++++++++++++----------------- arch/x86/kernel/cpu/mce/intel.c | 3 ++- 2 files changed, 23 insertions(+), 22 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index ad0623b65..b7b98c33a 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -496,6 +496,7 @@ bool mce_usable_address(struct mce *m) =20 case X86_VENDOR_INTEL: case X86_VENDOR_ZHAOXIN: + case X86_VENDOR_CENTAUR: return intel_mce_usable_address(m); =20 default: @@ -513,6 +514,7 @@ bool mce_is_memory_error(struct mce *m) =20 case X86_VENDOR_INTEL: case X86_VENDOR_ZHAOXIN: + case X86_VENDOR_CENTAUR: /* * Intel SDM Volume 3B - 15.9.2 Compound Error Codes * @@ -1247,7 +1249,8 @@ static noinstr bool mce_check_crashing_cpu(void) =20 mcgstatus =3D __rdmsr(MSR_IA32_MCG_STATUS); =20 - if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_ZHAOXIN) { + if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_ZHAOXIN || + boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_CENTAUR) { if (mcgstatus & MCG_STATUS_LMCES) return false; } @@ -1521,7 +1524,8 @@ noinstr void do_machine_check(struct pt_regs *regs) * on Intel, Zhaoxin only. */ if (m.cpuvendor =3D=3D X86_VENDOR_INTEL || - m.cpuvendor =3D=3D X86_VENDOR_ZHAOXIN) + m.cpuvendor =3D=3D X86_VENDOR_ZHAOXIN || + m.cpuvendor =3D=3D X86_VENDOR_CENTAUR) lmce =3D m.mcgstatus & MCG_STATUS_LMCES; =20 /* @@ -1970,6 +1974,18 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_= x86 *c) } } =20 + if (c->x86_vendor =3D=3D X86_VENDOR_CENTAUR) { + /* + * All newer Centaur CPUs support MCE broadcasting. Enable + * synchronization with a one second timeout. + */ + if ((c->x86 =3D=3D 6 && c->x86_model =3D=3D 0xf && c->x86_stepping >=3D = 0xe) || + c->x86 > 6) { + if (cfg->monarch_timeout < 0) + cfg->monarch_timeout =3D USEC_PER_SEC; + } + } + if (cfg->monarch_timeout < 0) cfg->monarch_timeout =3D 0; if (cfg->bootlog !=3D 0) @@ -2012,21 +2028,6 @@ static void __mcheck_cpu_init_early(struct cpuinfo_x= 86 *c) } } =20 -static void mce_centaur_feature_init(struct cpuinfo_x86 *c) -{ - struct mca_config *cfg =3D &mca_cfg; - - /* - * All newer Centaur CPUs support MCE broadcasting. Enable - * synchronization with a one second timeout. - */ - if ((c->x86 =3D=3D 6 && c->x86_model =3D=3D 0xf && c->x86_stepping >=3D 0= xe) || - c->x86 > 6) { - if (cfg->monarch_timeout < 0) - cfg->monarch_timeout =3D USEC_PER_SEC; - } -} - static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) { struct mce_bank *mce_banks =3D this_cpu_ptr(mce_banks_array); @@ -2072,9 +2073,6 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x= 86 *c) break; =20 case X86_VENDOR_CENTAUR: - mce_centaur_feature_init(c); - break; - case X86_VENDOR_ZHAOXIN: mce_zhaoxin_feature_init(c); break; @@ -2092,6 +2090,7 @@ static void __mcheck_cpu_clear_vendor(struct cpuinfo_= x86 *c) break; =20 case X86_VENDOR_ZHAOXIN: + case X86_VENDOR_CENTAUR: mce_zhaoxin_feature_clear(c); break; =20 @@ -2401,7 +2400,8 @@ static void vendor_disable_error_reporting(void) if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL || boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_HYGON || boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD || - boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_ZHAOXIN) + boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_ZHAOXIN || + boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_CENTAUR) return; =20 mce_disable_error_reporting(); diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/inte= l.c index f6103e6bf..b7e67f4f7 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -88,7 +88,8 @@ static int cmci_supported(int *banks) * makes sure none of the backdoors are entered otherwise. */ if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL && - boot_cpu_data.x86_vendor !=3D X86_VENDOR_ZHAOXIN) + boot_cpu_data.x86_vendor !=3D X86_VENDOR_ZHAOXIN && + boot_cpu_data.x86_vendor !=3D X86_VENDOR_CENTAUR) return 0; =20 if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6) --=20 2.34.1 From nobody Sat Nov 30 12:49:27 2024 Received: from mx2.zhaoxin.com (mx2.zhaoxin.com [203.110.167.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4915C18C332 for ; Mon, 9 Sep 2024 11:17:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 9 Sep 2024 18:43:52 +0800 From: Tony W Wang-oc To: , , , , , , , , CC: , , , Lyle Li Subject: [PATCH v1 2/3] x86/mce: Add zhaoxin.c to support Zhaoxin MCA Date: Mon, 9 Sep 2024 18:43:48 +0800 X-ASG-Orig-Subj: [PATCH v1 2/3] x86/mce: Add zhaoxin.c to support Zhaoxin MCA Message-ID: <20240909104349.3349-3-TonyWWang-oc@zhaoxin.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240909104349.3349-1-TonyWWang-oc@zhaoxin.com> References: <20240909104349.3349-1-TonyWWang-oc@zhaoxin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Moderation-Data: 9/9/2024 7:02:47 PM X-Barracuda-Connect: ZXSHMBX2.zhaoxin.com[10.28.252.164] X-Barracuda-Start-Time: 1725879768 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.36:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 4785 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.130206 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- Content-Type: text/plain; charset="utf-8" From: Lyle Li For the sake of code standardization, add zhaoxin.c to override the Zhaoxin MCA code. Signed-off-by: Lyle Li Reviewed-by: Tony W Wang-oc --- arch/x86/Kconfig | 8 +++++++ arch/x86/kernel/cpu/mce/Makefile | 2 +- arch/x86/kernel/cpu/mce/core.c | 28 ------------------------ arch/x86/kernel/cpu/mce/internal.h | 7 ++++++ arch/x86/kernel/cpu/mce/zhaoxin.c | 35 ++++++++++++++++++++++++++++++ 5 files changed, 51 insertions(+), 29 deletions(-) create mode 100644 arch/x86/kernel/cpu/mce/zhaoxin.c diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 1d7122a18..b908cdfb9 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1171,6 +1171,14 @@ config X86_MCE_INTEL Additional support for intel specific MCE features such as the thermal monitor. =20 +config X86_MCE_ZHAOXIN + def_bool y + prompt "Zhaoxin MCE features" + depends on X86_MCE_INTEL + help + Additional support for zhaoxin specific MCE features such as + the corrected machine check interrupt. + config X86_MCE_AMD def_bool y prompt "AMD MCE features" diff --git a/arch/x86/kernel/cpu/mce/Makefile b/arch/x86/kernel/cpu/mce/Mak= efile index 015856abd..2e863e78d 100644 --- a/arch/x86/kernel/cpu/mce/Makefile +++ b/arch/x86/kernel/cpu/mce/Makefile @@ -5,7 +5,7 @@ obj-$(CONFIG_X86_ANCIENT_MCE) +=3D winchip.o p5.o obj-$(CONFIG_X86_MCE_INTEL) +=3D intel.o obj-$(CONFIG_X86_MCE_AMD) +=3D amd.o obj-$(CONFIG_X86_MCE_THRESHOLD) +=3D threshold.o - +obj-$(CONFIG_X86_MCE_ZHAOXIN) +=3D zhaoxin.o mce-inject-y :=3D inject.o obj-$(CONFIG_X86_MCE_INJECT) +=3D mce-inject.o =20 diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index b7b98c33a..b32bfd9f3 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -2028,34 +2028,6 @@ static void __mcheck_cpu_init_early(struct cpuinfo_x= 86 *c) } } =20 -static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) -{ - struct mce_bank *mce_banks =3D this_cpu_ptr(mce_banks_array); - - /* - * These CPUs have MCA bank 8 which reports only one error type called - * SVAD (System View Address Decoder). The reporting of that error is - * controlled by IA32_MC8.CTL.0. - * - * If enabled, prefetching on these CPUs will cause SVAD MCE when - * virtual machines start and result in a system panic. Always disable - * bank 8 SVAD error by default. - */ - if ((c->x86 =3D=3D 7 && c->x86_model =3D=3D 0x1b) || - (c->x86_model =3D=3D 0x19 || c->x86_model =3D=3D 0x1f)) { - if (this_cpu_read(mce_num_banks) > 8) - mce_banks[8].ctl =3D 0; - } - - intel_init_cmci(); - intel_init_lmce(); -} - -static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) -{ - intel_clear_lmce(); -} - static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) { switch (c->x86_vendor) { diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/i= nternal.h index 01f8f0396..e9b06b825 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -334,4 +334,11 @@ static __always_inline u32 mca_msr_reg(int bank, enum = mca_msr reg) } =20 extern void (*mc_poll_banks)(void); +#ifdef CONFIG_X86_MCE_ZHAOXIN +void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c); +void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c); +#else +void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) {} +void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) {} +#endif #endif /* __X86_MCE_INTERNAL_H__ */ diff --git a/arch/x86/kernel/cpu/mce/zhaoxin.c b/arch/x86/kernel/cpu/mce/zh= aoxin.c new file mode 100644 index 000000000..97d12ce0c --- /dev/null +++ b/arch/x86/kernel/cpu/mce/zhaoxin.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Zhaoxin specific MCE features + * Author: Lyle Li + */ +#include +#include "internal.h" + +void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) +{ + struct mce_bank *mce_banks =3D this_cpu_ptr(mce_banks_array); + + /* + * These CPUs have MCA bank 8 which reports only one error type called + * SVAD (System View Address Decoder). The reporting of that error is + * controlled by IA32_MC8.CTL.0. + * + * If enabled, prefetching on these CPUs will cause SVAD MCE when + * virtual machines start and result in a system panic. Always disable + * bank 8 SVAD error by default. + */ + if ((c->x86 =3D=3D 7 && c->x86_model =3D=3D 0x1b) || + (c->x86_model =3D=3D 0x19 || c->x86_model =3D=3D 0x1f)) { + if (this_cpu_read(mce_num_banks) > 8) + mce_banks[8].ctl =3D 0; + } + + intel_init_cmci(); + intel_init_lmce(); +} + +void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) +{ + intel_clear_lmce(); +} --=20 2.34.1 From nobody Sat Nov 30 12:49:27 2024 Received: from mx2.zhaoxin.com (mx2.zhaoxin.com [203.110.167.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E273F1B5309 for ; Mon, 9 Sep 2024 11:02:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.110.167.99 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725879779; cv=none; b=JmCId3vk4TuKdLvGGdvOxPPOB4OZqID4bTJl3l3u67I8rxH3zLJhnXhemn6sPVyM6pJmJkVSnVw8gBgGi/0G3eUs1FR/WEEXMaAB1sXAPfH/JtQVkNRD2v+OwBPMa3/gjTbbpCBtAHFaX2EITXVG3aYPCdXMogfzoL6PTOs0ZDE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725879779; c=relaxed/simple; bh=s9A502O3iKkERZoBN8m5F2WimPPfkpUnmF3aUeXrBek=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=m5DicoKWrXM208Kkfvq7duOZrkCMvPUDJAMvh0iaOV23S0kHOL6E8QUVoALGr2lQ7VDXaQkOFw+zyVprgZdLyLyeKFNG+zt1wx1efUp+qLDUdlVwrJXKSdVfLcGpfkqYeR2JU683rBB0DM0hxlAc0YSVozzdIJrMbGCank31oIY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com; spf=pass smtp.mailfrom=zhaoxin.com; arc=none smtp.client-ip=203.110.167.99 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zhaoxin.com X-ASG-Debug-ID: 1725879772-1eb14e31a6f3b00001-xx1T2L Received: from ZXSHMBX1.zhaoxin.com (ZXSHMBX1.zhaoxin.com [10.28.252.163]) by mx2.zhaoxin.com with ESMTP id n9pBb5GZiHjEdqyT (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Mon, 09 Sep 2024 19:02:52 +0800 (CST) X-Barracuda-Envelope-From: TonyWWang-oc@zhaoxin.com X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.163 Received: from ZXSHMBX2.zhaoxin.com (10.28.252.164) by ZXSHMBX1.zhaoxin.com (10.28.252.163) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Mon, 9 Sep 2024 19:02:51 +0800 Received: from ZXSHMBX2.zhaoxin.com ([fe80::d4e0:880a:d21:684d]) by ZXSHMBX2.zhaoxin.com ([fe80::d4e0:880a:d21:684d%4]) with mapi id 15.01.2507.039; Mon, 9 Sep 2024 19:02:51 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.163 Received: from tony.zhaoxin.com (10.32.65.165) by ZXBJMBX03.zhaoxin.com (10.29.252.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 9 Sep 2024 18:43:54 +0800 From: Tony W Wang-oc To: , , , , , , , , CC: , , , Lyle Li Subject: [PATCH v1 3/3] x86/mce: Add CMCI storm switching support for Zhaoxin Date: Mon, 9 Sep 2024 18:43:49 +0800 X-ASG-Orig-Subj: [PATCH v1 3/3] x86/mce: Add CMCI storm switching support for Zhaoxin Message-ID: <20240909104349.3349-4-TonyWWang-oc@zhaoxin.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240909104349.3349-1-TonyWWang-oc@zhaoxin.com> References: <20240909104349.3349-1-TonyWWang-oc@zhaoxin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Moderation-Data: 9/9/2024 7:02:50 PM X-Barracuda-Connect: ZXSHMBX1.zhaoxin.com[10.28.252.163] X-Barracuda-Start-Time: 1725879772 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.36:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 4285 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.130206 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- Content-Type: text/plain; charset="utf-8" From: Lyle Li Zhaoxin CPUs support CMCI compatible with Intel, because Zhaoxin's UCR error is not reported through CMCI, and in order to be compatible with intel's CMCI code, so add Zhaoxin CMCI storm toggle to support the new CMCI storm switching in mce/intel.c, mce/zhaoxin.c, mce/threshold.c, and mce/internal.h. Signed-off-by: Lyle Li Reviewed-by: Tony W Wang-oc --- arch/x86/kernel/cpu/mce/intel.c | 5 ++--- arch/x86/kernel/cpu/mce/internal.h | 7 ++++++- arch/x86/kernel/cpu/mce/threshold.c | 4 ++++ arch/x86/kernel/cpu/mce/zhaoxin.c | 18 ++++++++++++++++++ 4 files changed, 30 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/inte= l.c index b7e67f4f7..aa75e2848 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -45,7 +45,7 @@ static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned); * cmci_discover_lock protects against parallel discovery attempts * which could race against each other. */ -static DEFINE_RAW_SPINLOCK(cmci_discover_lock); +DEFINE_RAW_SPINLOCK(cmci_discover_lock); =20 /* * On systems that do support CMCI but it's disabled, polling for MCEs can @@ -61,7 +61,7 @@ static DEFINE_SPINLOCK(cmci_poll_lock); * MCi_CTL2 threshold for each bank when there is no storm. * Default value for each bank may have been set by BIOS. */ -static u16 cmci_threshold[MAX_NR_BANKS]; +u16 cmci_threshold[MAX_NR_BANKS]; =20 /* * High threshold to limit CMCI rate during storms. Max supported is @@ -73,7 +73,6 @@ static u16 cmci_threshold[MAX_NR_BANKS]; * to corrected errors, so keeping CMCI enabled means that uncorrected * errors will still be processed in a timely fashion. */ -#define CMCI_STORM_THRESHOLD 32749 =20 static int cmci_supported(int *banks) { diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/i= nternal.h index e9b06b825..8fa1f590f 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -7,7 +7,7 @@ =20 #include #include - +#include enum severity_level { MCE_NO_SEVERITY, MCE_DEFERRED_SEVERITY, @@ -334,11 +334,16 @@ static __always_inline u32 mca_msr_reg(int bank, enum= mca_msr reg) } =20 extern void (*mc_poll_banks)(void); +#define CMCI_STORM_THRESHOLD 32749 +extern raw_spinlock_t cmci_discover_lock; +extern u16 cmci_threshold[MAX_NR_BANKS]; #ifdef CONFIG_X86_MCE_ZHAOXIN void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c); void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c); +void mce_zhaoxin_handle_storm(int bank, bool on); #else void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) {} void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) {} +void mce_zhaoxin_handle_storm(int bank, bool on) {} #endif #endif /* __X86_MCE_INTERNAL_H__ */ diff --git a/arch/x86/kernel/cpu/mce/threshold.c b/arch/x86/kernel/cpu/mce/= threshold.c index 89e31e1e5..200280387 100644 --- a/arch/x86/kernel/cpu/mce/threshold.c +++ b/arch/x86/kernel/cpu/mce/threshold.c @@ -63,6 +63,10 @@ static void mce_handle_storm(unsigned int bank, bool on) case X86_VENDOR_INTEL: mce_intel_handle_storm(bank, on); break; + case X86_VENDOR_ZHAOXIN: + case X86_VENDOR_CENTAUR: + mce_zhaoxin_handle_storm(bank, on); + break; } } =20 diff --git a/arch/x86/kernel/cpu/mce/zhaoxin.c b/arch/x86/kernel/cpu/mce/zh= aoxin.c index 97d12ce0c..38beca449 100644 --- a/arch/x86/kernel/cpu/mce/zhaoxin.c +++ b/arch/x86/kernel/cpu/mce/zhaoxin.c @@ -33,3 +33,21 @@ void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) { intel_clear_lmce(); } + +void mce_zhaoxin_handle_storm(int bank, bool on) +{ + unsigned long flags; + u64 val; + + raw_spin_lock_irqsave(&cmci_discover_lock, flags); + rdmsrl(MSR_IA32_MCx_CTL2(bank), val); + if (on) { + val &=3D ~(MCI_CTL2_CMCI_EN | MCI_CTL2_CMCI_THRESHOLD_MASK); + val |=3D CMCI_STORM_THRESHOLD; + } else { + val &=3D ~MCI_CTL2_CMCI_THRESHOLD_MASK; + val |=3D (MCI_CTL2_CMCI_EN | cmci_threshold[bank]); + } + wrmsrl(MSR_IA32_MCx_CTL2(bank), val); + raw_spin_unlock_irqrestore(&cmci_discover_lock, flags); +} --=20 2.34.1