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However, only the performance cores can execute 32-bit EL0. This results in logical cores that can only execute 32-bit EL0 in high p-states. Trying to support 32-bit EL0 on a CPU that can only execute it in certain states is a bad idea. The A10 family only supports 16KB page size anyway so many AArch32 executables won't run anyways. Pretend that it does not support 32-bit EL0 at all. Signed-off-by: Nick Chan --- arch/arm64/kernel/cpufeature.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 718728a85430..386698f42172 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -3529,6 +3529,31 @@ void __init setup_boot_cpu_features(void) setup_boot_cpu_capabilities(); } =20 +static void __init bad_aarch32_el0_fixup(void) +{ + static const struct midr_range bad_aarch32_el0[] =3D { + MIDR_ALL_VERSIONS(MIDR_APPLE_A10_T2_HURRICANE_ZEPHYR), + MIDR_ALL_VERSIONS(MIDR_APPLE_A10X_HURRICANE_ZEPHYR), + {} + }; + + /* + * The Apple A10 family can only execute 32-bit EL0 when in high + * p-states. Pretend it does not support 32-bit EL0. + */ + if (is_midr_in_range_list(read_cpuid_id(), bad_aarch32_el0)) { + struct arm64_ftr_reg *regp; + + regp =3D get_arm64_ftr_reg(SYS_ID_AA64PFR0_EL1); + if (!regp) + return; + u64 val =3D (regp->sys_val & ~ID_AA64PFR0_EL1_EL0_MASK) + | ID_AA64PFR0_EL1_EL0_IMP; + + update_cpu_ftr_reg(regp, val); + } +} + static void __init setup_system_capabilities(void) { /* @@ -3562,6 +3587,8 @@ static void __init setup_system_capabilities(void) =20 void __init setup_system_features(void) { + bad_aarch32_el0_fixup(); + setup_system_capabilities(); =20 kpti_install_ng_mappings(); --=20 2.46.0