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Signed-off-by: Sayyad Abid --- .../staging/rtl8723bs/include/hal_pwr_seq.h | 46 +++++++++---------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/staging/rtl8723bs/include/hal_pwr_seq.h b/drivers/stag= ing/rtl8723bs/include/hal_pwr_seq.h index 5e43cc89f535..10fef1b3f393 100644 --- a/drivers/staging/rtl8723bs/include/hal_pwr_seq.h +++ b/drivers/staging/rtl8723bs/include/hal_pwr_seq.h @@ -5,26 +5,26 @@ #include "HalPwrSeqCmd.h" /* - Check document WM-20130815-JackieLau-RTL8723B_Power_Architecture v08.vsd - There are 6 HW Power States: - 0: POFF--Power Off - 1: PDN--Power Down - 2: CARDEMU--Card Emulation - 3: ACT--Active Mode - 4: LPS--Low Power State - 5: SUS--Suspend - - The transition from different states are defined below - TRANS_CARDEMU_TO_ACT - TRANS_ACT_TO_CARDEMU - TRANS_CARDEMU_TO_SUS - TRANS_SUS_TO_CARDEMU - TRANS_CARDEMU_TO_PDN - TRANS_ACT_TO_LPS - TRANS_LPS_TO_ACT - - TRANS_END -*/ + * Check document WM-20130815-JackieLau-RTL8723B_Power_Architecture v08.vsd + * There are 6 HW Power States: + * 0: POFF--Power Off + * 1: PDN--Power Down + * 2: CARDEMU--Card Emulation + * 3: ACT--Active Mode + * 4: LPS--Low Power State + * 5: SUS--Suspend + * + * The transition from different states are defined below + * TRANS_CARDEMU_TO_ACT + * TRANS_ACT_TO_CARDEMU + * TRANS_CARDEMU_TO_SUS + * TRANS_SUS_TO_CARDEMU + * TRANS_CARDEMU_TO_PDN + * TRANS_ACT_TO_LPS + * TRANS_LPS_TO_ACT + * + * TRANS_END + */ #define RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS 26 #define RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS 15 #define RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS 15 @@ -101,7 +101,7 @@ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADD= R_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 =3D 0x20 , SOP option to disable = BG/MB*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO= _MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] =3D = 2b'01 enable WL suspend*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR= _MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] =3D 1, enable SW LPS*/ \ - {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_B= ASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] =3D 1 to enable GPIO9 as E= XT WAKEUP*/ \ + {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR= _MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] =3D 1 to enable GPIO9 as EXT WAKE= UP*/ \ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADD= R_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] =3D 1b'1 12H LDO enter sleep m= ode*/ \ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADD= R_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADD= R_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ @@ -112,7 +112,7 @@ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR= _MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down= enable*/ \ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADD= R_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADD= R_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ - {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_B= ASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] =3D 0 to disable GPIO9 as = EXT WAKEUP*/ \ + {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR= _MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] =3D 0 to disable GPIO9 as EXT WAK= EUP*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR= _MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] =3D 2b'01enable WL suspen= d*/\ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADD= R_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] =3D 1b'0 12H LDO enter normal mod= e*/ \ {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR= _MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ @@ -209,7 +209,7 @@ #define RTL8723B_TRANS_END \ /* format */ \ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comm= ents here*/ \ - {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_E= ND, 0, 0}, + {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_E= ND, 0, 0}, extern struct wlan_pwr_cfg rtl8723B_power_on_flow[RTL8723B_TRANS_CARDEMU_T= O_ACT_STEPS+RTL8723B_TRANS_END_STEPS]; -- 2.39.2