From nobody Sun Feb 8 12:30:55 2026 Received: from mail-pj1-f41.google.com (mail-pj1-f41.google.com [209.85.216.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C5E81D5CF8 for ; Fri, 6 Sep 2024 17:15:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725642922; cv=none; b=GJavVk81Sv7Ta8RJW2+eZOQkNXe0QION5qdFkijejNUiJnWyvesgHccs2V6XdsJl8CAnjHq7XlG5kXqT1QcRo8+fiAk6HZ1mJFfF791bhjCnt9pj1GtvhYv8aVJ3k4SYPw5AwPUyHJMoRCHaYyW8WonrXdxl5cYSMJrSzQOqE9s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725642922; c=relaxed/simple; bh=5lOko4x++LaiuMBYnIcL5wTu9SP0pMlfceld25rlKVI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MddKy2kd7ZDPMw1JJFJAkd2X5Zer1PV0sbBqhtkXclennGHFu2il1URNX5eW8Nq4bs9GF1h+AiUq1KUOEJ7au3BCbE0OGUPwgSBXgsIFxtpDex3yFb1Q/3SN94NtKYSMZK7CjOL/VOB4BxWafj4XU1KNaG74XBmeN69IpbR4eWs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=NpXCbxr3; arc=none smtp.client-ip=209.85.216.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="NpXCbxr3" Received: by mail-pj1-f41.google.com with SMTP id 98e67ed59e1d1-2d8b68bddeaso1687346a91.1 for ; Fri, 06 Sep 2024 10:15:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1725642920; x=1726247720; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KTx9T0QsthgtMWPrZGO+mOSHexmLZhoXS2lkiJJqmPw=; b=NpXCbxr3rHPHnMoUSFzFfHvR/ffgPBra3Z4XYyI0uzG+ceBsUO5hDzuKFNP49MMl7O Xu4dkTk6/iFeaejiSpEw3PzrZ/gQFN9Ln8DzcJVlYJeGywiUkbuH3e3RgTJ3R/Hk0Vbv /8fhDNLs8ri5shEELP413m9SC+Y54mVTSHhsIqbjskIC/ZXx8eHb4lbdbHV6pSs6x/Rm pysJnyleNJfkfahMyODHyXK2LMNXbNEswadHYRmSNRFNFS2hLcDouV2ndObRMYg68VIc e9dXxDdVlLpbbX6J/GHMhUvDvT0iJeYxZ08smkj13/EAVAdgo0qxK7WPsjHkm5q+/Crl paFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1725642920; x=1726247720; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KTx9T0QsthgtMWPrZGO+mOSHexmLZhoXS2lkiJJqmPw=; b=Zo4iR0Szmh007xthSjfndl9I7FbJKxbRko/B9B2fnL7CWO3Y1AJxA67GP+di63XFIF L6hDtFgDN8nANPecWJRfvZo5FY89ecp3nKTZs+iOQnLEtW9JCjrD2hy3PUWikj20blfO lQ8v2SKNATFauuFo8x4XWD2TRQLORKWlXN57dsvgl2O2Eg4LjqQRQnLP+PI2Q26D8Ckm 1nHQlX2HczyUbExsp7qJa7BBY5byPgEMSePzXPVff3SqVMBRUJRGybCwVyNWWO+JZBS0 pgI+80qrzkbZBVq1v7EB2Ivf+Vo4SXb1A2n/lQEw5GZurz6PF8c6xHzjI/dbLEUocPeO 5DXw== X-Forwarded-Encrypted: i=1; AJvYcCXa74rbvEjzrX9NaUX+EfYJFWei8+eL1Mj9kN2JiQIqAMvRmCELrEXR8dMCQyHta6cPeGfpHx/KhLlm764=@vger.kernel.org X-Gm-Message-State: AOJu0Yx2JHMWp6HmLaJ7tTOvLQed036L+kTKTJOA/dxHbqroH470zWUX 2aRZnw8lIDavzLj7c4iemLjA2N6n+vk4JKS088PaNx1noHVnPda1 X-Google-Smtp-Source: AGHT+IHFpxzGKP7uZ+bLuIto3ZkdFlTSlbTArs9pk4dQhGEvEew0w4wkM3mOpXuijDV8JQXfBH9a8g== X-Received: by 2002:a17:90a:348e:b0:2d3:d7f4:8ace with SMTP id 98e67ed59e1d1-2dad4dddd7cmr3729535a91.8.1725642920458; Fri, 06 Sep 2024 10:15:20 -0700 (PDT) Received: from localhost.localdomain ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-2dadc10fa99sm1841519a91.39.2024.09.06.10.15.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Sep 2024 10:15:20 -0700 (PDT) From: Nick Chan To: Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: asahi@lists.linux.dev, ~postmarketos/upstreaming@lists.sr.ht, Nick Chan Subject: [PATCH RESEND 1/2] arm64: cputype: Add CPU types for A7-A11, T2 SoCs Date: Sat, 7 Sep 2024 01:13:24 +0800 Message-ID: <20240906171449.324354-2-towinchenmi@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240906171449.324354-1-towinchenmi@gmail.com> References: <20240906171449.324354-1-towinchenmi@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" A10(X), T2 types will be used soon, and the rest are added for documentation purposes. The A9 is made in two different fabs and those have different part numbers, and the TSMC cores are also used in A9X, so it cannot use the usual naming scheme. The A10(X), T2 performance/efficiency core pairs appears as single logical cores to software, so both the performance and efficiency core codenames needs to be included. Signed-off-by: Nick Chan --- arch/arm64/include/asm/cputype.h | 42 +++++++++++++++++++++++--------- 1 file changed, 30 insertions(+), 12 deletions(-) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cput= ype.h index 5a7dfeb8e8eb..f1720158a54f 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -129,18 +129,27 @@ =20 #define HISI_CPU_PART_TSV110 0xD01 =20 -#define APPLE_CPU_PART_M1_ICESTORM 0x022 -#define APPLE_CPU_PART_M1_FIRESTORM 0x023 -#define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024 -#define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025 -#define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028 -#define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029 -#define APPLE_CPU_PART_M2_BLIZZARD 0x032 -#define APPLE_CPU_PART_M2_AVALANCHE 0x033 -#define APPLE_CPU_PART_M2_BLIZZARD_PRO 0x034 -#define APPLE_CPU_PART_M2_AVALANCHE_PRO 0x035 -#define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038 -#define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039 +#define APPLE_CPU_PART_A7_CYCLONE 0x1 +#define APPLE_CPU_PART_A8_TYPHOON 0x2 +#define APPLE_CPU_PART_A8X_TYPHOON 0x3 +#define APPLE_CPU_PART_SAMSUNG_TWISTER 0x4 /* Used in Samsung A9 */ +#define APPLE_CPU_PART_TSMC_TWISTER 0x5 /* Used in TSMC A9 and A9X */ +#define APPLE_CPU_PART_A10_T2_HURRICANE_ZEPHYR 0x6 +#define APPLE_CPU_PART_A10X_HURRICANE_ZEPHYR 0x7 +#define APPLE_CPU_PART_A11_MONSOON 0x8 +#define APPLE_CPU_PART_A11_MISTRAL 0x9 +#define APPLE_CPU_PART_M1_ICESTORM 0x022 +#define APPLE_CPU_PART_M1_FIRESTORM 0x023 +#define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024 +#define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025 +#define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028 +#define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029 +#define APPLE_CPU_PART_M2_BLIZZARD 0x032 +#define APPLE_CPU_PART_M2_AVALANCHE 0x033 +#define APPLE_CPU_PART_M2_BLIZZARD_PRO 0x034 +#define APPLE_CPU_PART_M2_AVALANCHE_PRO 0x035 +#define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038 +#define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039 =20 #define AMPERE_CPU_PART_AMPERE1 0xAC3 #define AMPERE_CPU_PART_AMPERE1A 0xAC4 @@ -200,6 +209,15 @@ #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_P= ART_CARMEL) #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU= _PART_A64FX) #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TS= V110) +#define MIDR_APPLE_A7_CYCLONE MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_= PART_A7_CYCLONE) +#define MIDR_APPLE_A8_TYPHOON MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_= PART_A8_TYPHOON) +#define MIDR_APPLE_A8X_TYPHOON MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU= _PART_A8X_TYPHOON) +#define MIDR_APPLE_SAMSUNG_TWISTER MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE= _CPU_PART_SAMSUNG_TWISTER) +#define MIDR_APPLE_TSMC_TWISTER MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CP= U_PART_TSMC_TWISTER) +#define MIDR_APPLE_A10_T2_HURRICANE_ZEPHYR MIDR_CPU_MODEL(ARM_CPU_IMP_APPL= E, APPLE_CPU_PART_A10_T2_HURRICANE_ZEPHYR) +#define MIDR_APPLE_A10X_HURRICANE_ZEPHYR MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE,= APPLE_CPU_PART_A10X_HURRICANE_ZEPHYR) +#define MIDR_APPLE_A11_MONSOON MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU= _PART_A11_MONSOON) +#define MIDR_APPLE_A11_MISTRAL MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU= _PART_A11_MISTRAL) #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU= _PART_M1_ICESTORM) #define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CP= U_PART_M1_FIRESTORM) #define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE= _CPU_PART_M1_ICESTORM_PRO) --=20 2.46.0 From nobody Sun Feb 8 12:30:55 2026 Received: from mail-pj1-f45.google.com (mail-pj1-f45.google.com [209.85.216.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB3DE1D47CE for ; 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Fri, 06 Sep 2024 10:15:28 -0700 (PDT) Received: from localhost.localdomain ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-2dadc10fa99sm1841519a91.39.2024.09.06.10.15.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Sep 2024 10:15:27 -0700 (PDT) From: Nick Chan To: Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: asahi@lists.linux.dev, ~postmarketos/upstreaming@lists.sr.ht, Nick Chan Subject: [PATCH RESEND 2/2] arm64: cpufeature: Pretend that Apple A10(X), T2 does not support 32-bit EL0 Date: Sat, 7 Sep 2024 01:13:26 +0800 Message-ID: <20240906171449.324354-4-towinchenmi@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240906171449.324354-1-towinchenmi@gmail.com> References: <20240906171449.324354-1-towinchenmi@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Apple A10(X), T2 consists of logical cores that can switch between P-mode and E-mode based on the frequency. However, only P-mode supported 32-bit EL0. Trying to support 32-bit EL0 on a CPU that can only execute it in certain states is a bad idea. The A10(X), T2 only supports 16KB page size anyway so many AArch32 executables won't run anyways. Pretend that it does not support 32-bit EL0 at all. Signed-off-by: Nick Chan --- arch/arm64/kernel/cpufeature.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 718728a85430..458bcbc4f328 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -3529,6 +3529,29 @@ void __init setup_boot_cpu_features(void) setup_boot_cpu_capabilities(); } =20 +static void __init bad_aarch32_el0_fixup(void) +{ +#ifdef CONFIG_ARCH_APPLE + static const struct midr_range bad_aarch32_el0[] =3D { + MIDR_ALL_VERSIONS(MIDR_APPLE_A10_T2_HURRICANE_ZEPHYR), + MIDR_ALL_VERSIONS(MIDR_APPLE_A10X_HURRICANE_ZEPHYR), + {} + }; + + if (is_midr_in_range_list(read_cpuid_id(), bad_aarch32_el0)) { + struct arm64_ftr_reg *regp; + + regp =3D get_arm64_ftr_reg(SYS_ID_AA64PFR0_EL1); + if (!regp) + return; + u64 val =3D (regp->sys_val & ~ID_AA64PFR0_EL1_EL0_MASK) + | ID_AA64PFR0_EL1_EL0_IMP; + + update_cpu_ftr_reg(regp, val); + } +#endif +} + static void __init setup_system_capabilities(void) { /* @@ -3562,6 +3585,8 @@ static void __init setup_system_capabilities(void) =20 void __init setup_system_features(void) { + bad_aarch32_el0_fixup(); + setup_system_capabilities(); =20 kpti_install_ng_mappings(); --=20 2.46.0