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Signed-off-by: Gowthami Thiagarajan --- drivers/perf/marvell_cn10k_ddr_pmu.c | 106 +++++++++++++++++++++------ 1 file changed, 83 insertions(+), 23 deletions(-) diff --git a/drivers/perf/marvell_cn10k_ddr_pmu.c b/drivers/perf/marvell_cn= 10k_ddr_pmu.c index e33d383aa6d2..648ad3a740bf 100644 --- a/drivers/perf/marvell_cn10k_ddr_pmu.c +++ b/drivers/perf/marvell_cn10k_ddr_pmu.c @@ -136,6 +136,16 @@ struct cn10k_ddr_pmu { struct hlist_node node; }; =20 +struct ddr_pmu_ops { + void (*enable_read_freerun_counter)(struct cn10k_ddr_pmu *pmu, + bool enable); + void (*enable_write_freerun_counter)(struct cn10k_ddr_pmu *pmu, + bool enable); + void (*clear_read_freerun_counter)(struct cn10k_ddr_pmu *pmu); + void (*clear_write_freerun_counter)(struct cn10k_ddr_pmu *pmu); + void (*pmu_overflow_handler)(struct cn10k_ddr_pmu *pmu, int evt_idx); +}; + #define to_cn10k_ddr_pmu(p) container_of(p, struct cn10k_ddr_pmu, pmu) =20 struct ddr_pmu_platform_data { @@ -152,6 +162,7 @@ struct ddr_pmu_platform_data { u64 ddrc_perf_cnt_freerun_clr; u64 ddrc_perf_cnt_value_wr_op; u64 ddrc_perf_cnt_value_rd_op; + const struct ddr_pmu_ops *ops; }; =20 static ssize_t cn10k_ddr_pmu_event_show(struct device *dev, @@ -375,6 +386,7 @@ static void cn10k_ddr_perf_counter_enable(struct cn10k_= ddr_pmu *pmu, int counter, bool enable) { const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; + const struct ddr_pmu_ops *ops =3D p_data->ops; u32 reg; u64 val; =20 @@ -394,21 +406,10 @@ static void cn10k_ddr_perf_counter_enable(struct cn10= k_ddr_pmu *pmu, =20 writeq_relaxed(val, pmu->base + reg); } else { - val =3D readq_relaxed(pmu->base + - p_data->ddrc_perf_cnt_freerun_en); - if (enable) { - if (counter =3D=3D DDRC_PERF_READ_COUNTER_IDX) - val |=3D DDRC_PERF_FREERUN_READ_EN; - else - val |=3D DDRC_PERF_FREERUN_WRITE_EN; - } else { - if (counter =3D=3D DDRC_PERF_READ_COUNTER_IDX) - val &=3D ~DDRC_PERF_FREERUN_READ_EN; - else - val &=3D ~DDRC_PERF_FREERUN_WRITE_EN; - } - writeq_relaxed(val, pmu->base + - p_data->ddrc_perf_cnt_freerun_en); + if (counter =3D=3D DDRC_PERF_READ_COUNTER_IDX) + ops->enable_read_freerun_counter(pmu, enable); + else + ops->enable_write_freerun_counter(pmu, enable); } } =20 @@ -464,6 +465,7 @@ static int cn10k_ddr_perf_event_add(struct perf_event *= event, int flags) { struct cn10k_ddr_pmu *pmu =3D to_cn10k_ddr_pmu(event->pmu); const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; + const struct ddr_pmu_ops *ops =3D p_data->ops; struct hw_perf_event *hwc =3D &event->hw; u8 config =3D event->attr.config; int counter, ret; @@ -492,12 +494,9 @@ static int cn10k_ddr_perf_event_add(struct perf_event = *event, int flags) } else { /* fixed event counter, clear counter value */ if (counter =3D=3D DDRC_PERF_READ_COUNTER_IDX) - val =3D DDRC_FREERUN_READ_CNT_CLR; + ops->clear_read_freerun_counter(pmu); else - val =3D DDRC_FREERUN_WRITE_CNT_CLR; - - writeq_relaxed(val, pmu->base + - p_data->ddrc_perf_cnt_freerun_ctrl); + ops->clear_write_freerun_counter(pmu); } =20 hwc->state |=3D PERF_HES_STOPPED; @@ -579,9 +578,63 @@ static void cn10k_ddr_perf_event_update_all(struct cn1= 0k_ddr_pmu *pmu) } } =20 +static void ddr_pmu_enable_read_freerun(struct cn10k_ddr_pmu *pmu, bool en= able) +{ + const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; + u64 val; + + val =3D readq_relaxed(pmu->base + p_data->ddrc_perf_cnt_freerun_en); + if (enable) + val |=3D DDRC_PERF_FREERUN_READ_EN; + else + val &=3D ~DDRC_PERF_FREERUN_READ_EN; + + writeq_relaxed(val, pmu->base + p_data->ddrc_perf_cnt_freerun_en); +} + +static void ddr_pmu_enable_write_freerun(struct cn10k_ddr_pmu *pmu, bool e= nable) +{ + const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; + u64 val; + + val =3D readq_relaxed(pmu->base + p_data->ddrc_perf_cnt_freerun_en); + if (enable) + val |=3D DDRC_PERF_FREERUN_WRITE_EN; + else + val &=3D ~DDRC_PERF_FREERUN_WRITE_EN; + + writeq_relaxed(val, pmu->base + p_data->ddrc_perf_cnt_freerun_en); +} + +static void ddr_pmu_read_clear_freerun(struct cn10k_ddr_pmu *pmu) +{ + const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; + u64 val; + + val =3D DDRC_FREERUN_READ_CNT_CLR; + writeq_relaxed(val, pmu->base + p_data->ddrc_perf_cnt_freerun_ctrl); +} + +static void ddr_pmu_write_clear_freerun(struct cn10k_ddr_pmu *pmu) +{ + const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; + u64 val; + + val =3D DDRC_FREERUN_WRITE_CNT_CLR; + writeq_relaxed(val, pmu->base + p_data->ddrc_perf_cnt_freerun_ctrl); +} + +static void ddr_pmu_overflow_hander(struct cn10k_ddr_pmu *pmu, int evt_idx) +{ + cn10k_ddr_perf_event_update_all(pmu); + cn10k_ddr_perf_pmu_disable(&pmu->pmu); + cn10k_ddr_perf_pmu_enable(&pmu->pmu); +} + static irqreturn_t cn10k_ddr_pmu_overflow_handler(struct cn10k_ddr_pmu *pm= u) { const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; + const struct ddr_pmu_ops *ops =3D p_data->ops; struct perf_event *event; struct hw_perf_event *hwc; u64 prev_count, new_count; @@ -621,9 +674,7 @@ static irqreturn_t cn10k_ddr_pmu_overflow_handler(struc= t cn10k_ddr_pmu *pmu) value =3D cn10k_ddr_perf_read_counter(pmu, i); if (value =3D=3D p_data->counter_max_val) { pr_info("Counter-(%d) reached max value\n", i); - cn10k_ddr_perf_event_update_all(pmu); - cn10k_ddr_perf_pmu_disable(&pmu->pmu); - cn10k_ddr_perf_pmu_enable(&pmu->pmu); + ops->pmu_overflow_handler(pmu, i); } } =20 @@ -662,6 +713,14 @@ static int cn10k_ddr_pmu_offline_cpu(unsigned int cpu,= struct hlist_node *node) return 0; } =20 +static const struct ddr_pmu_ops ddr_pmu_ops =3D { + .enable_read_freerun_counter =3D ddr_pmu_enable_read_freerun, + .enable_write_freerun_counter =3D ddr_pmu_enable_write_freerun, + .clear_read_freerun_counter =3D ddr_pmu_read_clear_freerun, + .clear_write_freerun_counter =3D ddr_pmu_write_clear_freerun, + .pmu_overflow_handler =3D ddr_pmu_overflow_hander, +}; + static const struct ddr_pmu_platform_data cn10k_ddr_pmu_pdata =3D { .counter_overflow_val =3D BIT_ULL(48), .counter_max_val =3D GENMASK_ULL(48, 0), @@ -676,6 +735,7 @@ static const struct ddr_pmu_platform_data cn10k_ddr_pmu= _pdata =3D { .ddrc_perf_cnt_freerun_clr =3D 0, .ddrc_perf_cnt_value_wr_op =3D CN10K_DDRC_PERF_CNT_VALUE_WR_OP, .ddrc_perf_cnt_value_rd_op =3D CN10K_DDRC_PERF_CNT_VALUE_RD_OP, + .ops =3D &ddr_pmu_ops, }; =20 static int cn10k_ddr_perf_probe(struct platform_device *pdev) --=20 2.25.1