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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 10:11:11.9292 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 27ae8d96-c00f-4dac-41eb-08dcccc9e741 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6892 Content-Type: text/plain; charset="utf-8" After commit ("x86/cpu/topology: Add support for the AMD 0x80000026 leaf"), on AMD processors that support extended CPUID leaf 0x80000026, the topology_die_cpumask() and topology_logical_die_id() macros, no longer return the package cpumask and package id, instead they return the CCD (Core Complex Die) mask and id respectively. This leads to the energy-pkg event scope to be modified to CCD instead of package. So, change the PMU scope for AMD and Hygon back to package. On a 12 CCD 1 Package AMD Zen4 Genoa machine: Before: $ cat /sys/devices/power/cpumask 0,8,16,24,32,40,48,56,64,72,80,88. The expected cpumask here is supposed to be just "0", as it is a package scope event, only one CPU will be collecting the event for all the CPUs in the package. After: $ cat /sys/devices/power/cpumask 0 Signed-off-by: Dhananjay Ugwekar Reviewed-by: Kan Liang --- v2 Link: https://lore.kernel.org/all/20240730044917.4680-2-Dhananjay.Ugweka= r@amd.com/ Changes from v2: * Rebase on top of kan.liang's PMU scope patchset [1] * Set pmu.scope variable to package for AMD/Hygon CPUs tip/master + PMU scope patchset [1] to be taken as base for testing this pa= tch.=20 [1]: https://lore.kernel.org/all/20240802151643.1691631-1-kan.liang@linux.i= ntel.com/ --- arch/x86/events/rapl.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index b70ad880c5bc..0c57dd5aa767 100644 --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -139,9 +139,32 @@ static unsigned int rapl_cntr_mask; static u64 rapl_timer_ms; static struct perf_msr *rapl_msrs; =20 +/* + * RAPL Package energy counter scope: + * 1. AMD/HYGON platforms have a per-PKG package energy counter + * 2. For Intel platforms + * 2.1. CLX-AP is multi-die and its RAPL MSRs are die-scope + * 2.2. Other Intel platforms are single die systems so the scope can be + * considered as either pkg-scope or die-scope, and we are considering + * them as die-scope. + */ +#define rapl_pmu_is_pkg_scope() \ + (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD || \ + boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_HYGON) + +/* + * Helper function to get the correct topology id according to the + * RAPL PMU scope. + */ +static inline unsigned int get_rapl_pmu_idx(int cpu) +{ + return rapl_pmu_is_pkg_scope() ? topology_logical_package_id(cpu) : + topology_logical_die_id(cpu); +} + static inline struct rapl_pmu *cpu_to_rapl_pmu(unsigned int cpu) { - unsigned int rapl_pmu_idx =3D topology_logical_die_id(cpu); + unsigned int rapl_pmu_idx =3D get_rapl_pmu_idx(cpu); =20 /* * The unsigned check also catches the '-1' return value for non @@ -617,7 +640,7 @@ static void __init init_rapl_pmu(void) pmu->timer_interval =3D ms_to_ktime(rapl_timer_ms); rapl_hrtimer_init(pmu); =20 - rapl_pmus->pmus[topology_logical_die_id(cpu)] =3D pmu; + rapl_pmus->pmus[get_rapl_pmu_idx(cpu)] =3D pmu; } =20 cpus_read_unlock(); @@ -646,6 +669,12 @@ static int __init init_rapl_pmus(void) rapl_pmus->pmu.module =3D THIS_MODULE; rapl_pmus->pmu.scope =3D PERF_PMU_SCOPE_DIE; rapl_pmus->pmu.capabilities =3D PERF_PMU_CAP_NO_EXCLUDE; + + if (rapl_pmu_is_pkg_scope()) { + rapl_pmus->nr_rapl_pmu =3D topology_max_packages(); + rapl_pmus->pmu.scope =3D PERF_PMU_SCOPE_PKG; + } + return 0; } =20 --=20 2.34.1