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[75.72.166.104]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-39f3afc4ff6sm34556175ab.37.2024.09.03.19.33.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2024 19:33:39 -0700 (PDT) From: Adam Ford To: linux-phy@lists.infradead.org Cc: dominique.martinet@atmark-techno.com, linux-imx@nxp.com, festevam@gmail.com, frieder.schrempf@kontron.de, aford@beaconembedded.com, Sandor.yu@nxp.com, Adam Ford , Vinod Koul , Kishon Vijay Abraham I , Marco Felsch , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Lucas Stach , linux-kernel@vger.kernel.org Subject: [PATCH V5 4/5] phy: freescale: fsl-samsung-hdmi: Use closest divider Date: Tue, 3 Sep 2024 21:32:43 -0500 Message-ID: <20240904023310.163371-5-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240904023310.163371-1-aford173@gmail.com> References: <20240904023310.163371-1-aford173@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, if the clock values cannot be set to the exact rate, the round_rate and set_rate functions use the closest value found in the look-up-table. In preparation of removing values from the LUT that can be calculated evenly with the integer calculator, it's necessary to ensure to check both the look-up-table and the integer divider clock values to get the closest values to the requested value. It does this by measuring the difference between the requested clock value and the closest value in both integer divider calucator and the fractional clock look-up-table. Which ever has the smallest difference between them is returned as the cloesest rate. Signed-off-by: Adam Ford Signed-off-by: Dominique Martinet --- V5: No Change V4: New to series --- drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 40 +++++++++++++++----- 1 file changed, 31 insertions(+), 9 deletions(-) diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/fre= escale/phy-fsl-samsung-hdmi.c index 8f2c0082aa12..56b08e684179 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -550,7 +550,7 @@ static unsigned long phy_clk_recalc_rate(struct clk_hw = *hw, static long phy_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { - u32 int_div_clk; + u32 int_div_clk, delta_int, delta_frac; int i; u16 m; u8 p, s; @@ -563,6 +563,7 @@ static long phy_clk_round_rate(struct clk_hw *hw, for (i =3D ARRAY_SIZE(phy_pll_cfg) - 1; i >=3D 0; i--) if (phy_pll_cfg[i].pixclk <=3D rate) break; + /* If the rate is an exact match, return it now */ if (rate =3D=3D phy_pll_cfg[i].pixclk) return phy_pll_cfg[i].pixclk; @@ -579,15 +580,21 @@ static long phy_clk_round_rate(struct clk_hw *hw, if (int_div_clk =3D=3D rate) return int_div_clk; =20 - /* Fall back to the closest value in the LUT */ - return phy_pll_cfg[i].pixclk; + /* Calculate the differences and use the closest one */ + delta_frac =3D (rate - phy_pll_cfg[i].pixclk); + delta_int =3D (rate - int_div_clk); + + if (delta_int < delta_frac) + return int_div_clk; + else + return phy_pll_cfg[i].pixclk; } =20 static int phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct fsl_samsung_hdmi_phy *phy =3D to_fsl_samsung_hdmi_phy(hw); - u32 int_div_clk; + u32 int_div_clk, delta_int, delta_frac; int i; u16 m; u8 p, s; @@ -602,19 +609,34 @@ static int phy_clk_set_rate(struct clk_hw *hw, calculated_phy_pll_cfg.pll_div_regs[2] =3D FIELD_PREP(REG03_PMS_S_MASK, = s-1); /* pll_div_regs 3-6 are fixed and pre-defined already */ phy->cur_cfg =3D &calculated_phy_pll_cfg; + goto done; } else { /* Otherwise, search the LUT */ - dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: using fractional divider\n"); - for (i =3D ARRAY_SIZE(phy_pll_cfg) - 1; i >=3D 0; i--) - if (phy_pll_cfg[i].pixclk <=3D rate) + for (i =3D ARRAY_SIZE(phy_pll_cfg) - 1; i >=3D 0; i--) { + if (phy_pll_cfg[i].pixclk =3D=3D rate) { + dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: using fractional divider\n"); + phy->cur_cfg =3D &phy_pll_cfg[i]; + goto done; + } + + if (phy_pll_cfg[i].pixclk < rate) break; + } =20 if (i < 0) return -EINVAL; - - phy->cur_cfg =3D &phy_pll_cfg[i]; } =20 + /* Calculate the differences for each clock against the requested value */ + delta_frac =3D (rate - phy_pll_cfg[i].pixclk); + delta_int =3D (rate - int_div_clk); + + /* Use the value closest to the desired */ + if (delta_int < delta_frac) + phy->cur_cfg =3D &calculated_phy_pll_cfg; + else + phy->cur_cfg =3D &phy_pll_cfg[i]; +done: return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); } =20 --=20 2.43.0