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[75.72.166.104]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-39f3afc4ff6sm34556175ab.37.2024.09.03.19.33.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2024 19:33:24 -0700 (PDT) From: Adam Ford To: linux-phy@lists.infradead.org Cc: dominique.martinet@atmark-techno.com, linux-imx@nxp.com, festevam@gmail.com, frieder.schrempf@kontron.de, aford@beaconembedded.com, Sandor.yu@nxp.com, Adam Ford , Marco Felsch , Vinod Koul , Kishon Vijay Abraham I , Lucas Stach , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , linux-kernel@vger.kernel.org Subject: [PATCH V5 1/5] phy: freescale: fsl-samsung-hdmi: Replace register defines with macro Date: Tue, 3 Sep 2024 21:32:40 -0500 Message-ID: <20240904023310.163371-2-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240904023310.163371-1-aford173@gmail.com> References: <20240904023310.163371-1-aford173@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There are 47 registers defined as PHY_REG_xx were xx goes from 00 to 47. Simplify this by replacing them all with a macro which is passed the register number to return the proper register offset. Signed-off-by: Adam Ford Reviewed-by: Marco Felsch Reviewed-by: Frieder Schrempf Tested-by: Frieder Schrempf --- V5: Restore comment about REG33. Add spacing between the REG entries to easier readability --- drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 133 ++++++------------- 1 file changed, 43 insertions(+), 90 deletions(-) diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/fre= escale/phy-fsl-samsung-hdmi.c index 9048cdc760c2..acea7008aefc 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -14,76 +14,29 @@ #include #include =20 -#define PHY_REG_00 0x00 -#define PHY_REG_01 0x04 -#define PHY_REG_02 0x08 -#define PHY_REG_08 0x20 -#define PHY_REG_09 0x24 -#define PHY_REG_10 0x28 -#define PHY_REG_11 0x2c - -#define PHY_REG_12 0x30 -#define REG12_CK_DIV_MASK GENMASK(5, 4) - -#define PHY_REG_13 0x34 -#define REG13_TG_CODE_LOW_MASK GENMASK(7, 0) - -#define PHY_REG_14 0x38 -#define REG14_TOL_MASK GENMASK(7, 4) -#define REG14_RP_CODE_MASK GENMASK(3, 1) -#define REG14_TG_CODE_HIGH_MASK GENMASK(0, 0) - -#define PHY_REG_15 0x3c -#define PHY_REG_16 0x40 -#define PHY_REG_17 0x44 -#define PHY_REG_18 0x48 -#define PHY_REG_19 0x4c -#define PHY_REG_20 0x50 - -#define PHY_REG_21 0x54 -#define REG21_SEL_TX_CK_INV BIT(7) -#define REG21_PMS_S_MASK GENMASK(3, 0) - -#define PHY_REG_22 0x58 -#define PHY_REG_23 0x5c -#define PHY_REG_24 0x60 -#define PHY_REG_25 0x64 -#define PHY_REG_26 0x68 -#define PHY_REG_27 0x6c -#define PHY_REG_28 0x70 -#define PHY_REG_29 0x74 -#define PHY_REG_30 0x78 -#define PHY_REG_31 0x7c -#define PHY_REG_32 0x80 +#define PHY_REG(reg) (reg * 4) =20 +#define REG12_CK_DIV_MASK GENMASK(5, 4) + +#define REG13_TG_CODE_LOW_MASK GENMASK(7, 0) + +#define REG14_TOL_MASK GENMASK(7, 4) +#define REG14_RP_CODE_MASK GENMASK(3, 1) +#define REG14_TG_CODE_HIGH_MASK GENMASK(0, 0) + +#define REG21_SEL_TX_CK_INV BIT(7) +#define REG21_PMS_S_MASK GENMASK(3, 0) /* * REG33 does not match the ref manual. According to Sandor Yu from NXP, * "There is a doc issue on the i.MX8MP latest RM" * REG33 is being used per guidance from Sandor */ +#define REG33_MODE_SET_DONE BIT(7) +#define REG33_FIX_DA BIT(1) =20 -#define PHY_REG_33 0x84 -#define REG33_MODE_SET_DONE BIT(7) -#define REG33_FIX_DA BIT(1) - -#define PHY_REG_34 0x88 -#define REG34_PHY_READY BIT(7) -#define REG34_PLL_LOCK BIT(6) -#define REG34_PHY_CLK_READY BIT(5) - -#define PHY_REG_35 0x8c -#define PHY_REG_36 0x90 -#define PHY_REG_37 0x94 -#define PHY_REG_38 0x98 -#define PHY_REG_39 0x9c -#define PHY_REG_40 0xa0 -#define PHY_REG_41 0xa4 -#define PHY_REG_42 0xa8 -#define PHY_REG_43 0xac -#define PHY_REG_44 0xb0 -#define PHY_REG_45 0xb4 -#define PHY_REG_46 0xb8 -#define PHY_REG_47 0xbc +#define REG34_PHY_READY BIT(7) +#define REG34_PLL_LOCK BIT(6) +#define REG34_PHY_CLK_READY BIT(5) =20 #define PHY_PLL_DIV_REGS_NUM 6 =20 @@ -369,29 +322,29 @@ struct reg_settings { }; =20 static const struct reg_settings common_phy_cfg[] =3D { - { PHY_REG_00, 0x00 }, { PHY_REG_01, 0xd1 }, - { PHY_REG_08, 0x4f }, { PHY_REG_09, 0x30 }, - { PHY_REG_10, 0x33 }, { PHY_REG_11, 0x65 }, + { PHY_REG(0), 0x00 }, { PHY_REG(1), 0xd1 }, + { PHY_REG(8), 0x4f }, { PHY_REG(9), 0x30 }, + { PHY_REG(10), 0x33 }, { PHY_REG(11), 0x65 }, /* REG12 pixclk specific */ /* REG13 pixclk specific */ /* REG14 pixclk specific */ - { PHY_REG_15, 0x80 }, { PHY_REG_16, 0x6c }, - { PHY_REG_17, 0xf2 }, { PHY_REG_18, 0x67 }, - { PHY_REG_19, 0x00 }, { PHY_REG_20, 0x10 }, + { PHY_REG(15), 0x80 }, { PHY_REG(16), 0x6c }, + { PHY_REG(17), 0xf2 }, { PHY_REG(18), 0x67 }, + { PHY_REG(19), 0x00 }, { PHY_REG(20), 0x10 }, /* REG21 pixclk specific */ - { PHY_REG_22, 0x30 }, { PHY_REG_23, 0x32 }, - { PHY_REG_24, 0x60 }, { PHY_REG_25, 0x8f }, - { PHY_REG_26, 0x00 }, { PHY_REG_27, 0x00 }, - { PHY_REG_28, 0x08 }, { PHY_REG_29, 0x00 }, - { PHY_REG_30, 0x00 }, { PHY_REG_31, 0x00 }, - { PHY_REG_32, 0x00 }, { PHY_REG_33, 0x80 }, - { PHY_REG_34, 0x00 }, { PHY_REG_35, 0x00 }, - { PHY_REG_36, 0x00 }, { PHY_REG_37, 0x00 }, - { PHY_REG_38, 0x00 }, { PHY_REG_39, 0x00 }, - { PHY_REG_40, 0x00 }, { PHY_REG_41, 0xe0 }, - { PHY_REG_42, 0x83 }, { PHY_REG_43, 0x0f }, - { PHY_REG_44, 0x3E }, { PHY_REG_45, 0xf8 }, - { PHY_REG_46, 0x00 }, { PHY_REG_47, 0x00 } + { PHY_REG(22), 0x30 }, { PHY_REG(23), 0x32 }, + { PHY_REG(24), 0x60 }, { PHY_REG(25), 0x8f }, + { PHY_REG(26), 0x00 }, { PHY_REG(27), 0x00 }, + { PHY_REG(28), 0x08 }, { PHY_REG(29), 0x00 }, + { PHY_REG(30), 0x00 }, { PHY_REG(31), 0x00 }, + { PHY_REG(32), 0x00 }, { PHY_REG(33), 0x80 }, + { PHY_REG(34), 0x00 }, { PHY_REG(35), 0x00 }, + { PHY_REG(36), 0x00 }, { PHY_REG(37), 0x00 }, + { PHY_REG(38), 0x00 }, { PHY_REG(39), 0x00 }, + { PHY_REG(40), 0x00 }, { PHY_REG(41), 0xe0 }, + { PHY_REG(42), 0x83 }, { PHY_REG(43), 0x0f }, + { PHY_REG(44), 0x3E }, { PHY_REG(45), 0xf8 }, + { PHY_REG(46), 0x00 }, { PHY_REG(47), 0x00 } }; =20 struct fsl_samsung_hdmi_phy { @@ -442,7 +395,7 @@ fsl_samsung_hdmi_phy_configure_pixclk(struct fsl_samsun= g_hdmi_phy *phy, } =20 writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, div), - phy->regs + PHY_REG_21); + phy->regs + PHY_REG(21)); } =20 static void @@ -469,7 +422,7 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_= samsung_hdmi_phy *phy, break; } =20 - writeb(FIELD_PREP(REG12_CK_DIV_MASK, ilog2(div)), phy->regs + PHY_REG_12); + writeb(FIELD_PREP(REG12_CK_DIV_MASK, ilog2(div)), phy->regs + PHY_REG(12)= ); =20 /* * Calculation for the frequency lock detector target code (fld_tg_code) @@ -489,11 +442,11 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fs= l_samsung_hdmi_phy *phy, =20 /* FLD_TOL and FLD_RP_CODE taken from downstream driver */ writeb(FIELD_PREP(REG13_TG_CODE_LOW_MASK, fld_tg_code), - phy->regs + PHY_REG_13); + phy->regs + PHY_REG(13)); writeb(FIELD_PREP(REG14_TOL_MASK, 2) | FIELD_PREP(REG14_RP_CODE_MASK, 2) | FIELD_PREP(REG14_TG_CODE_HIGH_MASK, fld_tg_code >> 8), - phy->regs + PHY_REG_14); + phy->regs + PHY_REG(14)); } =20 static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, @@ -503,7 +456,7 @@ static int fsl_samsung_hdmi_phy_configure(struct fsl_sa= msung_hdmi_phy *phy, u8 val; =20 /* HDMI PHY init */ - writeb(REG33_FIX_DA, phy->regs + PHY_REG_33); + writeb(REG33_FIX_DA, phy->regs + PHY_REG(33)); =20 /* common PHY registers */ for (i =3D 0; i < ARRAY_SIZE(common_phy_cfg); i++) @@ -511,14 +464,14 @@ static int fsl_samsung_hdmi_phy_configure(struct fsl_= samsung_hdmi_phy *phy, =20 /* set individual PLL registers PHY_REG2 ... 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[75.72.166.104]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-39f3afc4ff6sm34556175ab.37.2024.09.03.19.33.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2024 19:33:29 -0700 (PDT) From: Adam Ford To: linux-phy@lists.infradead.org Cc: dominique.martinet@atmark-techno.com, linux-imx@nxp.com, festevam@gmail.com, frieder.schrempf@kontron.de, aford@beaconembedded.com, Sandor.yu@nxp.com, Adam Ford , Marco Felsch , Vinod Koul , Kishon Vijay Abraham I , Lucas Stach , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , linux-kernel@vger.kernel.org Subject: [PATCH V5 2/5] phy: freescale: fsl-samsung-hdmi: Simplify REG21_PMS_S_MASK lookup Date: Tue, 3 Sep 2024 21:32:41 -0500 Message-ID: <20240904023310.163371-3-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240904023310.163371-1-aford173@gmail.com> References: <20240904023310.163371-1-aford173@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The value of 'S' is writen to two places, PHY_REG3[7:4] and PHY_REG21[3:0]. There is a lookup table which contains the value of PHY_REG3. Rather than using a switch statement based on the pixel clock to search for the value of 'S' again, just shift the contents of PHY_REG3[7:4] >> 4 and place the value in PHY_REG21[3:0]. Doing this can eliminate an entire function. Signed-off-by: Adam Ford Reviewed-by: Marco Felsch Reviewed-by: Frieder Schrempf Tested-by: Frieder Schrempf --- V5: No Change --- drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 39 ++------------------ 1 file changed, 4 insertions(+), 35 deletions(-) diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/fre= escale/phy-fsl-samsung-hdmi.c index acea7008aefc..4f6874226f9a 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -364,40 +364,6 @@ to_fsl_samsung_hdmi_phy(struct clk_hw *hw) return container_of(hw, struct fsl_samsung_hdmi_phy, hw); } =20 -static void -fsl_samsung_hdmi_phy_configure_pixclk(struct fsl_samsung_hdmi_phy *phy, - const struct phy_config *cfg) -{ - u8 div =3D 0x1; - - switch (cfg->pixclk) { - case 22250000 ... 33750000: - div =3D 0xf; - break; - case 35000000 ... 40000000: - div =3D 0xb; - break; - case 43200000 ... 47500000: - div =3D 0x9; - break; - case 50349650 ... 63500000: - div =3D 0x7; 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[75.72.166.104]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-39f3afc4ff6sm34556175ab.37.2024.09.03.19.33.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2024 19:33:34 -0700 (PDT) From: Adam Ford To: linux-phy@lists.infradead.org Cc: dominique.martinet@atmark-techno.com, linux-imx@nxp.com, festevam@gmail.com, frieder.schrempf@kontron.de, aford@beaconembedded.com, Sandor.yu@nxp.com, Adam Ford , Vinod Koul , Kishon Vijay Abraham I , Marco Felsch , Lucas Stach , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , linux-kernel@vger.kernel.org Subject: [PATCH V5 3/5] phy: freescale: fsl-samsung-hdmi: Support dynamic integer Date: Tue, 3 Sep 2024 21:32:42 -0500 Message-ID: <20240904023310.163371-4-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240904023310.163371-1-aford173@gmail.com> References: <20240904023310.163371-1-aford173@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There is currently a look-up table for a variety of resolutions. Since the phy has the ability to dynamically calculate the values necessary to use the intger divider which should allow more resolutions without having to update the look-up-table. If the lookup table cannot find an exact match, fall back to the dynamic calculator of the integer divider. Previously, the value of P was hard-coded to 1, this required an update to the phy_pll_cfg table to add in the extra value into the table, so if the value of P is calculated to be something else by the PMS calculator, the calculated_phy_pll_cfg structure can be used instead without having to keep track of which method was used. Signed-off-by: Adam Ford Reviewed-by: Frieder Schrempf Tested-by: Frieder Schrempf --- V5: No Change V4: No Change V3: Change size of pll_div_regs to include PHY_REG01 (P) Create calculated_phy_pll_cfg to containe the values Eliminate the PMS calculation from fsl_samsung_hdmi_phy_configure Make the LUT primary and fall back to integer calculator in phy_clk_round_rate. Check the range right away to ensure it's reaonsable rather than trying to find a clock only to learn it's outside the range. Overall added notes and comments where stuff may not be intuitive. V2: Update phy_clk_round_rate and phy_clk_set_rate to both support the integer clock PMS calculator. --- drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 341 +++++++++++++------ 1 file changed, 235 insertions(+), 106 deletions(-) diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/fre= escale/phy-fsl-samsung-hdmi.c index 4f6874226f9a..8f2c0082aa12 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -16,6 +16,8 @@ =20 #define PHY_REG(reg) (reg * 4) =20 +#define REG01_PMS_P_MASK GENMASK(3, 0) +#define REG03_PMS_S_MASK GENMASK(7, 4) #define REG12_CK_DIV_MASK GENMASK(5, 4) =20 #define REG13_TG_CODE_LOW_MASK GENMASK(7, 0) @@ -38,281 +40,296 @@ #define REG34_PLL_LOCK BIT(6) #define REG34_PHY_CLK_READY BIT(5) =20 -#define PHY_PLL_DIV_REGS_NUM 6 +#ifndef MHZ +#define MHZ (1000UL * 1000UL) +#endif + +#define PHY_PLL_DIV_REGS_NUM 7 =20 struct phy_config { u32 pixclk; u8 pll_div_regs[PHY_PLL_DIV_REGS_NUM]; }; =20 +/* + * The calculated_phy_pll_cfg only handles integer divider for PMS only, + * meaning the last four entries will be fixed, but the first three will + * be calculated by the PMS calculator + */ +static struct phy_config calculated_phy_pll_cfg =3D { + .pixclk =3D 0, + .pll_div_regs =3D { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00 }, +}; + +/* The lookup table contains values for which the fractional divder is use= d */ static const struct phy_config phy_pll_cfg[] =3D { { .pixclk =3D 22250000, - .pll_div_regs =3D { 0x4b, 0xf1, 0x89, 0x88, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x4b, 0xf1, 0x89, 0x88, 0x80, 0x40 }, }, { .pixclk =3D 23750000, - .pll_div_regs =3D { 0x50, 0xf1, 0x86, 0x85, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x50, 0xf1, 0x86, 0x85, 0x80, 0x40 }, }, { .pixclk =3D 24000000, - .pll_div_regs =3D { 0x50, 0xf0, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs =3D { 0xd1, 0x50, 0xf0, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk =3D 24024000, - .pll_div_regs =3D { 0x50, 0xf1, 0x99, 0x02, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x50, 0xf1, 0x99, 0x02, 0x80, 0x40 }, }, { .pixclk =3D 25175000, - .pll_div_regs =3D { 0x54, 0xfc, 0xcc, 0x91, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x54, 0xfc, 0xcc, 0x91, 0x80, 0x40 }, }, { .pixclk =3D 25200000, - .pll_div_regs =3D { 0x54, 0xf0, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs =3D { 0xd1, 0x54, 0xf0, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk =3D 26750000, - .pll_div_regs =3D { 0x5a, 0xf2, 0x89, 0x88, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x5a, 0xf2, 0x89, 0x88, 0x80, 0x40 }, }, { .pixclk =3D 27000000, - .pll_div_regs =3D { 0x5a, 0xf0, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs =3D { 0xd1, 0x5a, 0xf0, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk =3D 27027000, - .pll_div_regs =3D { 0x5a, 0xf2, 0xfd, 0x0c, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x5a, 0xf2, 0xfd, 0x0c, 0x80, 0x40 }, }, { .pixclk =3D 29500000, - .pll_div_regs =3D { 0x62, 0xf4, 0x95, 0x08, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x62, 0xf4, 0x95, 0x08, 0x80, 0x40 }, }, { .pixclk =3D 30750000, - .pll_div_regs =3D { 0x66, 0xf4, 0x82, 0x01, 0x88, 0x45 }, + .pll_div_regs =3D { 0xd1, 0x66, 0xf4, 0x82, 0x01, 0x88, 0x45 }, }, { .pixclk =3D 30888000, - .pll_div_regs =3D { 0x66, 0xf4, 0x99, 0x18, 0x88, 0x45 }, + .pll_div_regs =3D { 0xd1, 0x66, 0xf4, 0x99, 0x18, 0x88, 0x45 }, }, { .pixclk =3D 33750000, - .pll_div_regs =3D { 0x70, 0xf4, 0x82, 0x01, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x70, 0xf4, 0x82, 0x01, 0x80, 0x40 }, }, { .pixclk =3D 35000000, - .pll_div_regs =3D { 0x58, 0xb8, 0x8b, 0x88, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x58, 0xb8, 0x8b, 0x88, 0x80, 0x40 }, }, { .pixclk =3D 36000000, - .pll_div_regs =3D { 0x5a, 0xb0, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs =3D { 0xd1, 0x5a, 0xb0, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk =3D 36036000, - .pll_div_regs =3D { 0x5a, 0xb2, 0xfd, 0x0c, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x5a, 0xb2, 0xfd, 0x0c, 0x80, 0x40 }, }, { .pixclk =3D 40000000, - .pll_div_regs =3D { 0x64, 0xb0, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs =3D { 0xd1, 0x64, 0xb0, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk =3D 43200000, - .pll_div_regs =3D { 0x5a, 0x90, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs =3D { 0xd1, 0x5a, 0x90, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk =3D 43243200, - .pll_div_regs =3D { 0x5a, 0x92, 0xfd, 0x0c, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x5a, 0x92, 0xfd, 0x0c, 0x80, 0x40 }, }, { .pixclk =3D 44500000, - .pll_div_regs =3D { 0x5c, 0x92, 0x98, 0x11, 0x84, 0x41 }, + .pll_div_regs =3D { 0xd1, 0x5c, 0x92, 0x98, 0x11, 0x84, 0x41 }, }, { .pixclk =3D 47000000, - .pll_div_regs =3D { 0x62, 0x94, 0x95, 0x82, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x62, 0x94, 0x95, 0x82, 0x80, 0x40 }, }, { .pixclk =3D 47500000, - .pll_div_regs =3D { 0x63, 0x96, 0xa1, 0x82, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x63, 0x96, 0xa1, 0x82, 0x80, 0x40 }, }, { .pixclk =3D 50349650, - .pll_div_regs =3D { 0x54, 0x7c, 0xc3, 0x8f, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x54, 0x7c, 0xc3, 0x8f, 0x80, 0x40 }, }, { .pixclk =3D 50400000, - .pll_div_regs =3D { 0x54, 0x70, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs =3D { 0xd1, 0x54, 0x70, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk =3D 53250000, - .pll_div_regs =3D { 0x58, 0x72, 0x84, 0x03, 0x82, 0x41 }, + .pll_div_regs =3D { 0xd1, 0x58, 0x72, 0x84, 0x03, 0x82, 0x41 }, }, { .pixclk =3D 53500000, - .pll_div_regs =3D { 0x5a, 0x72, 0x89, 0x88, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x5a, 0x72, 0x89, 0x88, 0x80, 0x40 }, }, { .pixclk =3D 54000000, - .pll_div_regs =3D { 0x5a, 0x70, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs =3D { 0xd1, 0x5a, 0x70, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk =3D 54054000, - .pll_div_regs =3D { 0x5a, 0x72, 0xfd, 0x0c, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x5a, 0x72, 0xfd, 0x0c, 0x80, 0x40 }, }, { .pixclk =3D 59000000, - .pll_div_regs =3D { 0x62, 0x74, 0x95, 0x08, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x62, 0x74, 0x95, 0x08, 0x80, 0x40 }, }, { .pixclk =3D 59340659, - .pll_div_regs =3D { 0x62, 0x74, 0xdb, 0x52, 0x88, 0x47 }, + .pll_div_regs =3D { 0xd1, 0x62, 0x74, 0xdb, 0x52, 0x88, 0x47 }, }, { .pixclk =3D 59400000, - .pll_div_regs =3D { 0x63, 0x70, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs =3D { 0xd1, 0x63, 0x70, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk =3D 61500000, - .pll_div_regs =3D { 0x66, 0x74, 0x82, 0x01, 0x88, 0x45 }, + .pll_div_regs =3D { 0xd1, 0x66, 0x74, 0x82, 0x01, 0x88, 0x45 }, }, { .pixclk =3D 63500000, - .pll_div_regs =3D { 0x69, 0x74, 0x89, 0x08, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x69, 0x74, 0x89, 0x08, 0x80, 0x40 }, }, { .pixclk =3D 67500000, - .pll_div_regs =3D { 0x54, 0x52, 0x87, 0x03, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x54, 0x52, 0x87, 0x03, 0x80, 0x40 }, }, { .pixclk =3D 70000000, - .pll_div_regs =3D { 0x58, 0x58, 0x8b, 0x88, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x58, 0x58, 0x8b, 0x88, 0x80, 0x40 }, }, { .pixclk =3D 72000000, - .pll_div_regs =3D { 0x5a, 0x50, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs =3D { 0xd1, 0x5a, 0x50, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk =3D 72072000, - .pll_div_regs =3D { 0x5a, 0x52, 0xfd, 0x0c, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x5a, 0x52, 0xfd, 0x0c, 0x80, 0x40 }, }, { .pixclk =3D 74176000, - .pll_div_regs =3D { 0x5d, 0x58, 0xdb, 0xA2, 0x88, 0x41 }, + .pll_div_regs =3D { 0xd1, 0x5d, 0x58, 0xdb, 0xA2, 0x88, 0x41 }, }, { .pixclk =3D 74250000, - .pll_div_regs =3D { 0x5c, 0x52, 0x90, 0x0d, 0x84, 0x41 }, + .pll_div_regs =3D { 0xd1, 0x5c, 0x52, 0x90, 0x0d, 0x84, 0x41 }, }, { .pixclk =3D 78500000, - .pll_div_regs =3D { 0x62, 0x54, 0x87, 0x01, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x62, 0x54, 0x87, 0x01, 0x80, 0x40 }, }, { .pixclk =3D 80000000, - .pll_div_regs =3D { 0x64, 0x50, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs =3D { 0xd1, 0x64, 0x50, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk =3D 82000000, - .pll_div_regs =3D { 0x66, 0x54, 0x82, 0x01, 0x88, 0x45 }, + .pll_div_regs =3D { 0xd1, 0x66, 0x54, 0x82, 0x01, 0x88, 0x45 }, }, { .pixclk =3D 82500000, - .pll_div_regs =3D { 0x67, 0x54, 0x88, 0x01, 0x90, 0x49 }, + .pll_div_regs =3D { 0xd1, 0x67, 0x54, 0x88, 0x01, 0x90, 0x49 }, }, { .pixclk =3D 89000000, - .pll_div_regs =3D { 0x70, 0x54, 0x84, 0x83, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x70, 0x54, 0x84, 0x83, 0x80, 0x40 }, }, { .pixclk =3D 90000000, - .pll_div_regs =3D { 0x70, 0x54, 0x82, 0x01, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x70, 0x54, 0x82, 0x01, 0x80, 0x40 }, }, { .pixclk =3D 94000000, - .pll_div_regs =3D { 0x4e, 0x32, 0xa7, 0x10, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x4e, 0x32, 0xa7, 0x10, 0x80, 0x40 }, }, { .pixclk =3D 95000000, - .pll_div_regs =3D { 0x50, 0x31, 0x86, 0x85, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x50, 0x31, 0x86, 0x85, 0x80, 0x40 }, }, { .pixclk =3D 98901099, - .pll_div_regs =3D { 0x52, 0x3a, 0xdb, 0x4c, 0x88, 0x47 }, + .pll_div_regs =3D { 0xd1, 0x52, 0x3a, 0xdb, 0x4c, 0x88, 0x47 }, }, { .pixclk =3D 99000000, - .pll_div_regs =3D { 0x52, 0x32, 0x82, 0x01, 0x88, 0x47 }, + .pll_div_regs =3D { 0xd1, 0x52, 0x32, 0x82, 0x01, 0x88, 0x47 }, }, { .pixclk =3D 100699300, - .pll_div_regs =3D { 0x54, 0x3c, 0xc3, 0x8f, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x54, 0x3c, 0xc3, 0x8f, 0x80, 0x40 }, }, { .pixclk =3D 100800000, - .pll_div_regs =3D { 0x54, 0x30, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs =3D { 0xd1, 0x54, 0x30, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk =3D 102500000, - .pll_div_regs =3D { 0x55, 0x32, 0x8c, 0x05, 0x90, 0x4b }, + .pll_div_regs =3D { 0xd1, 0x55, 0x32, 0x8c, 0x05, 0x90, 0x4b }, }, { .pixclk =3D 104750000, - .pll_div_regs =3D { 0x57, 0x32, 0x98, 0x07, 0x90, 0x49 }, + .pll_div_regs =3D { 0xd1, 0x57, 0x32, 0x98, 0x07, 0x90, 0x49 }, }, { .pixclk =3D 106500000, - .pll_div_regs =3D { 0x58, 0x32, 0x84, 0x03, 0x82, 0x41 }, + .pll_div_regs =3D { 0xd1, 0x58, 0x32, 0x84, 0x03, 0x82, 0x41 }, }, { .pixclk =3D 107000000, - .pll_div_regs =3D { 0x5a, 0x32, 0x89, 0x88, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x5a, 0x32, 0x89, 0x88, 0x80, 0x40 }, }, { .pixclk =3D 108000000, - .pll_div_regs =3D { 0x5a, 0x30, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs =3D { 0xd1, 0x5a, 0x30, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk =3D 108108000, - .pll_div_regs =3D { 0x5a, 0x32, 0xfd, 0x0c, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x5a, 0x32, 0xfd, 0x0c, 0x80, 0x40 }, }, { .pixclk =3D 118000000, - .pll_div_regs =3D { 0x62, 0x34, 0x95, 0x08, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x62, 0x34, 0x95, 0x08, 0x80, 0x40 }, }, { .pixclk =3D 118800000, - .pll_div_regs =3D { 0x63, 0x30, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs =3D { 0xd1, 0x63, 0x30, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk =3D 123000000, - .pll_div_regs =3D { 0x66, 0x34, 0x82, 0x01, 0x88, 0x45 }, + .pll_div_regs =3D { 0xd1, 0x66, 0x34, 0x82, 0x01, 0x88, 0x45 }, }, { .pixclk =3D 127000000, - .pll_div_regs =3D { 0x69, 0x34, 0x89, 0x08, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x69, 0x34, 0x89, 0x08, 0x80, 0x40 }, }, { .pixclk =3D 135000000, - .pll_div_regs =3D { 0x70, 0x34, 0x82, 0x01, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x70, 0x34, 0x82, 0x01, 0x80, 0x40 }, }, { .pixclk =3D 135580000, - .pll_div_regs =3D { 0x71, 0x39, 0xe9, 0x82, 0x9c, 0x5b }, + .pll_div_regs =3D { 0xd1, 0x71, 0x39, 0xe9, 0x82, 0x9c, 0x5b }, }, { .pixclk =3D 137520000, - .pll_div_regs =3D { 0x72, 0x38, 0x99, 0x10, 0x85, 0x41 }, + .pll_div_regs =3D { 0xd1, 0x72, 0x38, 0x99, 0x10, 0x85, 0x41 }, }, { .pixclk =3D 138750000, - .pll_div_regs =3D { 0x73, 0x35, 0x88, 0x05, 0x90, 0x4d }, + .pll_div_regs =3D { 0xd1, 0x73, 0x35, 0x88, 0x05, 0x90, 0x4d }, }, { .pixclk =3D 140000000, - .pll_div_regs =3D { 0x75, 0x36, 0xa7, 0x90, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x75, 0x36, 0xa7, 0x90, 0x80, 0x40 }, }, { .pixclk =3D 144000000, - .pll_div_regs =3D { 0x78, 0x30, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs =3D { 0xd1, 0x78, 0x30, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk =3D 148352000, - .pll_div_regs =3D { 0x7b, 0x35, 0xdb, 0x39, 0x90, 0x45 }, + .pll_div_regs =3D { 0xd1, 0x7b, 0x35, 0xdb, 0x39, 0x90, 0x45 }, }, { .pixclk =3D 148500000, - .pll_div_regs =3D { 0x7b, 0x35, 0x84, 0x03, 0x90, 0x45 }, + .pll_div_regs =3D { 0xd1, 0x7b, 0x35, 0x84, 0x03, 0x90, 0x45 }, }, { .pixclk =3D 154000000, - .pll_div_regs =3D { 0x40, 0x18, 0x83, 0x01, 0x00, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x40, 0x18, 0x83, 0x01, 0x00, 0x40 }, }, { .pixclk =3D 157000000, - .pll_div_regs =3D { 0x41, 0x11, 0xa7, 0x14, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x41, 0x11, 0xa7, 0x14, 0x80, 0x40 }, }, { .pixclk =3D 160000000, - .pll_div_regs =3D { 0x42, 0x12, 0xa1, 0x20, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x42, 0x12, 0xa1, 0x20, 0x80, 0x40 }, }, { .pixclk =3D 162000000, - .pll_div_regs =3D { 0x43, 0x18, 0x8b, 0x08, 0x96, 0x55 }, + .pll_div_regs =3D { 0xd1, 0x43, 0x18, 0x8b, 0x08, 0x96, 0x55 }, }, { .pixclk =3D 164000000, - .pll_div_regs =3D { 0x45, 0x11, 0x83, 0x82, 0x90, 0x4b }, + .pll_div_regs =3D { 0xd1, 0x45, 0x11, 0x83, 0x82, 0x90, 0x4b }, }, { .pixclk =3D 165000000, - .pll_div_regs =3D { 0x45, 0x11, 0x84, 0x81, 0x90, 0x4b }, + .pll_div_regs =3D { 0xd1, 0x45, 0x11, 0x84, 0x81, 0x90, 0x4b }, }, { .pixclk =3D 180000000, - .pll_div_regs =3D { 0x4b, 0x10, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs =3D { 0xd1, 0x4b, 0x10, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk =3D 185625000, - .pll_div_regs =3D { 0x4e, 0x12, 0x9a, 0x95, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x4e, 0x12, 0x9a, 0x95, 0x80, 0x40 }, }, { .pixclk =3D 188000000, - .pll_div_regs =3D { 0x4e, 0x12, 0xa7, 0x10, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x4e, 0x12, 0xa7, 0x10, 0x80, 0x40 }, }, { .pixclk =3D 198000000, - .pll_div_regs =3D { 0x52, 0x12, 0x82, 0x01, 0x88, 0x47 }, + .pll_div_regs =3D { 0xd1, 0x52, 0x12, 0x82, 0x01, 0x88, 0x47 }, }, { .pixclk =3D 205000000, - .pll_div_regs =3D { 0x55, 0x12, 0x8c, 0x05, 0x90, 0x4b }, + .pll_div_regs =3D { 0xd1, 0x55, 0x12, 0x8c, 0x05, 0x90, 0x4b }, }, { .pixclk =3D 209500000, - .pll_div_regs =3D { 0x57, 0x12, 0x98, 0x07, 0x90, 0x49 }, + .pll_div_regs =3D { 0xd1, 0x57, 0x12, 0x98, 0x07, 0x90, 0x49 }, }, { .pixclk =3D 213000000, - .pll_div_regs =3D { 0x58, 0x12, 0x84, 0x03, 0x82, 0x41 }, + .pll_div_regs =3D { 0xd1, 0x58, 0x12, 0x84, 0x03, 0x82, 0x41 }, }, { .pixclk =3D 216000000, - .pll_div_regs =3D { 0x5a, 0x10, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs =3D { 0xd1, 0x5a, 0x10, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk =3D 216216000, - .pll_div_regs =3D { 0x5a, 0x12, 0xfd, 0x0c, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x5a, 0x12, 0xfd, 0x0c, 0x80, 0x40 }, }, { .pixclk =3D 237600000, - .pll_div_regs =3D { 0x63, 0x10, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs =3D { 0xd1, 0x63, 0x10, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk =3D 254000000, - .pll_div_regs =3D { 0x69, 0x14, 0x89, 0x08, 0x80, 0x40 }, + .pll_div_regs =3D { 0xd1, 0x69, 0x14, 0x89, 0x08, 0x80, 0x40 }, }, { .pixclk =3D 277500000, - .pll_div_regs =3D { 0x73, 0x15, 0x88, 0x05, 0x90, 0x4d }, + .pll_div_regs =3D { 0xd1, 0x73, 0x15, 0x88, 0x05, 0x90, 0x4d }, }, { .pixclk =3D 288000000, - .pll_div_regs =3D { 0x78, 0x10, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs =3D { 0xd1, 0x78, 0x10, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk =3D 297000000, - .pll_div_regs =3D { 0x7b, 0x15, 0x84, 0x03, 0x90, 0x45 }, + .pll_div_regs =3D { 0xd1, 0x7b, 0x15, 0x84, 0x03, 0x90, 0x45 }, }, }; =20 @@ -322,7 +339,8 @@ struct reg_settings { }; =20 static const struct reg_settings common_phy_cfg[] =3D { - { PHY_REG(0), 0x00 }, { PHY_REG(1), 0xd1 }, + { PHY_REG(0), 0x00 }, + /* PHY_REG(1-7) pix clk specific */ { PHY_REG(8), 0x4f }, { PHY_REG(9), 0x30 }, { PHY_REG(10), 0x33 }, { PHY_REG(11), 0x65 }, /* REG12 pixclk specific */ @@ -415,6 +433,76 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl= _samsung_hdmi_phy *phy, phy->regs + PHY_REG(14)); } =20 +static unsigned long fsl_samsung_hdmi_phy_find_pms(unsigned long fout, u8 = *p, u16 *m, u8 *s) +{ + unsigned long best_freq =3D 0; + u32 min_delta =3D 0xffffffff; + u8 _p, best_p; + u16 _m, best_m; + u8 _s, best_s; + + /* The ref manual states the values of 'P' range from 1 to 11 */ + for (_p =3D 1; _p <=3D 11; ++_p) { + for (_s =3D 1; _s <=3D 16; ++_s) { + u64 tmp; + u32 delta; + + /* s must be one or even */ + if (_s > 1 && (_s & 0x01) =3D=3D 1) + _s++; + + /* _s cannot be 14 per the TRM */ + if (_s =3D=3D 14) + continue; + + /* + * TODO: Ref Manual doesn't state the range of _m + * so this should be further refined if possible. + * This range was set based on the original values + * in the look-up table + */ + tmp =3D (u64)fout * (_p * _s); + do_div(tmp, 24 * MHZ); + _m =3D tmp; + if (_m < 0x30 || _m > 0x7b) + continue; + + /* + * Rev 2 of the Ref Manual states the + * VCO can range between 750MHz and + * 3GHz. The VCO is assumed to be _m x + * the reference frequency of 24MHz divided + * by the prescaler, _p + */ + tmp =3D (u64)_m * 24 * MHZ; + do_div(tmp, _p); + if (tmp < 750 * MHZ || + tmp > 3000 * MHZ) + continue; + + tmp =3D (u64)_m * 24 * MHZ; + do_div(tmp, _p * _s); + + delta =3D abs(fout - tmp); + if (delta < min_delta) { + best_p =3D _p; + best_s =3D _s; + best_m =3D _m; + min_delta =3D delta; + best_freq =3D tmp; + } + } + } + + if (best_freq) { + *p =3D best_p; + *m =3D best_m; + *s =3D best_s; + } + + return best_freq; +} + static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, const struct phy_config *cfg) { @@ -428,13 +516,13 @@ static int fsl_samsung_hdmi_phy_configure(struct fsl_= samsung_hdmi_phy *phy, for (i =3D 0; i < ARRAY_SIZE(common_phy_cfg); i++) writeb(common_phy_cfg[i].val, phy->regs + common_phy_cfg[i].reg); =20 - /* set individual PLL registers PHY_REG2 ... PHY_REG7 */ + /* set individual PLL registers PHY_REG1 ... PHY_REG7 */ for (i =3D 0; i < PHY_PLL_DIV_REGS_NUM; i++) - writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG(2) + i * 4); + writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG(1) + i * 4); =20 - /* High nibble of pll_div_regs[1] contains S which also gets written to R= EG21 */ + /* High nibble of PHY_REG3 and low nibble of PHY_REG21 both contain 'S' */ writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, - cfg->pll_div_regs[1] >> 4), phy->regs + PHY_REG(21)); + cfg->pll_div_regs[2] >> 4), phy->regs + PHY_REG(21)); =20 fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg); =20 @@ -462,29 +550,70 @@ static unsigned long phy_clk_recalc_rate(struct clk_h= w *hw, static long phy_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { + u32 int_div_clk; int i; + u16 m; + u8 p, s; + + /* If the clock is out of range return error instead of searching */ + if (rate > 297000000 || rate < 22250000) + return -EINVAL; =20 + /* Check the look-up table */ for (i =3D ARRAY_SIZE(phy_pll_cfg) - 1; i >=3D 0; i--) if (phy_pll_cfg[i].pixclk <=3D rate) - return phy_pll_cfg[i].pixclk; + break; + /* If the rate is an exact match, return it now */ + if (rate =3D=3D phy_pll_cfg[i].pixclk) + return phy_pll_cfg[i].pixclk; + + /* + * The math on the lookup table shows the PMS math yields a + * frequency 5 x pixclk. + * When we check the integer divider against the desired rate, + * multiply the rate x 5 and then divide the outcome by 5. + */ + int_div_clk =3D fsl_samsung_hdmi_phy_find_pms(rate * 5, &p, &m, &s) / 5; =20 - return -EINVAL; + /* If the rate is an exact match, return it now */ + if (int_div_clk =3D=3D rate) + return int_div_clk; + + /* Fall back to the closest value in the LUT */ + return phy_pll_cfg[i].pixclk; } =20 static int phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct fsl_samsung_hdmi_phy *phy =3D to_fsl_samsung_hdmi_phy(hw); + u32 int_div_clk; int i; - - for (i =3D ARRAY_SIZE(phy_pll_cfg) - 1; i >=3D 0; i--) - if (phy_pll_cfg[i].pixclk <=3D rate) - break; - - if (i < 0) - return -EINVAL; - - phy->cur_cfg =3D &phy_pll_cfg[i]; + u16 m; + u8 p, s; + + /* If the integer divider works, just use it */ + int_div_clk =3D fsl_samsung_hdmi_phy_find_pms(rate * 5, &p, &m, &s) / 5; + if (int_div_clk =3D=3D rate) { + dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: using integer divider\n"); + calculated_phy_pll_cfg.pixclk =3D int_div_clk; + calculated_phy_pll_cfg.pll_div_regs[0] =3D FIELD_PREP(REG01_PMS_P_MASK, = p); + calculated_phy_pll_cfg.pll_div_regs[1] =3D m; + calculated_phy_pll_cfg.pll_div_regs[2] =3D FIELD_PREP(REG03_PMS_S_MASK, = s-1); + /* pll_div_regs 3-6 are fixed and pre-defined already */ + phy->cur_cfg =3D &calculated_phy_pll_cfg; + } else { + /* Otherwise, search the LUT */ + dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: using fractional divider\n"); + for (i =3D ARRAY_SIZE(phy_pll_cfg) - 1; i >=3D 0; i--) + if (phy_pll_cfg[i].pixclk <=3D rate) + break; + + if (i < 0) + return -EINVAL; + + phy->cur_cfg =3D &phy_pll_cfg[i]; + } =20 return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); 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[75.72.166.104]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-39f3afc4ff6sm34556175ab.37.2024.09.03.19.33.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2024 19:33:39 -0700 (PDT) From: Adam Ford To: linux-phy@lists.infradead.org Cc: dominique.martinet@atmark-techno.com, linux-imx@nxp.com, festevam@gmail.com, frieder.schrempf@kontron.de, aford@beaconembedded.com, Sandor.yu@nxp.com, Adam Ford , Vinod Koul , Kishon Vijay Abraham I , Marco Felsch , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Lucas Stach , linux-kernel@vger.kernel.org Subject: [PATCH V5 4/5] phy: freescale: fsl-samsung-hdmi: Use closest divider Date: Tue, 3 Sep 2024 21:32:43 -0500 Message-ID: <20240904023310.163371-5-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240904023310.163371-1-aford173@gmail.com> References: <20240904023310.163371-1-aford173@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, if the clock values cannot be set to the exact rate, the round_rate and set_rate functions use the closest value found in the look-up-table. In preparation of removing values from the LUT that can be calculated evenly with the integer calculator, it's necessary to ensure to check both the look-up-table and the integer divider clock values to get the closest values to the requested value. It does this by measuring the difference between the requested clock value and the closest value in both integer divider calucator and the fractional clock look-up-table. Which ever has the smallest difference between them is returned as the cloesest rate. Signed-off-by: Adam Ford Signed-off-by: Dominique Martinet --- V5: No Change V4: New to series --- drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 40 +++++++++++++++----- 1 file changed, 31 insertions(+), 9 deletions(-) diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/fre= escale/phy-fsl-samsung-hdmi.c index 8f2c0082aa12..56b08e684179 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -550,7 +550,7 @@ static unsigned long phy_clk_recalc_rate(struct clk_hw = *hw, static long phy_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { - u32 int_div_clk; + u32 int_div_clk, delta_int, delta_frac; int i; u16 m; u8 p, s; @@ -563,6 +563,7 @@ static long phy_clk_round_rate(struct clk_hw *hw, for (i =3D ARRAY_SIZE(phy_pll_cfg) - 1; i >=3D 0; i--) if (phy_pll_cfg[i].pixclk <=3D rate) break; + /* If the rate is an exact match, return it now */ if (rate =3D=3D phy_pll_cfg[i].pixclk) return phy_pll_cfg[i].pixclk; @@ -579,15 +580,21 @@ static long phy_clk_round_rate(struct clk_hw *hw, if (int_div_clk =3D=3D rate) return int_div_clk; =20 - /* Fall back to the closest value in the LUT */ - return phy_pll_cfg[i].pixclk; + /* Calculate the differences and use the closest one */ + delta_frac =3D (rate - phy_pll_cfg[i].pixclk); + delta_int =3D (rate - int_div_clk); + + if (delta_int < delta_frac) + return int_div_clk; + else + return phy_pll_cfg[i].pixclk; } =20 static int phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct fsl_samsung_hdmi_phy *phy =3D to_fsl_samsung_hdmi_phy(hw); - u32 int_div_clk; + u32 int_div_clk, delta_int, delta_frac; int i; u16 m; u8 p, s; @@ -602,19 +609,34 @@ static int phy_clk_set_rate(struct clk_hw *hw, calculated_phy_pll_cfg.pll_div_regs[2] =3D FIELD_PREP(REG03_PMS_S_MASK, = s-1); /* pll_div_regs 3-6 are fixed and pre-defined already */ phy->cur_cfg =3D &calculated_phy_pll_cfg; + goto done; } else { /* Otherwise, search the LUT */ - dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: using fractional divider\n"); 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[75.72.166.104]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-39f3afc4ff6sm34556175ab.37.2024.09.03.19.33.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2024 19:33:44 -0700 (PDT) From: Adam Ford To: linux-phy@lists.infradead.org Cc: dominique.martinet@atmark-techno.com, linux-imx@nxp.com, festevam@gmail.com, frieder.schrempf@kontron.de, aford@beaconembedded.com, Sandor.yu@nxp.com, Adam Ford , Vinod Koul , Kishon Vijay Abraham I , Marco Felsch , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Lucas Stach , linux-kernel@vger.kernel.org Subject: [PATCH V5 5/5] phy: freescale: fsl-samsung-hdmi: Remove unnecessary LUT entries Date: Tue, 3 Sep 2024 21:32:44 -0500 Message-ID: <20240904023310.163371-6-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240904023310.163371-1-aford173@gmail.com> References: <20240904023310.163371-1-aford173@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The lookup table contains entries which use the integer divider instead of just the fractional divider. Since the set and round functions check both the integer divider values and the LUT values, it's no longer necessary to keep the integer divder values in the, as they are able to by dynamically calcuated. Signed-off-by: Adam Ford Reviewed-by: Frieder Schrempf Tested-by: Frieder Schrempf --- V5: No Change V4: New to series --- drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 83 +++----------------- 1 file changed, 13 insertions(+), 70 deletions(-) diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/fre= escale/phy-fsl-samsung-hdmi.c index 56b08e684179..a37d7b989552 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -69,25 +69,16 @@ static const struct phy_config phy_pll_cfg[] =3D { }, { .pixclk =3D 23750000, .pll_div_regs =3D { 0xd1, 0x50, 0xf1, 0x86, 0x85, 0x80, 0x40 }, - }, { - .pixclk =3D 24000000, - .pll_div_regs =3D { 0xd1, 0x50, 0xf0, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk =3D 24024000, .pll_div_regs =3D { 0xd1, 0x50, 0xf1, 0x99, 0x02, 0x80, 0x40 }, }, { .pixclk =3D 25175000, .pll_div_regs =3D { 0xd1, 0x54, 0xfc, 0xcc, 0x91, 0x80, 0x40 }, - }, { - .pixclk =3D 25200000, - .pll_div_regs =3D { 0xd1, 0x54, 0xf0, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk =3D 26750000, .pll_div_regs =3D { 0xd1, 0x5a, 0xf2, 0x89, 0x88, 0x80, 0x40 }, - }, { - .pixclk =3D 27000000, - .pll_div_regs =3D { 0xd1, 0x5a, 0xf0, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk =3D 27027000, .pll_div_regs =3D { 0xd1, 0x5a, 0xf2, 0xfd, 0x0c, 0x80, 0x40 }, }, { @@ -105,18 +96,9 @@ static const struct phy_config phy_pll_cfg[] =3D { }, { .pixclk =3D 35000000, .pll_div_regs =3D { 0xd1, 0x58, 0xb8, 0x8b, 0x88, 0x80, 0x40 }, - }, { - .pixclk =3D 36000000, - .pll_div_regs =3D { 0xd1, 0x5a, 0xb0, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk =3D 36036000, .pll_div_regs =3D { 0xd1, 0x5a, 0xb2, 0xfd, 0x0c, 0x80, 0x40 }, - }, { - .pixclk =3D 40000000, - .pll_div_regs =3D { 0xd1, 0x64, 0xb0, 0x00, 0x00, 0x80, 0x00 }, - }, { - .pixclk =3D 43200000, - .pll_div_regs =3D { 0xd1, 0x5a, 0x90, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk =3D 43243200, .pll_div_regs =3D { 0xd1, 0x5a, 0x92, 0xfd, 0x0c, 0x80, 0x40 }, @@ -132,19 +114,13 @@ static const struct phy_config phy_pll_cfg[] =3D { }, { .pixclk =3D 50349650, .pll_div_regs =3D { 0xd1, 0x54, 0x7c, 0xc3, 0x8f, 0x80, 0x40 }, - }, { - .pixclk =3D 50400000, - .pll_div_regs =3D { 0xd1, 0x54, 0x70, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk =3D 53250000, .pll_div_regs =3D { 0xd1, 0x58, 0x72, 0x84, 0x03, 0x82, 0x41 }, }, { .pixclk =3D 53500000, .pll_div_regs =3D { 0xd1, 0x5a, 0x72, 0x89, 0x88, 0x80, 0x40 }, - }, { - .pixclk =3D 54000000, - .pll_div_regs =3D { 0xd1, 0x5a, 0x70, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk =3D 54054000, .pll_div_regs =3D { 0xd1, 0x5a, 0x72, 0xfd, 0x0c, 0x80, 0x40 }, }, { @@ -153,10 +129,7 @@ static const struct phy_config phy_pll_cfg[] =3D { }, { .pixclk =3D 59340659, .pll_div_regs =3D { 0xd1, 0x62, 0x74, 0xdb, 0x52, 0x88, 0x47 }, - }, { - .pixclk =3D 59400000, - .pll_div_regs =3D { 0xd1, 0x63, 0x70, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk =3D 61500000, .pll_div_regs =3D { 0xd1, 0x66, 0x74, 0x82, 0x01, 0x88, 0x45 }, }, { @@ -168,10 +141,7 @@ static const struct phy_config phy_pll_cfg[] =3D { }, { .pixclk =3D 70000000, .pll_div_regs =3D { 0xd1, 0x58, 0x58, 0x8b, 0x88, 0x80, 0x40 }, - }, { - .pixclk =3D 72000000, - .pll_div_regs =3D { 0xd1, 0x5a, 0x50, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk =3D 72072000, .pll_div_regs =3D { 0xd1, 0x5a, 0x52, 0xfd, 0x0c, 0x80, 0x40 }, }, { @@ -183,10 +153,7 @@ static const struct phy_config phy_pll_cfg[] =3D { }, { .pixclk =3D 78500000, .pll_div_regs =3D { 0xd1, 0x62, 0x54, 0x87, 0x01, 0x80, 0x40 }, - }, { - .pixclk =3D 80000000, - .pll_div_regs =3D { 0xd1, 0x64, 0x50, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk =3D 82000000, .pll_div_regs =3D { 0xd1, 0x66, 0x54, 0x82, 0x01, 0x88, 0x45 }, }, { @@ -213,10 +180,7 @@ static const struct phy_config phy_pll_cfg[] =3D { }, { .pixclk =3D 100699300, .pll_div_regs =3D { 0xd1, 0x54, 0x3c, 0xc3, 0x8f, 0x80, 0x40 }, - }, { - .pixclk =3D 100800000, - .pll_div_regs =3D { 0xd1, 0x54, 0x30, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk =3D 102500000, .pll_div_regs =3D { 0xd1, 0x55, 0x32, 0x8c, 0x05, 0x90, 0x4b }, }, { @@ -228,19 +192,13 @@ static const struct phy_config phy_pll_cfg[] =3D { }, { .pixclk =3D 107000000, .pll_div_regs =3D { 0xd1, 0x5a, 0x32, 0x89, 0x88, 0x80, 0x40 }, - }, { - .pixclk =3D 108000000, - .pll_div_regs =3D { 0xd1, 0x5a, 0x30, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk =3D 108108000, .pll_div_regs =3D { 0xd1, 0x5a, 0x32, 0xfd, 0x0c, 0x80, 0x40 }, }, { .pixclk =3D 118000000, .pll_div_regs =3D { 0xd1, 0x62, 0x34, 0x95, 0x08, 0x80, 0x40 }, - }, { - .pixclk =3D 118800000, - .pll_div_regs =3D { 0xd1, 0x63, 0x30, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk =3D 123000000, .pll_div_regs =3D { 0xd1, 0x66, 0x34, 0x82, 0x01, 0x88, 0x45 }, }, { @@ -261,10 +219,7 @@ static const struct phy_config phy_pll_cfg[] =3D { }, { .pixclk =3D 140000000, .pll_div_regs =3D { 0xd1, 0x75, 0x36, 0xa7, 0x90, 0x80, 0x40 }, - }, { - .pixclk =3D 144000000, - .pll_div_regs =3D { 0xd1, 0x78, 0x30, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk =3D 148352000, .pll_div_regs =3D { 0xd1, 0x7b, 0x35, 0xdb, 0x39, 0x90, 0x45 }, }, { @@ -288,9 +243,6 @@ static const struct phy_config phy_pll_cfg[] =3D { }, { .pixclk =3D 165000000, .pll_div_regs =3D { 0xd1, 0x45, 0x11, 0x84, 0x81, 0x90, 0x4b }, - }, { - .pixclk =3D 180000000, - .pll_div_regs =3D { 0xd1, 0x4b, 0x10, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk =3D 185625000, .pll_div_regs =3D { 0xd1, 0x4e, 0x12, 0x9a, 0x95, 0x80, 0x40 }, @@ -309,25 +261,16 @@ static const struct phy_config phy_pll_cfg[] =3D { }, { .pixclk =3D 213000000, .pll_div_regs =3D { 0xd1, 0x58, 0x12, 0x84, 0x03, 0x82, 0x41 }, - }, { - .pixclk =3D 216000000, - .pll_div_regs =3D { 0xd1, 0x5a, 0x10, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk =3D 216216000, .pll_div_regs =3D { 0xd1, 0x5a, 0x12, 0xfd, 0x0c, 0x80, 0x40 }, - }, { - .pixclk =3D 237600000, - .pll_div_regs =3D { 0xd1, 0x63, 0x10, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk =3D 254000000, .pll_div_regs =3D { 0xd1, 0x69, 0x14, 0x89, 0x08, 0x80, 0x40 }, }, { .pixclk =3D 277500000, .pll_div_regs =3D { 0xd1, 0x73, 0x15, 0x88, 0x05, 0x90, 0x4d }, - }, { - .pixclk =3D 288000000, - .pll_div_regs =3D { 0xd1, 0x78, 0x10, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk =3D 297000000, .pll_div_regs =3D { 0xd1, 0x7b, 0x15, 0x84, 0x03, 0x90, 0x45 }, }, --=20 2.43.0