From nobody Fri Dec 19 15:19:53 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33B4E1D9321; Wed, 4 Sep 2024 13:18:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725455893; cv=none; b=UYlkQzPni7xWCcbZMhzi2kMxfezEHpccO9G8jdVRCtTIu8eBfbKkD4qzIfKe7QeMC34cbUTdu8ACwjjhV+VbeiqwebDdPTQw+2ATOYHlvp63aXRXCPkdoFMeyGHg8s4qVCgz4ciwVp/tR/pMGGldKqZtjm2AB4JmjmQhkcikcWw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725455893; c=relaxed/simple; bh=Ud8t+NptIm7kdIHbyjKIMjof6/+CgsCMNGFLB/tgAb0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aSHZMc5EnRSkuYnzX2W1WBN2cFRxR5in6Cx2K8tOdbpJLUjWE6ExfiZbccrHPor1cbVQwVMhPFF/F0wIRe74P/R62kt0UsrqYFdmIYKs8VVUvsZKsufBfucSKT8Ay+VyZ1nDu6w4J2KGKOK+aNbz9aBUo76E+xNZc4iVmkKw09E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mUb+nhux; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mUb+nhux" Received: by smtp.kernel.org (Postfix) with ESMTPS id CCAA5C4CEC6; Wed, 4 Sep 2024 13:18:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725455892; bh=Ud8t+NptIm7kdIHbyjKIMjof6/+CgsCMNGFLB/tgAb0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=mUb+nhuxHIi8Ptk5n3OsDarMFfKMNgpv1NgnqCOQQFaBXgEjt11ZhJdcsrKEVRRzX ZoJZKal/H1npuz+qCgQmZan45HTMZDlRhRU0+eYJuvbtOUgkfj+XNgCCgmgByE1jtv 6MU/+APO3aJQM4PjQuj/HcD//kn216GCe7j8PRe0Vt/Dz7sScoKWoSDvZacf5NTi5y 1fN9vg5xzZnjwAiaKBwfKqDRjvjCTCRU1NNwOWonqIsYMfjHeNTwnL/i5ZVn++g3/Y pzQejM/kPuoPK8l3hBvQsllcLB921SGgiMTeZy3K0bBBDZrZjvruTvNQlx0g5wyuTv 3i66qnaoRpIKA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA792CD37B4; Wed, 4 Sep 2024 13:18:12 +0000 (UTC) From: Joel Granados via B4 Relay Date: Wed, 04 Sep 2024 15:17:12 +0200 Subject: [PATCH 1/6] iommu/vt-d: Separate page request queue from SVM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240904-jag-iopfv8-v1-1-e3549920adf3@samsung.com> References: <20240904-jag-iopfv8-v1-0-e3549920adf3@samsung.com> In-Reply-To: <20240904-jag-iopfv8-v1-0-e3549920adf3@samsung.com> To: David Woodhouse , Lu Baolu , Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian , Klaus Jensen Cc: linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Joel Granados X-Mailer: b4 0.15-dev-00a43 X-Developer-Signature: v=1; a=openpgp-sha256; l=28559; i=j.granados@samsung.com; h=from:subject:message-id; bh=TOQqgQuZS0zWrtl/DI+d0pz/7aq+LSM/sVptQHrtB0g=; b=owJ4nAHtARL+kA0DAAoBupfNUreWQU8ByyZiAGbYXhBRyhCBT3yYhGkzj9xDSzOIZickTj3RJ cQwboCXPbHOU4kBswQAAQoAHRYhBK5HCVcl5jElzssnkLqXzVK3lkFPBQJm2F4QAAoJELqXzVK3 lkFPh4oL/idvBd4/dTC8GqEOArTpQE1G7Iivp7Uu0bR0IiEH0uJ8waTqUVy4+V7NvAScKYb8akp Qo71S+EcBJd54KfsmY706OAobU7Zcfyu3b2SAz8UsXcdHs2rPxDSVKpQvmkpCXhCpQzICBXKcey xkncJEp2LViBRxtBsln9NfzYqhtOKaozyVu4qr+3jAmL05mXCDseXJA4uUa4o5oMJspaWsBwtZ3 04/J38VtqYAQpGyB9x/y5JQ1n0qOi98UMbuKLE83kMoZDaguZQehMmao1+zluBKHW/9GNpGrYN0 vTxD8QMBTmyLaoVnxJZfAgqhtPbeWLd7vfr65LACKwFx6qPhpk3V1RQxH4qqRrHsLP6xOp5GRef Ukd92Bd6ohchyFCzOVY6uzbgdOON9xJ8cwmAsbRe8+2g2CEzF/KwjIdl195ZvdN6uRwFEMuTb6l dkSME6h5BNpyv2l1NFeFmRRaeXJ/MPAxb+Iijc9R6G7z3jQtHhBYJRBV74AvJKCG/aKqeSlDt65 Fs= X-Developer-Key: i=j.granados@samsung.com; a=openpgp; fpr=F1F8E46D30F0F6C4A45FF4465895FAAC338C6E77 X-Endpoint-Received: by B4 Relay for j.granados@samsung.com/default with auth_id=70 X-Original-From: Joel Granados Reply-To: j.granados@samsung.com From: Joel Granados IO page faults are no longer dependent on CONFIG_INTEL_IOMMU_SVM. Move all Page Request Queue (PRQ) functions that handle prq events to a new file in drivers/iommu/intel/prq.c. The page_req_des struct is made available in drivers/iommu/intel/iommu.h. No functional changes are intended. This is a preparation patch to enable the use of IO page faults outside the SVM and nested use cases. Signed-off-by: Joel Granados --- drivers/iommu/intel/Makefile | 2 +- drivers/iommu/intel/iommu.c | 18 +- drivers/iommu/intel/iommu.h | 14 +- drivers/iommu/intel/prq.c | 410 +++++++++++++++++++++++++++++++++++++++= ++++ drivers/iommu/intel/svm.c | 397 ---------------------------------------= -- 5 files changed, 423 insertions(+), 418 deletions(-) diff --git a/drivers/iommu/intel/Makefile b/drivers/iommu/intel/Makefile index c8beb0281559..d3bb0798092d 100644 --- a/drivers/iommu/intel/Makefile +++ b/drivers/iommu/intel/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_DMAR_TABLE) +=3D dmar.o -obj-$(CONFIG_INTEL_IOMMU) +=3D iommu.o pasid.o nested.o cache.o +obj-$(CONFIG_INTEL_IOMMU) +=3D iommu.o pasid.o nested.o cache.o prq.o obj-$(CONFIG_DMAR_TABLE) +=3D trace.o cap_audit.o obj-$(CONFIG_DMAR_PERF) +=3D perf.o obj-$(CONFIG_INTEL_IOMMU_DEBUGFS) +=3D debugfs.o diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 4aa070cf56e7..5acc52c62e8c 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1487,12 +1487,10 @@ static void free_dmar_iommu(struct intel_iommu *iom= mu) /* free context mapping */ free_context_table(iommu); =20 -#ifdef CONFIG_INTEL_IOMMU_SVM if (pasid_supported(iommu)) { if (ecap_prs(iommu->ecap)) - intel_svm_finish_prq(iommu); + intel_finish_prq(iommu); } -#endif } =20 /* @@ -2482,19 +2480,18 @@ static int __init init_dmars(void) =20 iommu_flush_write_buffer(iommu); =20 -#ifdef CONFIG_INTEL_IOMMU_SVM if (pasid_supported(iommu) && ecap_prs(iommu->ecap)) { /* * Call dmar_alloc_hwirq() with dmar_global_lock held, * could cause possible lock race condition. */ up_write(&dmar_global_lock); - ret =3D intel_svm_enable_prq(iommu); + ret =3D intel_enable_prq(iommu); down_write(&dmar_global_lock); if (ret) goto free_iommu; } -#endif + ret =3D dmar_set_interrupt(iommu); if (ret) goto free_iommu; @@ -2924,13 +2921,12 @@ static int intel_iommu_add(struct dmar_drhd_unit *d= maru) intel_iommu_init_qi(iommu); iommu_flush_write_buffer(iommu); =20 -#ifdef CONFIG_INTEL_IOMMU_SVM if (pasid_supported(iommu) && ecap_prs(iommu->ecap)) { - ret =3D intel_svm_enable_prq(iommu); + ret =3D intel_enable_prq(iommu); if (ret) goto disable_iommu; } -#endif + ret =3D dmar_set_interrupt(iommu); if (ret) goto disable_iommu; @@ -4673,9 +4669,7 @@ const struct iommu_ops intel_iommu_ops =3D { .def_domain_type =3D device_def_domain_type, .remove_dev_pasid =3D intel_iommu_remove_dev_pasid, .pgsize_bitmap =3D SZ_4K, -#ifdef CONFIG_INTEL_IOMMU_SVM - .page_response =3D intel_svm_page_response, -#endif + .page_response =3D intel_page_response, .default_domain_ops =3D &(const struct iommu_domain_ops) { .attach_dev =3D intel_iommu_attach_device, .set_dev_pasid =3D intel_iommu_set_dev_pasid, diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index a969be2258b1..3bce514e1d88 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -719,12 +719,10 @@ struct intel_iommu { =20 struct iommu_flush flush; #endif -#ifdef CONFIG_INTEL_IOMMU_SVM struct page_req_dsc *prq; unsigned char prq_name[16]; /* Name for PRQ interrupt */ unsigned long prq_seq_number; struct completion prq_complete; -#endif struct iopf_queue *iopf_queue; unsigned char iopfq_name[16]; /* Synchronization between fault report and iommu device release. */ @@ -1156,18 +1154,18 @@ void intel_context_flush_present(struct device_doma= in_info *info, struct context_entry *context, u16 did, bool affect_domains); =20 +int intel_enable_prq(struct intel_iommu *iommu); +int intel_finish_prq(struct intel_iommu *iommu); +void intel_page_response(struct device *dev, struct iopf_fault *evt, + struct iommu_page_response *msg); +void intel_drain_pasid_prq(struct device *dev, u32 pasid); + #ifdef CONFIG_INTEL_IOMMU_SVM void intel_svm_check(struct intel_iommu *iommu); -int intel_svm_enable_prq(struct intel_iommu *iommu); -int intel_svm_finish_prq(struct intel_iommu *iommu); -void intel_svm_page_response(struct device *dev, struct iopf_fault *evt, - struct iommu_page_response *msg); struct iommu_domain *intel_svm_domain_alloc(struct device *dev, struct mm_struct *mm); -void intel_drain_pasid_prq(struct device *dev, u32 pasid); #else static inline void intel_svm_check(struct intel_iommu *iommu) {} -static inline void intel_drain_pasid_prq(struct device *dev, u32 pasid) {} static inline struct iommu_domain *intel_svm_domain_alloc(struct device *d= ev, struct mm_struct *mm) { diff --git a/drivers/iommu/intel/prq.c b/drivers/iommu/intel/prq.c new file mode 100644 index 000000000000..3376f60082b5 --- /dev/null +++ b/drivers/iommu/intel/prq.c @@ -0,0 +1,410 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright =C2=A9 2015 Intel Corporation. + * + * Originally split from drivers/iommu/intel/svm.c + */ + +#include +#include + +#include "iommu.h" +#include "../iommu-pages.h" +#include "trace.h" + +/* Page request queue descriptor */ +struct page_req_dsc { + union { + struct { + u64 type:8; + u64 pasid_present:1; + u64 rsvd:7; + u64 rid:16; + u64 pasid:20; + u64 exe_req:1; + u64 pm_req:1; + u64 rsvd2:10; + }; + u64 qw_0; + }; + union { + struct { + u64 rd_req:1; + u64 wr_req:1; + u64 lpig:1; + u64 prg_index:9; + u64 addr:52; + }; + u64 qw_1; + }; + u64 qw_2; + u64 qw_3; +}; + +/** + * intel_drain_pasid_prq - Drain page requests and responses for a pasid + * @dev: target device + * @pasid: pasid for draining + * + * Drain all pending page requests and responses related to @pasid in both + * software and hardware. This is supposed to be called after the device + * driver has stopped DMA, the pasid entry has been cleared, and both IOTLB + * and DevTLB have been invalidated. + * + * It waits until all pending page requests for @pasid in the page fault + * queue are completed by the prq handling thread. Then follow the steps + * described in VT-d spec CH7.10 to drain all page requests and page + * responses pending in the hardware. + */ +void intel_drain_pasid_prq(struct device *dev, u32 pasid) +{ + struct device_domain_info *info; + struct dmar_domain *domain; + struct intel_iommu *iommu; + struct qi_desc desc[3]; + struct pci_dev *pdev; + int head, tail; + u16 sid, did; + int qdep; + + info =3D dev_iommu_priv_get(dev); + if (WARN_ON(!info || !dev_is_pci(dev))) + return; + + if (!info->pri_enabled) + return; + + iommu =3D info->iommu; + domain =3D info->domain; + pdev =3D to_pci_dev(dev); + sid =3D PCI_DEVID(info->bus, info->devfn); + did =3D domain_id_iommu(domain, iommu); + qdep =3D pci_ats_queue_depth(pdev); + + /* + * Check and wait until all pending page requests in the queue are + * handled by the prq handling thread. + */ +prq_retry: + reinit_completion(&iommu->prq_complete); + tail =3D dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK; + head =3D dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK; + while (head !=3D tail) { + struct page_req_dsc *req; + + req =3D &iommu->prq[head / sizeof(*req)]; + if (!req->pasid_present || req->pasid !=3D pasid) { + head =3D (head + sizeof(*req)) & PRQ_RING_MASK; + continue; + } + + wait_for_completion(&iommu->prq_complete); + goto prq_retry; + } + + iopf_queue_flush_dev(dev); + + /* + * Perform steps described in VT-d spec CH7.10 to drain page + * requests and responses in hardware. + */ + memset(desc, 0, sizeof(desc)); + desc[0].qw0 =3D QI_IWD_STATUS_DATA(QI_DONE) | + QI_IWD_FENCE | + QI_IWD_TYPE; + desc[1].qw0 =3D QI_EIOTLB_PASID(pasid) | + QI_EIOTLB_DID(did) | + QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | + QI_EIOTLB_TYPE; + desc[2].qw0 =3D QI_DEV_EIOTLB_PASID(pasid) | + QI_DEV_EIOTLB_SID(sid) | + QI_DEV_EIOTLB_QDEP(qdep) | + QI_DEIOTLB_TYPE | + QI_DEV_IOTLB_PFSID(info->pfsid); +qi_retry: + reinit_completion(&iommu->prq_complete); + qi_submit_sync(iommu, desc, 3, QI_OPT_WAIT_DRAIN); + if (readl(iommu->reg + DMAR_PRS_REG) & DMA_PRS_PRO) { + wait_for_completion(&iommu->prq_complete); + goto qi_retry; + } +} + + +static bool is_canonical_address(u64 addr) +{ + int shift =3D 64 - (__VIRTUAL_MASK_SHIFT + 1); + long saddr =3D (long) addr; + + return (((saddr << shift) >> shift) =3D=3D saddr); +} + +static void handle_bad_prq_event(struct intel_iommu *iommu, + struct page_req_dsc *req, int result) +{ + struct qi_desc desc =3D { }; + + pr_err("%s: Invalid page request: %08llx %08llx\n", + iommu->name, ((unsigned long long *)req)[0], + ((unsigned long long *)req)[1]); + + if (!req->lpig) + return; + + desc.qw0 =3D QI_PGRP_PASID(req->pasid) | + QI_PGRP_DID(req->rid) | + QI_PGRP_PASID_P(req->pasid_present) | + QI_PGRP_RESP_CODE(result) | + QI_PGRP_RESP_TYPE; + desc.qw1 =3D QI_PGRP_IDX(req->prg_index) | + QI_PGRP_LPIG(req->lpig); + + qi_submit_sync(iommu, &desc, 1, 0); +} + +static int prq_to_iommu_prot(struct page_req_dsc *req) +{ + int prot =3D 0; + + if (req->rd_req) + prot |=3D IOMMU_FAULT_PERM_READ; + if (req->wr_req) + prot |=3D IOMMU_FAULT_PERM_WRITE; + if (req->exe_req) + prot |=3D IOMMU_FAULT_PERM_EXEC; + if (req->pm_req) + prot |=3D IOMMU_FAULT_PERM_PRIV; + + return prot; +} + +static void intel_prq_report(struct intel_iommu *iommu, struct device *dev, + struct page_req_dsc *desc) +{ + struct iopf_fault event =3D { }; + + /* Fill in event data for device specific processing */ + event.fault.type =3D IOMMU_FAULT_PAGE_REQ; + event.fault.prm.addr =3D (u64)desc->addr << VTD_PAGE_SHIFT; + event.fault.prm.pasid =3D desc->pasid; + event.fault.prm.grpid =3D desc->prg_index; + event.fault.prm.perm =3D prq_to_iommu_prot(desc); + + if (desc->lpig) + event.fault.prm.flags |=3D IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE; + if (desc->pasid_present) { + event.fault.prm.flags |=3D IOMMU_FAULT_PAGE_REQUEST_PASID_VALID; + event.fault.prm.flags |=3D IOMMU_FAULT_PAGE_RESPONSE_NEEDS_PASID; + } + + iommu_report_device_fault(dev, &event); +} + +static irqreturn_t prq_event_thread(int irq, void *d) +{ + struct intel_iommu *iommu =3D d; + struct page_req_dsc *req; + int head, tail, handled; + struct device *dev; + u64 address; + + /* + * Clear PPR bit before reading head/tail registers, to ensure that + * we get a new interrupt if needed. + */ + writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG); + + tail =3D dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK; + head =3D dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK; + handled =3D (head !=3D tail); + while (head !=3D tail) { + req =3D &iommu->prq[head / sizeof(*req)]; + address =3D (u64)req->addr << VTD_PAGE_SHIFT; + + if (unlikely(!req->pasid_present)) { + pr_err("IOMMU: %s: Page request without PASID\n", + iommu->name); +bad_req: + handle_bad_prq_event(iommu, req, QI_RESP_INVALID); + goto prq_advance; + } + + if (unlikely(!is_canonical_address(address))) { + pr_err("IOMMU: %s: Address is not canonical\n", + iommu->name); + goto bad_req; + } + + if (unlikely(req->pm_req && (req->rd_req | req->wr_req))) { + pr_err("IOMMU: %s: Page request in Privilege Mode\n", + iommu->name); + goto bad_req; + } + + if (unlikely(req->exe_req && req->rd_req)) { + pr_err("IOMMU: %s: Execution request not supported\n", + iommu->name); + goto bad_req; + } + + /* Drop Stop Marker message. No need for a response. */ + if (unlikely(req->lpig && !req->rd_req && !req->wr_req)) + goto prq_advance; + + /* + * If prq is to be handled outside iommu driver via receiver of + * the fault notifiers, we skip the page response here. + */ + mutex_lock(&iommu->iopf_lock); + dev =3D device_rbtree_find(iommu, req->rid); + if (!dev) { + mutex_unlock(&iommu->iopf_lock); + goto bad_req; + } + + intel_prq_report(iommu, dev, req); + trace_prq_report(iommu, dev, req->qw_0, req->qw_1, + req->qw_2, req->qw_3, + iommu->prq_seq_number++); + mutex_unlock(&iommu->iopf_lock); +prq_advance: + head =3D (head + sizeof(*req)) & PRQ_RING_MASK; + } + + dmar_writeq(iommu->reg + DMAR_PQH_REG, tail); + + /* + * Clear the page request overflow bit and wake up all threads that + * are waiting for the completion of this handling. + */ + if (readl(iommu->reg + DMAR_PRS_REG) & DMA_PRS_PRO) { + pr_info_ratelimited("IOMMU: %s: PRQ overflow detected\n", + iommu->name); + head =3D dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK; + tail =3D dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK; + if (head =3D=3D tail) { + iopf_queue_discard_partial(iommu->iopf_queue); + writel(DMA_PRS_PRO, iommu->reg + DMAR_PRS_REG); + pr_info_ratelimited("IOMMU: %s: PRQ overflow cleared", + iommu->name); + } + } + + if (!completion_done(&iommu->prq_complete)) + complete(&iommu->prq_complete); + + return IRQ_RETVAL(handled); +} + +int intel_enable_prq(struct intel_iommu *iommu) +{ + struct iopf_queue *iopfq; + int irq, ret; + + iommu->prq =3D iommu_alloc_pages_node(iommu->node, GFP_KERNEL, PRQ_ORDER); + if (!iommu->prq) { + pr_warn("IOMMU: %s: Failed to allocate page request queue\n", + iommu->name); + return -ENOMEM; + } + + irq =3D dmar_alloc_hwirq(IOMMU_IRQ_ID_OFFSET_PRQ + iommu->seq_id, iommu->= node, iommu); + if (irq <=3D 0) { + pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n", + iommu->name); + ret =3D -EINVAL; + goto free_prq; + } + iommu->pr_irq =3D irq; + + snprintf(iommu->iopfq_name, sizeof(iommu->iopfq_name), + "dmar%d-iopfq", iommu->seq_id); + iopfq =3D iopf_queue_alloc(iommu->iopfq_name); + if (!iopfq) { + pr_err("IOMMU: %s: Failed to allocate iopf queue\n", iommu->name); + ret =3D -ENOMEM; + goto free_hwirq; + } + iommu->iopf_queue =3D iopfq; + + snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->s= eq_id); + + ret =3D request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT, + iommu->prq_name, iommu); + if (ret) { + pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n", + iommu->name); + goto free_iopfq; + } + dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL); + dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL); + dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORD= ER); + + init_completion(&iommu->prq_complete); + + return 0; + +free_iopfq: + iopf_queue_free(iommu->iopf_queue); + iommu->iopf_queue =3D NULL; +free_hwirq: + dmar_free_hwirq(irq); + iommu->pr_irq =3D 0; +free_prq: + iommu_free_pages(iommu->prq, PRQ_ORDER); + iommu->prq =3D NULL; + + return ret; +} + +int intel_finish_prq(struct intel_iommu *iommu) +{ + dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL); + dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL); + dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL); + + if (iommu->pr_irq) { + free_irq(iommu->pr_irq, iommu); + dmar_free_hwirq(iommu->pr_irq); + iommu->pr_irq =3D 0; + } + + if (iommu->iopf_queue) { + iopf_queue_free(iommu->iopf_queue); + iommu->iopf_queue =3D NULL; + } + + iommu_free_pages(iommu->prq, PRQ_ORDER); + iommu->prq =3D NULL; + + return 0; +} + +void intel_page_response(struct device *dev, struct iopf_fault *evt, + struct iommu_page_response *msg) +{ + struct device_domain_info *info =3D dev_iommu_priv_get(dev); + struct intel_iommu *iommu =3D info->iommu; + u8 bus =3D info->bus, devfn =3D info->devfn; + struct iommu_fault_page_request *prm; + struct qi_desc desc; + bool pasid_present; + bool last_page; + u16 sid; + + prm =3D &evt->fault.prm; + sid =3D PCI_DEVID(bus, devfn); + pasid_present =3D prm->flags & IOMMU_FAULT_PAGE_REQUEST_PASID_VALID; + last_page =3D prm->flags & IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE; + + desc.qw0 =3D QI_PGRP_PASID(prm->pasid) | QI_PGRP_DID(sid) | + QI_PGRP_PASID_P(pasid_present) | + QI_PGRP_RESP_CODE(msg->code) | + QI_PGRP_RESP_TYPE; + desc.qw1 =3D QI_PGRP_IDX(prm->grpid) | QI_PGRP_LPIG(last_page); + desc.qw2 =3D 0; + desc.qw3 =3D 0; + + qi_submit_sync(iommu, &desc, 1, 0); +} + diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c index 0e3a9b38bef2..6ab7d9d03d3d 100644 --- a/drivers/iommu/intel/svm.c +++ b/drivers/iommu/intel/svm.c @@ -25,92 +25,6 @@ #include "../iommu-pages.h" #include "trace.h" =20 -static irqreturn_t prq_event_thread(int irq, void *d); - -int intel_svm_enable_prq(struct intel_iommu *iommu) -{ - struct iopf_queue *iopfq; - int irq, ret; - - iommu->prq =3D iommu_alloc_pages_node(iommu->node, GFP_KERNEL, PRQ_ORDER); - if (!iommu->prq) { - pr_warn("IOMMU: %s: Failed to allocate page request queue\n", - iommu->name); - return -ENOMEM; - } - - irq =3D dmar_alloc_hwirq(IOMMU_IRQ_ID_OFFSET_PRQ + iommu->seq_id, iommu->= node, iommu); - if (irq <=3D 0) { - pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n", - iommu->name); - ret =3D -EINVAL; - goto free_prq; - } - iommu->pr_irq =3D irq; - - snprintf(iommu->iopfq_name, sizeof(iommu->iopfq_name), - "dmar%d-iopfq", iommu->seq_id); - iopfq =3D iopf_queue_alloc(iommu->iopfq_name); - if (!iopfq) { - pr_err("IOMMU: %s: Failed to allocate iopf queue\n", iommu->name); - ret =3D -ENOMEM; - goto free_hwirq; - } - iommu->iopf_queue =3D iopfq; - - snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->s= eq_id); - - ret =3D request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT, - iommu->prq_name, iommu); - if (ret) { - pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n", - iommu->name); - goto free_iopfq; - } - dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL); - dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL); - dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORD= ER); - - init_completion(&iommu->prq_complete); - - return 0; - -free_iopfq: - iopf_queue_free(iommu->iopf_queue); - iommu->iopf_queue =3D NULL; -free_hwirq: - dmar_free_hwirq(irq); - iommu->pr_irq =3D 0; -free_prq: - iommu_free_pages(iommu->prq, PRQ_ORDER); - iommu->prq =3D NULL; - - return ret; -} - -int intel_svm_finish_prq(struct intel_iommu *iommu) -{ - dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL); - dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL); - dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL); - - if (iommu->pr_irq) { - free_irq(iommu->pr_irq, iommu); - dmar_free_hwirq(iommu->pr_irq); - iommu->pr_irq =3D 0; - } - - if (iommu->iopf_queue) { - iopf_queue_free(iommu->iopf_queue); - iommu->iopf_queue =3D NULL; - } - - iommu_free_pages(iommu->prq, PRQ_ORDER); - iommu->prq =3D NULL; - - return 0; -} - void intel_svm_check(struct intel_iommu *iommu) { if (!pasid_supported(iommu)) @@ -237,317 +151,6 @@ static int intel_svm_set_dev_pasid(struct iommu_domai= n *domain, return ret; } =20 -/* Page request queue descriptor */ -struct page_req_dsc { - union { - struct { - u64 type:8; - u64 pasid_present:1; - u64 rsvd:7; - u64 rid:16; - u64 pasid:20; - u64 exe_req:1; - u64 pm_req:1; - u64 rsvd2:10; - }; - u64 qw_0; - }; - union { - struct { - u64 rd_req:1; - u64 wr_req:1; - u64 lpig:1; - u64 prg_index:9; - u64 addr:52; - }; - u64 qw_1; - }; - u64 qw_2; - u64 qw_3; -}; - -static bool is_canonical_address(u64 addr) -{ - int shift =3D 64 - (__VIRTUAL_MASK_SHIFT + 1); - long saddr =3D (long) addr; - - return (((saddr << shift) >> shift) =3D=3D saddr); -} - -/** - * intel_drain_pasid_prq - Drain page requests and responses for a pasid - * @dev: target device - * @pasid: pasid for draining - * - * Drain all pending page requests and responses related to @pasid in both - * software and hardware. This is supposed to be called after the device - * driver has stopped DMA, the pasid entry has been cleared, and both IOTLB - * and DevTLB have been invalidated. - * - * It waits until all pending page requests for @pasid in the page fault - * queue are completed by the prq handling thread. Then follow the steps - * described in VT-d spec CH7.10 to drain all page requests and page - * responses pending in the hardware. - */ -void intel_drain_pasid_prq(struct device *dev, u32 pasid) -{ - struct device_domain_info *info; - struct dmar_domain *domain; - struct intel_iommu *iommu; - struct qi_desc desc[3]; - struct pci_dev *pdev; - int head, tail; - u16 sid, did; - int qdep; - - info =3D dev_iommu_priv_get(dev); - if (WARN_ON(!info || !dev_is_pci(dev))) - return; - - if (!info->pri_enabled) - return; - - iommu =3D info->iommu; - domain =3D info->domain; - pdev =3D to_pci_dev(dev); - sid =3D PCI_DEVID(info->bus, info->devfn); - did =3D domain_id_iommu(domain, iommu); - qdep =3D pci_ats_queue_depth(pdev); - - /* - * Check and wait until all pending page requests in the queue are - * handled by the prq handling thread. - */ -prq_retry: - reinit_completion(&iommu->prq_complete); - tail =3D dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK; - head =3D dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK; - while (head !=3D tail) { - struct page_req_dsc *req; - - req =3D &iommu->prq[head / sizeof(*req)]; - if (!req->pasid_present || req->pasid !=3D pasid) { - head =3D (head + sizeof(*req)) & PRQ_RING_MASK; - continue; - } - - wait_for_completion(&iommu->prq_complete); - goto prq_retry; - } - - iopf_queue_flush_dev(dev); - - /* - * Perform steps described in VT-d spec CH7.10 to drain page - * requests and responses in hardware. - */ - memset(desc, 0, sizeof(desc)); - desc[0].qw0 =3D QI_IWD_STATUS_DATA(QI_DONE) | - QI_IWD_FENCE | - QI_IWD_TYPE; - desc[1].qw0 =3D QI_EIOTLB_PASID(pasid) | - QI_EIOTLB_DID(did) | - QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | - QI_EIOTLB_TYPE; - desc[2].qw0 =3D QI_DEV_EIOTLB_PASID(pasid) | - QI_DEV_EIOTLB_SID(sid) | - QI_DEV_EIOTLB_QDEP(qdep) | - QI_DEIOTLB_TYPE | - QI_DEV_IOTLB_PFSID(info->pfsid); -qi_retry: - reinit_completion(&iommu->prq_complete); - qi_submit_sync(iommu, desc, 3, QI_OPT_WAIT_DRAIN); - if (readl(iommu->reg + DMAR_PRS_REG) & DMA_PRS_PRO) { - wait_for_completion(&iommu->prq_complete); - goto qi_retry; - } -} - -static int prq_to_iommu_prot(struct page_req_dsc *req) -{ - int prot =3D 0; - - if (req->rd_req) - prot |=3D IOMMU_FAULT_PERM_READ; - if (req->wr_req) - prot |=3D IOMMU_FAULT_PERM_WRITE; - if (req->exe_req) - prot |=3D IOMMU_FAULT_PERM_EXEC; - if (req->pm_req) - prot |=3D IOMMU_FAULT_PERM_PRIV; - - return prot; -} - -static void intel_svm_prq_report(struct intel_iommu *iommu, struct device = *dev, - struct page_req_dsc *desc) -{ - struct iopf_fault event =3D { }; - - /* Fill in event data for device specific processing */ - event.fault.type =3D IOMMU_FAULT_PAGE_REQ; - event.fault.prm.addr =3D (u64)desc->addr << VTD_PAGE_SHIFT; - event.fault.prm.pasid =3D desc->pasid; - event.fault.prm.grpid =3D desc->prg_index; - event.fault.prm.perm =3D prq_to_iommu_prot(desc); - - if (desc->lpig) - event.fault.prm.flags |=3D IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE; - if (desc->pasid_present) { - event.fault.prm.flags |=3D IOMMU_FAULT_PAGE_REQUEST_PASID_VALID; - event.fault.prm.flags |=3D IOMMU_FAULT_PAGE_RESPONSE_NEEDS_PASID; - } - - iommu_report_device_fault(dev, &event); -} - -static void handle_bad_prq_event(struct intel_iommu *iommu, - struct page_req_dsc *req, int result) -{ - struct qi_desc desc =3D { }; - - pr_err("%s: Invalid page request: %08llx %08llx\n", - iommu->name, ((unsigned long long *)req)[0], - ((unsigned long long *)req)[1]); - - if (!req->lpig) - return; - - desc.qw0 =3D QI_PGRP_PASID(req->pasid) | - QI_PGRP_DID(req->rid) | - QI_PGRP_PASID_P(req->pasid_present) | - QI_PGRP_RESP_CODE(result) | - QI_PGRP_RESP_TYPE; - desc.qw1 =3D QI_PGRP_IDX(req->prg_index) | - QI_PGRP_LPIG(req->lpig); - - qi_submit_sync(iommu, &desc, 1, 0); -} - -static irqreturn_t prq_event_thread(int irq, void *d) -{ - struct intel_iommu *iommu =3D d; - struct page_req_dsc *req; - int head, tail, handled; - struct device *dev; - u64 address; - - /* - * Clear PPR bit before reading head/tail registers, to ensure that - * we get a new interrupt if needed. - */ - writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG); - - tail =3D dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK; - head =3D dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK; - handled =3D (head !=3D tail); - while (head !=3D tail) { - req =3D &iommu->prq[head / sizeof(*req)]; - address =3D (u64)req->addr << VTD_PAGE_SHIFT; - - if (unlikely(!req->pasid_present)) { - pr_err("IOMMU: %s: Page request without PASID\n", - iommu->name); -bad_req: - handle_bad_prq_event(iommu, req, QI_RESP_INVALID); - goto prq_advance; - } - - if (unlikely(!is_canonical_address(address))) { - pr_err("IOMMU: %s: Address is not canonical\n", - iommu->name); - goto bad_req; - } - - if (unlikely(req->pm_req && (req->rd_req | req->wr_req))) { - pr_err("IOMMU: %s: Page request in Privilege Mode\n", - iommu->name); - goto bad_req; - } - - if (unlikely(req->exe_req && req->rd_req)) { - pr_err("IOMMU: %s: Execution request not supported\n", - iommu->name); - goto bad_req; - } - - /* Drop Stop Marker message. No need for a response. */ - if (unlikely(req->lpig && !req->rd_req && !req->wr_req)) - goto prq_advance; - - /* - * If prq is to be handled outside iommu driver via receiver of - * the fault notifiers, we skip the page response here. - */ - mutex_lock(&iommu->iopf_lock); - dev =3D device_rbtree_find(iommu, req->rid); - if (!dev) { - mutex_unlock(&iommu->iopf_lock); - goto bad_req; - } - - intel_svm_prq_report(iommu, dev, req); - trace_prq_report(iommu, dev, req->qw_0, req->qw_1, - req->qw_2, req->qw_3, - iommu->prq_seq_number++); - mutex_unlock(&iommu->iopf_lock); -prq_advance: - head =3D (head + sizeof(*req)) & PRQ_RING_MASK; - } - - dmar_writeq(iommu->reg + DMAR_PQH_REG, tail); - - /* - * Clear the page request overflow bit and wake up all threads that - * are waiting for the completion of this handling. - */ - if (readl(iommu->reg + DMAR_PRS_REG) & DMA_PRS_PRO) { - pr_info_ratelimited("IOMMU: %s: PRQ overflow detected\n", - iommu->name); - head =3D dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK; - tail =3D dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK; - if (head =3D=3D tail) { - iopf_queue_discard_partial(iommu->iopf_queue); - writel(DMA_PRS_PRO, iommu->reg + DMAR_PRS_REG); - pr_info_ratelimited("IOMMU: %s: PRQ overflow cleared", - iommu->name); - } - } - - if (!completion_done(&iommu->prq_complete)) - complete(&iommu->prq_complete); - - return IRQ_RETVAL(handled); -} - -void intel_svm_page_response(struct device *dev, struct iopf_fault *evt, - struct iommu_page_response *msg) -{ - struct device_domain_info *info =3D dev_iommu_priv_get(dev); - struct intel_iommu *iommu =3D info->iommu; - u8 bus =3D info->bus, devfn =3D info->devfn; - struct iommu_fault_page_request *prm; - struct qi_desc desc; - bool pasid_present; - bool last_page; - u16 sid; - - prm =3D &evt->fault.prm; - sid =3D PCI_DEVID(bus, devfn); - pasid_present =3D prm->flags & IOMMU_FAULT_PAGE_REQUEST_PASID_VALID; - last_page =3D prm->flags & IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE; - - desc.qw0 =3D QI_PGRP_PASID(prm->pasid) | QI_PGRP_DID(sid) | - QI_PGRP_PASID_P(pasid_present) | - QI_PGRP_RESP_CODE(msg->code) | - QI_PGRP_RESP_TYPE; - desc.qw1 =3D QI_PGRP_IDX(prm->grpid) | QI_PGRP_LPIG(last_page); - desc.qw2 =3D 0; - desc.qw3 =3D 0; - - qi_submit_sync(iommu, &desc, 1, 0); -} - static void intel_svm_domain_free(struct iommu_domain *domain) { struct dmar_domain *dmar_domain =3D to_dmar_domain(domain); --=20 2.43.0 From nobody Fri Dec 19 15:19:53 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33AF41D79B2; Wed, 4 Sep 2024 13:18:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725455893; cv=none; b=rryD6evKYKDUwzpz62eG0oVovMOfxNtXEMj413FC15gKFED+n6jusD+E86G62t0bwk38/7jkDJXUvhEL7gATqbaL1KU7+XMyFY3XKJfaTLA4Gh1cRvR4M63ILMPRaAum6oYilbaS3neMkDZN4vLXUbZ7lBx4SamvfxooLBpZ5AI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725455893; c=relaxed/simple; bh=DahTmE+cw2GuBIr/HQoJZM14WQAlTGLxnm0oWWFYEwE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Lw+Z6rCydvrKr+GDKagTZ9p0YR/vM117XX3a46ACQx2Xq3WyZr2eWG0sKcx/VNty7KCZhBjHRH3O9GrUsjtM51iE4YrFh3ZDNcmV0Sik3604g+dq9JS8y3oOKxmA5aZ7/TKdZokYi6gaws8+M4INbE3zB9rKOtWOUJFwgOKqmIs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fyviVQ3P; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fyviVQ3P" Received: by smtp.kernel.org (Postfix) with ESMTPS id D6369C4CEC9; Wed, 4 Sep 2024 13:18:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725455892; bh=DahTmE+cw2GuBIr/HQoJZM14WQAlTGLxnm0oWWFYEwE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=fyviVQ3PMdptRUY4nYPnRxRIktYFE2Qk/a4SLu0y9jP6eV2J4+P04A+/sB1DWwpML 455u2U13Z/+ZgxdOr8LhIR1I9IDsw+03tos3Qy36UlgsMzmEbvRNb9zEtgMZZrHK0n p/aOGr779kY4bUjzCcLcJl47h99iQUMzaT5FSsHrh2Ao3pkLT1Z2QnbLhWO8Uwyd9g amqQ9GeQl9r8MQ/EkI2QSVitOtGiM38pWXz7MFnsq+nE9WPqXU+KfMy+X39SfGHRpa xjZ8NCBDY7RC+cAZw7WhBJwAUU6AE2kyece8s1m9FFHAMIxtAdLVMaB5H2Akk84fLg pCRdWzHELbRoQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C93F6CD4849; Wed, 4 Sep 2024 13:18:12 +0000 (UTC) From: Joel Granados via B4 Relay Date: Wed, 04 Sep 2024 15:17:13 +0200 Subject: [PATCH 2/6] iommu/vt-d: Remove the pasid present check in prq_event_thread Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240904-jag-iopfv8-v1-2-e3549920adf3@samsung.com> References: <20240904-jag-iopfv8-v1-0-e3549920adf3@samsung.com> In-Reply-To: <20240904-jag-iopfv8-v1-0-e3549920adf3@samsung.com> To: David Woodhouse , Lu Baolu , Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian , Klaus Jensen Cc: linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Joel Granados , Klaus Jensen X-Mailer: b4 0.15-dev-00a43 X-Developer-Signature: v=1; a=openpgp-sha256; l=1351; i=j.granados@samsung.com; h=from:subject:message-id; bh=FD3UiP6NJxmTUYvjmWxZFWuSigYaHG1wzRA5qCg/pTc=; b=owJ4nAHtARL+kA0DAAoBupfNUreWQU8ByyZiAGbYXhC3rVks+YQxMld3lqz3PtEbzx3YP/0tv SlyGftf39WU5YkBswQAAQoAHRYhBK5HCVcl5jElzssnkLqXzVK3lkFPBQJm2F4QAAoJELqXzVK3 lkFPT/AL/Rh3zXdT5UQaqGGi3xhl12hEX+DL8xYzus7bNkXGZIArVREL9Ww4N4fULNqSIcCJ46y EJUdiCBblIo79ZpC+jI45GUI8KDkChndRmfyHuwEzJC7mCuoHuShJff4c2xVFsjE4858NTA5pnV hA+wxIXDBRYNOt0e+Br+BAmbiyVRQ5bN259pkoqZ0nG6fQ4f+iKXen1Dsc10gr8BV+3xgxDf/eX YmEIKUO/135r3JdqWkCp6ixA1eAwcEFqMcdYbLVhT/o6Fe1d0slIhx/1KILIMPXcSAQ2WtuFwSz zkpx+VHDG7IH2RMAn+Hsq/mbTgBWDUmGJ64K8GWGmbnx0IF/IKpTkvQdDYLC342KrfZFByeUmEG 6mBeA8HC/9L3n6/5E7iPlvItL/aWmYzHJKyjQokz2Ipxwqy5a0uGbqrQBVze9Q8axKTvclOZL1Q R+/islwVuLf4Wycl7PJQ0tDt1nZDninu9SQOJnLzF5qVDxbwZbqlmAZv5s4qoC9LBr0pJZYzC96 Hs= X-Developer-Key: i=j.granados@samsung.com; a=openpgp; fpr=F1F8E46D30F0F6C4A45FF4465895FAAC338C6E77 X-Endpoint-Received: by B4 Relay for j.granados@samsung.com/default with auth_id=70 X-Original-From: Joel Granados Reply-To: j.granados@samsung.com From: Klaus Jensen PASID is not strictly needed when handling a PRQ event; remove the check for the pasid present bit in the request. This change was not included in the creation of prq.c to emphasize the change in capability checks when handing PRQ events. Signed-off-by: Klaus Jensen Signed-off-by: Joel Granados --- drivers/iommu/intel/prq.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/iommu/intel/prq.c b/drivers/iommu/intel/prq.c index 3376f60082b5..5f2d01a9aa11 100644 --- a/drivers/iommu/intel/prq.c +++ b/drivers/iommu/intel/prq.c @@ -221,18 +221,12 @@ static irqreturn_t prq_event_thread(int irq, void *d) req =3D &iommu->prq[head / sizeof(*req)]; address =3D (u64)req->addr << VTD_PAGE_SHIFT; =20 - if (unlikely(!req->pasid_present)) { - pr_err("IOMMU: %s: Page request without PASID\n", - iommu->name); -bad_req: - handle_bad_prq_event(iommu, req, QI_RESP_INVALID); - goto prq_advance; - } - if (unlikely(!is_canonical_address(address))) { pr_err("IOMMU: %s: Address is not canonical\n", iommu->name); - goto bad_req; +bad_req: + handle_bad_prq_event(iommu, req, QI_RESP_INVALID); + goto prq_advance; } =20 if (unlikely(req->pm_req && (req->rd_req | req->wr_req))) { --=20 2.43.0 From nobody Fri Dec 19 15:19:53 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C73E1DA2ED; Wed, 4 Sep 2024 13:18:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725455893; cv=none; b=SYry1jajeiVQuunMkhg+ImykvtkLkGv904Cl+zDJ8fwiQ9y1t7BnleA5v2DtlnK4hLSYquynnvebED6mbHemheeDMBoCOGmvGg+M6Ohu5wCVWcx3rYuRABMU7Nzr7WEsr/irj1sHc+G2AVuL22WLZfgzwCGoiao90eyOshnhM2A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725455893; c=relaxed/simple; bh=oGH1FuTsaRy7oacITrQ+mPPquktRVskCF8uOQBlSApM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=d/b40TKUmV8nO85KQ2Vf+UfCqsp/5qoZuc1bUeiZOeMcK24pJb4mD08XOUUfFn3updPkb1Kw15UJKjekI7KVBcaKoYyMq6k4n9pLr0c68q1BNguItctvEFPf5cbLKPjdzpQKw6/XRg5DTG6MEk99v/vvD/xBepOFR+I2MF1NqXQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WJsG7zy3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WJsG7zy3" Received: by smtp.kernel.org (Postfix) with ESMTPS id E2CDDC4CECA; Wed, 4 Sep 2024 13:18:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725455892; bh=oGH1FuTsaRy7oacITrQ+mPPquktRVskCF8uOQBlSApM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=WJsG7zy3iuBML+5ImuuDCT7Dg+tZ78VAi6xVGS7AgqkRDnjRDEBgxquUls5eem5eg CPEQgNrGTthf9nGIG6t4xMfaolLVU+CDD8Mc45c2B3F36h/wP512gxj2qDwd7PH6Oj fVqeDKPgrWER4DLczXx+rbMZ010cS9oJj2MsPkJdtVz2hPe+w82ZwnG0iGAk/5r8XN 8WbiaCiBL6EfZmCxMd/30vvJmX7Mh/9PpCSPDXypNB/4SHIpHeP93k78R8D1za4Jao MNsIPqy9R2+ZZk7oQHHtyIYjZyNVU4073IWECqSDwVbYHPNg8zXFak7O0a6VKWOZA1 Ejkz0a4h2yBNQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9052CA0ED3; Wed, 4 Sep 2024 13:18:12 +0000 (UTC) From: Joel Granados via B4 Relay Date: Wed, 04 Sep 2024 15:17:14 +0200 Subject: [PATCH 3/6] iommu: kconfig: Move IOMMU_IOPF into INTEL_IOMMU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240904-jag-iopfv8-v1-3-e3549920adf3@samsung.com> References: <20240904-jag-iopfv8-v1-0-e3549920adf3@samsung.com> In-Reply-To: <20240904-jag-iopfv8-v1-0-e3549920adf3@samsung.com> To: David Woodhouse , Lu Baolu , Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian , Klaus Jensen Cc: linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Joel Granados X-Mailer: b4 0.15-dev-00a43 X-Developer-Signature: v=1; a=openpgp-sha256; l=998; i=j.granados@samsung.com; h=from:subject:message-id; bh=A1IcN/yt0t1BbWgqjM2qPuJqNqel/ygqpz+aUMrV/hQ=; b=owJ4nAHtARL+kA0DAAoBupfNUreWQU8ByyZiAGbYXhESVKYlERtao5dlV515lqqcRZZFHelXY IAhr15mwVk2UIkBswQAAQoAHRYhBK5HCVcl5jElzssnkLqXzVK3lkFPBQJm2F4RAAoJELqXzVK3 lkFPD3wL/1YW2YIlo7fV0fDqWc+PvCSoS1xKWR2aLxKPa/kZBuc/SrFovAUFt9jr8hh4cxKSjNW fx4LcDnAKEEKx7dOM056DK9NypvbWuzHu4i7JAJV35O2Yew6c6OUWVyUEIe+VHHtj3Bj7Uy4imq /VQ8+h3WwXUNX+CwGpOocOf1olwaf+xxTbkVxKIJYZ4yIZndzLzYFnk2KXeMFT5+CfixqqvYuGf iEdCEpRYRw3A38/ONabQ/rkU/fiE6NmrlPkIX9MiPH7/vtyljjhEGflawkcfOug04hT497LTdJi JjJXAFmwZera9G9nPjwN5NC/qhrd6W4bGAHBmOg9gMgSq+Y6Ldjys6uzcMyhzAvwJzWQXGVT6dc 2st5xWJmxllTfpocVqvn5rQbHULshC5FDOX9YehAmzw7i5sQGFE+SkoNrButwGq5CuO6XMBqcad du6YYUVoOGpA3LIslfWNxezI4PhA55bTdsLzfnTemHi0OZvtRNAPmzKTiB/yjH2Izro2Xi00Rd6 kA= X-Developer-Key: i=j.granados@samsung.com; a=openpgp; fpr=F1F8E46D30F0F6C4A45FF4465895FAAC338C6E77 X-Endpoint-Received: by B4 Relay for j.granados@samsung.com/default with auth_id=70 X-Original-From: Joel Granados Reply-To: j.granados@samsung.com From: Joel Granados Move IOMMU_IOPF from under INTEL_IOMMU_SVM into INTEL_IOMMU. This certifies that the core intel iommu utilizes the IOPF library functions, independent of the INTEL_IOMMU_SVM config. Signed-off-by: Joel Granados --- drivers/iommu/intel/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/intel/Kconfig b/drivers/iommu/intel/Kconfig index f52fb39c968e..2888671c9278 100644 --- a/drivers/iommu/intel/Kconfig +++ b/drivers/iommu/intel/Kconfig @@ -15,6 +15,7 @@ config INTEL_IOMMU select DMA_OPS select IOMMU_API select IOMMU_IOVA + select IOMMU_IOPF select IOMMUFD_DRIVER if IOMMUFD select NEED_DMA_MAP_STATE select DMAR_TABLE @@ -51,7 +52,6 @@ config INTEL_IOMMU_SVM depends on X86_64 select MMU_NOTIFIER select IOMMU_SVA - select IOMMU_IOPF help Shared Virtual Memory (SVM) provides a facility for devices to access DMA resources through process address space by --=20 2.43.0 From nobody Fri Dec 19 15:19:53 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C78C1DA2F1; Wed, 4 Sep 2024 13:18:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725455893; cv=none; b=oNJgPG/wVgy5sDyXGlWPYkhyZ1MU5G/ZqMKCmxSaKTj+ouJh/JZTwDati6VnBgnhDC4Ix5LccdGS5TkF+UUkviq7mfutO4FVMkQthTB5YOJXM6M6KeRv+W0OjrDc/0I0nOZsQNw/1I/3oNKC9MEKGJyWqjP8OymAC8APiF9yDU4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725455893; c=relaxed/simple; bh=yI/YdEzUxnbqQlsPHNM+E/+LIgmQwvyu/UUnjDxNwS8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JWTq+0J44oBV20/LwqNJwzwAcGmvEc1FfP0O3TykuQPmgsaMxKV/0UBxDp4Z/fdWRiqjYSPKd/RzwGVfiB0xJL/IT7xTv67kx6UokQelM+4ETxIntE10WoY0TSmTeqTYDyH8CPGaJvgPxt+mSgz9U9IAu9+8/xt23Rlylf3M8c8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=spwhcUuS; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="spwhcUuS" Received: by smtp.kernel.org (Postfix) with ESMTPS id EE828C4CECB; Wed, 4 Sep 2024 13:18:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725455893; bh=yI/YdEzUxnbqQlsPHNM+E/+LIgmQwvyu/UUnjDxNwS8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=spwhcUuSm7L1C7L9DHgC5yryjkJG6KKMLMPRSK19MTijkUF6TVYHcPwGxHe+IsenI lJ6C9BP694YPCQdWAD8IaBHmvts2wgHBhwzlEN1smBPZiRg2iunqh3JhmoWrMmHOzh frM9+c0jdJ1EWmNOIoaFG63h/CrSqw4oAWKkq9sdk8gSFCKkw8U2Ow+bR7hKAeuXuL kSBS+nyPZPtWzH1aH2aE6RPjdspCnK1yoPlbc6jNYDKk+wlK6ndEMFO4bvWyiiK+Wd aMBcJLDA91ylKggYCexr/OWuzDdwm4CA4gQGBYUYIOyuJo8rl5jOXKN/i/z+OrfYuV Q0+pV3rW3TxVQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E55AFCD484A; Wed, 4 Sep 2024 13:18:12 +0000 (UTC) From: Joel Granados via B4 Relay Date: Wed, 04 Sep 2024 15:17:15 +0200 Subject: [PATCH 4/6] iommufd: Enable PRI when doing the iommufd_hwpt_alloc Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240904-jag-iopfv8-v1-4-e3549920adf3@samsung.com> References: <20240904-jag-iopfv8-v1-0-e3549920adf3@samsung.com> In-Reply-To: <20240904-jag-iopfv8-v1-0-e3549920adf3@samsung.com> To: David Woodhouse , Lu Baolu , Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian , Klaus Jensen Cc: linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Joel Granados X-Mailer: b4 0.15-dev-00a43 X-Developer-Signature: v=1; a=openpgp-sha256; l=1694; i=j.granados@samsung.com; h=from:subject:message-id; bh=DxEbBmnkeSWlQ/5MEXCH0l7yNP6fyq/9U3DrRBtODeQ=; b=owJ4nAHtARL+kA0DAAoBupfNUreWQU8ByyZiAGbYXhHUVwfr9e9QLrNk/WkXeQbulJ6RSgyT2 TPZKG7vlQIWu4kBswQAAQoAHRYhBK5HCVcl5jElzssnkLqXzVK3lkFPBQJm2F4RAAoJELqXzVK3 lkFPyWwL/AmecYUT1fby4BgodpsNYKnXazKHpsIXy7YsDjNlU3xf/fcPN3vtCegwhCJsA+lwZ04 6tW13HMXpIYATphufyLRh9pT1Kjj8Pbo2TAbx98TBn1z3ZcJAxYjN9Tvw/SZ5iCuBzl46YaRbjl XcbwbRE118OhI4oRB/UlE0GPIpp0Svw/qLZybfzpz0vWr1i5kehIpMfii8p80+Uq/4cGnvxnRBh h4ATTe05nkRMIC7ERLuvHJ+7Rl9ZeyI1KyA4NlfUQVHuzDC64dvioyeBnqvDZYUbtDMvJTwBJZA 883CD6c+DsOf1fD+7Sep8lnNStsK5uEyVvQ3Y+8MITzkCosC7pODJegRaRrgtGzDH1FpiqqwdNl I6sxFj3YastLrz/YpnF4E7rimieSWRskEWrkXNmG/PcyRAbWeR2N7/K6wcIZf8RFAJLg6E/UUz7 Wck4ZyiwYZ3MOtRa6LznsKzQgUUBhZPE2hzLHz16dZoM3xHFJXTTctjVb773zTZ5nL3qZ41+OT7 lc= X-Developer-Key: i=j.granados@samsung.com; a=openpgp; fpr=F1F8E46D30F0F6C4A45FF4465895FAAC338C6E77 X-Endpoint-Received: by B4 Relay for j.granados@samsung.com/default with auth_id=70 X-Original-From: Joel Granados Reply-To: j.granados@samsung.com From: Joel Granados Add IOMMU_HWPT_FAULT_ID_VALID as part of the valid flags when doing an iommufd_hwpt_alloc allowing the use of an iommu fault allocation (iommu_fault_alloc) with the IOMMU_HWPT_ALLOC ioctl. Signed-off-by: Joel Granados --- drivers/iommu/intel/iommu.c | 3 ++- drivers/iommu/iommufd/hw_pagetable.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 5acc52c62e8c..3d1c971eb9e5 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -3718,7 +3718,8 @@ intel_iommu_domain_alloc_user(struct device *dev, u32= flags, } =20 if (flags & - (~(IOMMU_HWPT_ALLOC_NEST_PARENT | IOMMU_HWPT_ALLOC_DIRTY_TRACKING))) + (~(IOMMU_HWPT_ALLOC_NEST_PARENT | IOMMU_HWPT_ALLOC_DIRTY_TRACKING + | IOMMU_HWPT_FAULT_ID_VALID))) return ERR_PTR(-EOPNOTSUPP); if (nested_parent && !nested_supported(iommu)) return ERR_PTR(-EOPNOTSUPP); diff --git a/drivers/iommu/iommufd/hw_pagetable.c b/drivers/iommu/iommufd/h= w_pagetable.c index aefde4443671..88074e459995 100644 --- a/drivers/iommu/iommufd/hw_pagetable.c +++ b/drivers/iommu/iommufd/hw_pagetable.c @@ -107,7 +107,8 @@ iommufd_hwpt_paging_alloc(struct iommufd_ctx *ictx, str= uct iommufd_ioas *ioas, const struct iommu_user_data *user_data) { const u32 valid_flags =3D IOMMU_HWPT_ALLOC_NEST_PARENT | - IOMMU_HWPT_ALLOC_DIRTY_TRACKING; + IOMMU_HWPT_ALLOC_DIRTY_TRACKING | + IOMMU_HWPT_FAULT_ID_VALID; const struct iommu_ops *ops =3D dev_iommu_ops(idev->dev); struct iommufd_hwpt_paging *hwpt_paging; struct iommufd_hw_pagetable *hwpt; --=20 2.43.0 From nobody Fri Dec 19 15:19:53 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92BB81DB523; Wed, 4 Sep 2024 13:18:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725455893; cv=none; b=hKFg4HGb8KAA9esg0I1Q8cKIHcRDtnfR2btRXJnnoCtskivadIa9OT2Zav/AqEpIIhcOls/JJLC7QA4Yxq4L6JbJ/RvZojl+vB3xVZNm16kBlijftn/LNfYmzJBzJB5ymHEcCtcY5dyWtsJ9veFNu/90tEpAmVj9iYhGYIpR22w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725455893; c=relaxed/simple; bh=UWgbkMn/UR7qk35hkkCjrqGkuDRLwBRgx9io5zfFQAM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=X0wtaz351dft6CUThY4rci8nG9Ozb1+UYW6KSRQFDtJihR90Ox9pbNdr5DZIChfavPpKloi5CR8JojWze3kywAGMxXELnt12CvnWPF+m5ntLsukceaXb4tdG/wc1yGuLdpmscRuPZHUydiyMQuhYXh3fdR2NA/tp0gQEcevOfw4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YHrDxhvS; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YHrDxhvS" Received: by smtp.kernel.org (Postfix) with ESMTPS id 052C4C4CECE; Wed, 4 Sep 2024 13:18:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725455893; bh=UWgbkMn/UR7qk35hkkCjrqGkuDRLwBRgx9io5zfFQAM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=YHrDxhvSuBZPGMEOUdxszLH4hFZUJGd1sDfUetNoxaJZx6YZXaIWLosteY3XOEJ56 qOxRUJuASLtbeE5Xtw7pBDPyWkpIvt8tbO1DLEW7w3NTt+R9ihpyQfTWGKQWrCjPx3 fuFji01h453lUitBNlL7GW4/CBNI5Qxm8Gps2jINAu9U3sFG82CgKrWlWHmEMaASXn Xo8VdbUn2wAr5iuvOZOW+U79XoSf7JB24Jk+yEa6Bhob38hM9sb4YEerhnW7Kf9+aj mraWIeYvrbSQI/sWnZkOP8xiCHT+k0n9Z7ZjdpGHHmgVEU85/lbiYXYqLCJq8Nm9N3 RzN9yZEIT525g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id F19F1CD484C; Wed, 4 Sep 2024 13:18:12 +0000 (UTC) From: Joel Granados via B4 Relay Date: Wed, 04 Sep 2024 15:17:16 +0200 Subject: [PATCH 5/6] iommu: init pasid array while doing domain_replace and iopf is active Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240904-jag-iopfv8-v1-5-e3549920adf3@samsung.com> References: <20240904-jag-iopfv8-v1-0-e3549920adf3@samsung.com> In-Reply-To: <20240904-jag-iopfv8-v1-0-e3549920adf3@samsung.com> To: David Woodhouse , Lu Baolu , Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian , Klaus Jensen Cc: linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Joel Granados X-Mailer: b4 0.15-dev-00a43 X-Developer-Signature: v=1; a=openpgp-sha256; l=3911; i=j.granados@samsung.com; h=from:subject:message-id; bh=pU8Ysqx41tEvpDjmz62CzUVFAwe2mnVh/jqq0I7a6v8=; b=owJ4nAHtARL+kA0DAAoBupfNUreWQU8ByyZiAGbYXhL2ESnsvHmBgN6QUX2UvqogpeVAeLBju RlQvGICyARVfokBswQAAQoAHRYhBK5HCVcl5jElzssnkLqXzVK3lkFPBQJm2F4SAAoJELqXzVK3 lkFPKPEL/0W3YFk6CZ063mfvqtAhaSNefjunJndB/tIn3/8SYtcSFlkwcglU8f60FsycxaA7pQP wt5i8nC1bKuklEe+/HFO59YQP3qJrA6ksrA2GxSpimLj7zGZ+5A4T+Igv+1xPAio8xmLyDin6F8 c7hHnssgc6MnWXBt21Z+SuJHSOGH2ZZt42uGRa2dfiedbJ/R+1EASlhK7/PpjUWVcwu6m1qWLAk sUVTtQ+3/ububVeuQluvvqEoRYIQckZs/TQckdGyQiloAB0oDAC658bLVAM9XO3Z7JyAcl2bo9W x8kShMtes53jIJMB9X+new/KNrut3AXrgijUe8V6kGQsRG0sj5gWo8pkUg/CJlUy6/cMsTq708h 1QjmCnMk0UbHCJoFao7QR/UlOZhnmGzf0wwxz92yzVkTCc1DvvqqiNUSyeK9IdQoqu5Sq1jRTx6 AKweNOKGOmdB3N+t/LPplSwKiq8ku4dUY1Yf5ys7tPN/KvQsuvpxrHqGYsYKc0WD596hKRiV8o6 kw= X-Developer-Key: i=j.granados@samsung.com; a=openpgp; fpr=F1F8E46D30F0F6C4A45FF4465895FAAC338C6E77 X-Endpoint-Received: by B4 Relay for j.granados@samsung.com/default with auth_id=70 X-Original-From: Joel Granados Reply-To: j.granados@samsung.com From: Joel Granados iommu_report_device_fault expects a pasid array to have an iommu_attach_handle when a fault is detected. Add this handle when the replacing hwpt has a valid iommufd fault object. Remove it when we release ownership of the group. Signed-off-by: Joel Granados --- drivers/iommu/iommu-priv.h | 3 +++ drivers/iommu/iommu.c | 30 ++++++++++++++++++++++++++++++ drivers/iommu/iommufd/fault.c | 22 ++++++++++++++++++++++ 3 files changed, 55 insertions(+) diff --git a/drivers/iommu/iommu-priv.h b/drivers/iommu/iommu-priv.h index de5b54eaa8bf..493e501badc7 100644 --- a/drivers/iommu/iommu-priv.h +++ b/drivers/iommu/iommu-priv.h @@ -38,6 +38,9 @@ void iommu_device_unregister_bus(struct iommu_device *iom= mu, struct iommu_attach_handle *iommu_attach_handle_get(struct iommu_group *gr= oup, ioasid_t pasid, unsigned int type); +int iommu_init_pasid_array(struct iommu_domain *domain, + struct iommu_group *group, + struct iommu_attach_handle *handle); int iommu_attach_group_handle(struct iommu_domain *domain, struct iommu_group *group, struct iommu_attach_handle *handle); diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index ed6c5cb60c5a..64ae1cf571aa 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -3262,6 +3262,9 @@ EXPORT_SYMBOL_GPL(iommu_device_claim_dma_owner); =20 static void __iommu_release_dma_ownership(struct iommu_group *group) { + if (!xa_empty(&group->pasid_array)) + xa_erase(&group->pasid_array, IOMMU_NO_PASID); + if (WARN_ON(!group->owner_cnt || !group->owner || !xa_empty(&group->pasid_array))) return; @@ -3495,6 +3498,33 @@ iommu_attach_handle_get(struct iommu_group *group, i= oasid_t pasid, unsigned int } EXPORT_SYMBOL_NS_GPL(iommu_attach_handle_get, IOMMUFD_INTERNAL); =20 +/** + * iommu_init_pasid_array - Initialize pasid array in the domain group + * + * Returns 0 on success. Error code on failure + * + * An IOMMU_NO_PASID element is *NOT* replaced if there is one already the= re. + */ +int iommu_init_pasid_array(struct iommu_domain *domain, + struct iommu_group *group, + struct iommu_attach_handle *handle) +{ + int ret; + + if (handle) + handle->domain =3D domain; + + mutex_lock(&group->mutex); + ret =3D xa_insert(&group->pasid_array, IOMMU_NO_PASID, handle, GFP_KERNEL= ); + mutex_unlock(&group->mutex); + + if (ret =3D=3D -EBUSY) + ret =3D 0; + + return ret; +} +EXPORT_SYMBOL_NS_GPL(iommu_init_pasid_array, IOMMUFD_INTERNAL); + /** * iommu_attach_group_handle - Attach an IOMMU domain to an IOMMU group * @domain: IOMMU domain to attach diff --git a/drivers/iommu/iommufd/fault.c b/drivers/iommu/iommufd/fault.c index a643d5c7c535..ea7f1bf64892 100644 --- a/drivers/iommu/iommufd/fault.c +++ b/drivers/iommu/iommufd/fault.c @@ -178,6 +178,25 @@ static int __fault_domain_replace_dev(struct iommufd_d= evice *idev, return ret; } =20 +static int iommufd_init_pasid_array(struct iommu_domain *domain, + struct iommufd_device *idev) +{ + int ret; + struct iommufd_attach_handle *handle; + struct iommu_group *group =3D idev->igroup->group; + + handle =3D kzalloc(sizeof(*handle), GFP_KERNEL); + if (!handle) + return -ENOMEM; + handle->idev =3D idev; + + ret =3D iommu_init_pasid_array(domain, group, &handle->handle); + if (ret) + kfree(handle); + + return ret; +} + int iommufd_fault_domain_replace_dev(struct iommufd_device *idev, struct iommufd_hw_pagetable *hwpt, struct iommufd_hw_pagetable *old) @@ -190,6 +209,9 @@ int iommufd_fault_domain_replace_dev(struct iommufd_dev= ice *idev, ret =3D iommufd_fault_iopf_enable(idev); if (ret) return ret; + + if (iommufd_init_pasid_array(hwpt->domain, idev)) + return -EINVAL; } =20 ret =3D __fault_domain_replace_dev(idev, hwpt, old); --=20 2.43.0 From nobody Fri Dec 19 15:19:53 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F97C1DAC46; Wed, 4 Sep 2024 13:18:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725455893; cv=none; b=BPigS4Ypk8FyxDoODvUg2cQC24avUOHi2fBIxm5c4mhe8wkoC2Yb1jvrp3KTYx3jBP2jYf8/vC+Q7x9fXzJEUla3r+mXAJlhphurYJPDvD/tLC4Wio+ReYsm5+9Kk+rOaPDdjMIrD+Mr+KIktz6JpnXUeec60Id9lu7sRlFKxYQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725455893; c=relaxed/simple; bh=ZQzu5Awk7csrIQP8WA5EilsMPXyklmrTn+/ECQpc/IE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=p4Ztb2BEln1OQWAI6V/Zok4zt2NN0GS573xrFXx5WPhO8n1paz1WYTCKyMyBJnOHhUyikGTnlV/GE4yXdYI+eFD9N+WUF6q0DiXyDM+PesYgEfEPKvRtJpjX4j8zWVdVDevrc1nbPzcJvpnUiYu+URnqwC3Fb5pu1WBSWNwVkEI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WfcIuRxc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WfcIuRxc" Received: by smtp.kernel.org (Postfix) with ESMTPS id 11B7AC4CED2; Wed, 4 Sep 2024 13:18:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725455893; bh=ZQzu5Awk7csrIQP8WA5EilsMPXyklmrTn+/ECQpc/IE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=WfcIuRxcmVKJvYDlPNuC/F/wjV/Oci38S3Dg/CJfmLZLkQl3jDyxJLcpSW2Vp1sKs 9vn/0mwhQsGFfnOmesIGNGtpLp6G7FDkwV+wwX30l4rznmLqsAt3KqRUmo0/eeQmuh +61gkHOrlKfu8YrAS/HWXmD7bWKXd84js7tHRkIii2KpKpCd52YO2+8mzn+nPTpLA4 xdJqWr/16lSrOz3azXYSY+aay5xmfdN+S6ZS7u/xh9ps4OVcutpyc7oU6IwE3JORyk PIs0pmRCxULEG5yt7P9z7Vj/xJ/+nReZZyKgvQIa7b4ax49pd0NjFhoVV7HZ/TQkOP f1sk+XDKbdZPA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08017CD37B4; Wed, 4 Sep 2024 13:18:13 +0000 (UTC) From: Joel Granados via B4 Relay Date: Wed, 04 Sep 2024 15:17:17 +0200 Subject: [PATCH 6/6] iommu/vt-d: drop pasid requirement for prq initialization Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240904-jag-iopfv8-v1-6-e3549920adf3@samsung.com> References: <20240904-jag-iopfv8-v1-0-e3549920adf3@samsung.com> In-Reply-To: <20240904-jag-iopfv8-v1-0-e3549920adf3@samsung.com> To: David Woodhouse , Lu Baolu , Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian , Klaus Jensen Cc: linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Joel Granados , Klaus Jensen X-Mailer: b4 0.15-dev-00a43 X-Developer-Signature: v=1; a=openpgp-sha256; l=1454; i=j.granados@samsung.com; h=from:subject:message-id; bh=GQ979ruQ4vAANRiiIGnsASOC26gBsL07Le0pjm1OYPs=; b=owJ4nAHtARL+kA0DAAoBupfNUreWQU8ByyZiAGbYXhKOqYL08HTDL5U1FS6YKVJeseJUwf3VA Vyg9JiqiavFWYkBswQAAQoAHRYhBK5HCVcl5jElzssnkLqXzVK3lkFPBQJm2F4SAAoJELqXzVK3 lkFPhwEMAJc0ezgHDa2U5drkdjhqFE9iQKVk3KUkm+9m70jbOA8N+95R9S36RYtpryTYFwjSTxS K3HNBVSj5Dfm1iz/uLNGPW71ImEuyoD+f9JveefAD8sN93nSlSykCrlFxmzKhVoM7rl9ZNJQ6Bq 6uIRRXA36olvwExRfh4pzkSA0IkNgj7ZRo690ffXGX7kY6BZkNHwTzWvrhswLPNUuL0UHCTi5LL D3O57Rq1BNiXC+/qUiYHKqmOdvHY9j7P1iYeXF1ZRqJG4G26BssP3kXmKkqP5bN0Isvk28PF16n F3QwHAW2KXPG+qOdm4JTI6/HZF+xBNjoJfq/sTkIKrJ5eo1NLMKacQA4SGqIR6YtEra0SlWb+w9 IvzME5R8OQuzOvnYhsfW6Fzwm2COK9juCNiITfiDH11K2h60XZ+48dYiTrs0Lq2BQ9hxRyPzpUe vlwFzoPVwkBXhUnA9kmWOa8FcbpKyKJ/ZsOVlLhBz38EpWnBlm4779t0Ic0hvwiyUeckIp4wj94 W8= X-Developer-Key: i=j.granados@samsung.com; a=openpgp; fpr=F1F8E46D30F0F6C4A45FF4465895FAAC338C6E77 X-Endpoint-Received: by B4 Relay for j.granados@samsung.com/default with auth_id=70 X-Original-From: Joel Granados Reply-To: j.granados@samsung.com From: Klaus Jensen PASID support within the IOMMU is not required to enable the Page Request Queue, only the PRS capability. Signed-off-by: Klaus Jensen Signed-off-by: Joel Granados --- drivers/iommu/intel/iommu.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 3d1c971eb9e5..9f3bbdbd6372 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1487,10 +1487,8 @@ static void free_dmar_iommu(struct intel_iommu *iomm= u) /* free context mapping */ free_context_table(iommu); =20 - if (pasid_supported(iommu)) { - if (ecap_prs(iommu->ecap)) - intel_finish_prq(iommu); - } + if (ecap_prs(iommu->ecap)) + intel_finish_prq(iommu); } =20 /* @@ -2480,7 +2478,7 @@ static int __init init_dmars(void) =20 iommu_flush_write_buffer(iommu); =20 - if (pasid_supported(iommu) && ecap_prs(iommu->ecap)) { + if (ecap_prs(iommu->ecap)) { /* * Call dmar_alloc_hwirq() with dmar_global_lock held, * could cause possible lock race condition. @@ -2921,7 +2919,7 @@ static int intel_iommu_add(struct dmar_drhd_unit *dma= ru) intel_iommu_init_qi(iommu); iommu_flush_write_buffer(iommu); =20 - if (pasid_supported(iommu) && ecap_prs(iommu->ecap)) { + if (ecap_prs(iommu->ecap)) { ret =3D intel_enable_prq(iommu); if (ret) goto disable_iommu; --=20 2.43.0