From nobody Thu Sep 19 16:33:12 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 25B361A0BF2; Tue, 3 Sep 2024 10:48:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725360526; cv=none; b=GAH3pZ6tB+J9yg7flPfxv11JgR3EfXhlLZRBHDrYKwDEjBnRm14QDunlKQHd/G46JcH+cMWVUjV47v/rR0CDGJeHhYtDX7sxU+mZvkm94Y6I++kSuVpDYmM5f9yAw58c4mQA0cX62PrSX4OHN5lsEPWSFtsWQt4mKqB4zAwFo5U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725360526; c=relaxed/simple; bh=049uuilb9z/YbFT1C82V6wGOnQJt5Pm3yY/25FZjxCQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aJF7X3BP7DQdKL/x2icyXZbGM3sUVMZ1HUIMk5kFmTdmCublQrogegDj61D85WAOo7P+dTVpCam5rfdh2/wIda7MuxFJ2YyJCPeSXIz+3hgteHECF+pbMutxMem9HlVkXRbhhC0kS0I0s2sUa6hgc3a5ivjgzJhzPEzJnlhPvUE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=gKIofAUc; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="gKIofAUc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1725360525; x=1756896525; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=049uuilb9z/YbFT1C82V6wGOnQJt5Pm3yY/25FZjxCQ=; b=gKIofAUcPqEzFx1b+hiIhlWAAg7foAgufQSf2QsBGBlM9S6AeXI/PXWJ kepYnAWkAFGvcprEZ0HF0sYQ3fHV5e4o7m+2sHcRpa6F82cuef2iYlUdr dxz4hM4xm4JAEQIT4t0RZdr2cRa8XDiKvXbrl1wjdv53Y+hOzXiL3R+oa bfYSas8eDDXJ9ZSYaT2SUJ8SGov0jTUg4Axr7+Nezd3qhDhLUaP8E+ZPu WOPKg2qODsKHsChhAdUawP6gxbO9NS70NkCYLCDSlRNkbVcY5LMDioG61 Rdn6qu1nTfXkfXik0qAH/NQcV+mUMVagMGPc2UPVrW5U/mVkaC/2Yeifq w==; X-CSE-ConnectionGUID: rIKhwXIVR0G9nc7kmcxc3g== X-CSE-MsgGUID: yaBXfKDdTsykn29SJXHkow== X-IronPort-AV: E=Sophos;i="6.10,198,1719903600"; d="scan'208";a="31885957" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Sep 2024 03:48:43 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 3 Sep 2024 03:48:17 -0700 Received: from che-ll-i17164.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 3 Sep 2024 03:48:07 -0700 From: Parthiban Veerasooran To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , , , , , , Parthiban Veerasooran Subject: [PATCH net-next v7 05/14] net: ethernet: oa_tc6: implement error interrupts unmasking Date: Tue, 3 Sep 2024 16:16:56 +0530 Message-ID: <20240903104705.378684-6-Parthiban.Veerasooran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240903104705.378684-1-Parthiban.Veerasooran@microchip.com> References: <20240903104705.378684-1-Parthiban.Veerasooran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This will unmask the following error interrupts from the MAC-PHY. tx protocol error rx buffer overflow error loss of framing error header error The MAC-PHY will signal an error by setting the EXST bit in the receive data footer which will then allow the host to read the STATUS0 register to find the source of the error. Reviewed-by: Andrew Lunn Signed-off-by: Parthiban Veerasooran --- drivers/net/ethernet/oa_tc6.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/net/ethernet/oa_tc6.c b/drivers/net/ethernet/oa_tc6.c index f774ed397213..86b032cdbee1 100644 --- a/drivers/net/ethernet/oa_tc6.c +++ b/drivers/net/ethernet/oa_tc6.c @@ -18,6 +18,13 @@ #define OA_TC6_REG_STATUS0 0x0008 #define STATUS0_RESETC BIT(6) /* Reset Complete */ =20 +/* Interrupt Mask Register #0 */ +#define OA_TC6_REG_INT_MASK0 0x000C +#define INT_MASK0_HEADER_ERR_MASK BIT(5) +#define INT_MASK0_LOSS_OF_FRAME_ERR_MASK BIT(4) +#define INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK BIT(3) +#define INT_MASK0_TX_PROTOCOL_ERR_MASK BIT(0) + /* Control command header */ #define OA_TC6_CTRL_HEADER_DATA_NOT_CTRL BIT(31) #define OA_TC6_CTRL_HEADER_WRITE_NOT_READ BIT(29) @@ -327,6 +334,23 @@ static int oa_tc6_sw_reset_macphy(struct oa_tc6 *tc6) return oa_tc6_write_register(tc6, OA_TC6_REG_STATUS0, regval); } =20 +static int oa_tc6_unmask_macphy_error_interrupts(struct oa_tc6 *tc6) +{ + u32 regval; + int ret; + + ret =3D oa_tc6_read_register(tc6, OA_TC6_REG_INT_MASK0, ®val); + if (ret) + return ret; + + regval &=3D ~(INT_MASK0_TX_PROTOCOL_ERR_MASK | + INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK | + INT_MASK0_LOSS_OF_FRAME_ERR_MASK | + INT_MASK0_HEADER_ERR_MASK); + + return oa_tc6_write_register(tc6, OA_TC6_REG_INT_MASK0, regval); +} + /** * oa_tc6_init - allocates and initializes oa_tc6 structure. * @spi: device with which data will be exchanged. @@ -369,6 +393,13 @@ struct oa_tc6 *oa_tc6_init(struct spi_device *spi) return NULL; } =20 + ret =3D oa_tc6_unmask_macphy_error_interrupts(tc6); + if (ret) { + dev_err(&tc6->spi->dev, + "MAC-PHY error interrupts unmask failed: %d\n", ret); + return NULL; + } + return tc6; } EXPORT_SYMBOL_GPL(oa_tc6_init); --=20 2.34.1