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[211.75.127.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-715e56d7804sm7405114b3a.154.2024.09.02.18.38.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Sep 2024 18:38:41 -0700 (PDT) Received: from hqs-appsw-a2o.mp600.macronix.com (linux-patcher [172.17.236.67]) by twhmp6px (Postfix) with ESMTPS id DE1E080526; Tue, 3 Sep 2024 09:47:09 +0800 (CST) From: Cheng Ming Lin To: miquel.raynal@bootlin.com, vigneshr@ti.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: richard@nod.at, alvinzhou@mxic.com.tw, leoyu@mxic.com.tw, Cheng Ming Lin Subject: [PATCH v6 1/2] mtd: spinand: Add support for setting plane select bits Date: Tue, 3 Sep 2024 09:36:24 +0800 Message-Id: <20240903013625.1658825-2-linchengming884@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240903013625.1658825-1-linchengming884@gmail.com> References: <20240903013625.1658825-1-linchengming884@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cheng Ming Lin Add two flags for inserting the Plane Select bit into the column address during the write_to_cache and the read_from_cache operation. Add the SPINAND_HAS_PROG_PLANE_SELECT_BIT flag for serial NAND flash that require inserting the Plane Select bit into the column address during the write_to_cache operation. Add the SPINAND_HAS_READ_PLANE_SELECT_BIT flag for serial NAND flash that require inserting the Plane Select bit into the column address during the read_from_cache operation. Signed-off-by: Cheng Ming Lin --- drivers/mtd/nand/spi/core.c | 6 ++++++ include/linux/mtd/spinand.h | 2 ++ 2 files changed, 8 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index e0b6715e5dfe..e7b592cdbb4c 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -386,6 +386,9 @@ static int spinand_read_from_cache_op(struct spinand_de= vice *spinand, else rdesc =3D spinand->dirmaps[req->pos.plane].rdesc_ecc; =20 + if (spinand->flags & SPINAND_HAS_READ_PLANE_SELECT_BIT) + column |=3D req->pos.plane << fls(nanddev_page_size(nand)); + while (nbytes) { ret =3D spi_mem_dirmap_read(rdesc, column, nbytes, buf); if (ret < 0) @@ -460,6 +463,9 @@ static int spinand_write_to_cache_op(struct spinand_dev= ice *spinand, else wdesc =3D spinand->dirmaps[req->pos.plane].wdesc_ecc; =20 + if (spinand->flags & SPINAND_HAS_PROG_PLANE_SELECT_BIT) + column |=3D req->pos.plane << fls(nanddev_page_size(nand)); + while (nbytes) { ret =3D spi_mem_dirmap_write(wdesc, column, nbytes, buf); if (ret < 0) diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 5c19ead60499..0e0df620da53 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -312,6 +312,8 @@ struct spinand_ecc_info { =20 #define SPINAND_HAS_QE_BIT BIT(0) #define SPINAND_HAS_CR_FEAT_BIT BIT(1) +#define SPINAND_HAS_PROG_PLANE_SELECT_BIT BIT(2) +#define SPINAND_HAS_READ_PLANE_SELECT_BIT BIT(3) =20 /** * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine stru= cture --=20 2.25.1