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[75.72.166.104]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-39f3b059c32sm28466715ab.75.2024.09.02.18.31.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Sep 2024 18:31:34 -0700 (PDT) From: Adam Ford To: linux-phy@lists.infradead.org Cc: dominique.martinet@atmark-techno.com, linux-imx@nxp.com, festevam@gmail.com, frieder.schrempf@kontron.de, aford@beaconembedded.com, Sandor.yu@nxp.com, Adam Ford , Vinod Koul , Kishon Vijay Abraham I , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Lucas Stach , Marco Felsch , linux-kernel@vger.kernel.org Subject: [PATCH V4 2/5] phy: freescale: fsl-samsung-hdmi: Simplify REG21_PMS_S_MASK lookup Date: Mon, 2 Sep 2024 20:30:44 -0500 Message-ID: <20240903013113.139698-3-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240903013113.139698-1-aford173@gmail.com> References: <20240903013113.139698-1-aford173@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The value of 'S' is writen to two places, PHY_REG3[7:4] and PHY_REG21[3:0]. There is a lookup table which contains the value of PHY_REG3. Rather than using a switch statement based on the pixel clock to search for the value of 'S' again, just shift the contents of PHY_REG3[7:4] >> 4 and place the value in PHY_REG21[3:0]. Doing this can eliminate an entire function. Signed-off-by: Adam Ford Reviewed-by: Marco Felsch --- drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 39 ++------------------ 1 file changed, 4 insertions(+), 35 deletions(-) diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/fre= escale/phy-fsl-samsung-hdmi.c index bc5d3625ece6..a700a300dc6f 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -355,40 +355,6 @@ to_fsl_samsung_hdmi_phy(struct clk_hw *hw) return container_of(hw, struct fsl_samsung_hdmi_phy, hw); } =20 -static void -fsl_samsung_hdmi_phy_configure_pixclk(struct fsl_samsung_hdmi_phy *phy, - const struct phy_config *cfg) -{ - u8 div =3D 0x1; - - switch (cfg->pixclk) { - case 22250000 ... 33750000: - div =3D 0xf; - break; - case 35000000 ... 40000000: - div =3D 0xb; - break; - case 43200000 ... 47500000: - div =3D 0x9; - break; - case 50349650 ... 63500000: - div =3D 0x7; - break; - case 67500000 ... 90000000: - div =3D 0x5; - break; - case 94000000 ... 148500000: - div =3D 0x3; - break; - case 154000000 ... 297000000: - div =3D 0x1; - break; - } - - writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, div), - phy->regs + PHY_REG(21)); -} - static void fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *p= hy, const struct phy_config *cfg) @@ -457,7 +423,10 @@ static int fsl_samsung_hdmi_phy_configure(struct fsl_s= amsung_hdmi_phy *phy, for (i =3D 0; i < PHY_PLL_DIV_REGS_NUM; i++) writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG(2) + i * 4); =20 - fsl_samsung_hdmi_phy_configure_pixclk(phy, cfg); + /* High nibble of pll_div_regs[1] contains S which also gets written to R= EG21 */ + writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, + cfg->pll_div_regs[1] >> 4), phy->regs + PHY_REG(21)); + fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg); =20 writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG(33)); --=20 2.43.0