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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240903-fix_fencei_optimization-v2-1-8025f20171fc@rivosinc.com> X-B4-Tracking: v=1; b=H4sIADGT12YC/x2MQQqAMAzAviI9O6hVQfyKiIzZaQ9O2URE2d8tH gNJXkgchRP0xQuRL0myBwUqC3CrDQsbmZWBkBrsKjJe7slzcCzTfpyyyWNPbUztu8o6QmyxBa2 PyKr+52HM+QPabkXyaQAAAA== To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Atish Patra , Samuel Holland , Andrea Parri Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2866; i=charlie@rivosinc.com; h=from:subject:message-id; bh=CB8edBfcGqRK+ymTERIGqlxIoQY7nhBdPrqLUxfx3VM=; b=owGbwMvMwCHWx5hUnlvL8Y3xtFoSQ9r1yabsibc2PpC8Fz5lTtuBLqdHkUsXmhe4vWxTtzHuP 29Zx2bdUcrCIMbBICumyMJzrYG59Y5+2VHRsgkwc1iZQIYwcHEKwEQWqzP8M2FReK927GdObf7r u1d334+5mrFDaUvYztKb1VysFgs9NjEyvPF5wKlToPzt8vy12h8ZDXZUfJ5zeYUS9/7LL77yev0 24gcA X-Developer-Key: i=charlie@rivosinc.com; a=openpgp; fpr=7D834FF11B1D8387E61C776FFB10D1F27D6B1354 The icache will be flushed in switch_to() if force_icache_flush is true, or in flush_icache_deferred() if icache_stale_mask is set. Between setting force_icache_flush to false and calculating the new icache_stale_mask, preemption needs to be disabled. There are two reasons for this: 1. If CPU migration happens between force_icache_flush =3D false, and the icache_stale_mask is set, an icache flush will not be emitted. 2. smp_processor_id() is used in set_icache_stale_mask() to mark the current CPU as not needing another flush since a flush will have happened either by userspace or by the kernel when performing the migration. smp_processor_id() is currently called twice with preemption enabled which causes a race condition. It allows icache_stale_mask to be populated with inconsistent CPU ids. Resolve these two issues by setting the icache_stale_mask before setting force_icache_flush to false, and using get_cpu()/put_cpu() to obtain the smp_processor_id(). Signed-off-by: Charlie Jenkins Fixes: 6b9391b581fd ("riscv: Include riscv_set_icache_flush_ctx prctl") --- Changes in v2: - This patch has been split into a different series from the other patch in the v1. This patch is unchanged. --- arch/riscv/mm/cacheflush.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index a03c994eed3b..b81672729887 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -158,6 +158,7 @@ void __init riscv_init_cbo_blocksizes(void) #ifdef CONFIG_SMP static void set_icache_stale_mask(void) { + int cpu =3D get_cpu(); cpumask_t *mask; bool stale_cpu; =20 @@ -168,10 +169,11 @@ static void set_icache_stale_mask(void) * concurrently on different harts. */ mask =3D ¤t->mm->context.icache_stale_mask; - stale_cpu =3D cpumask_test_cpu(smp_processor_id(), mask); + stale_cpu =3D cpumask_test_cpu(cpu, mask); =20 cpumask_setall(mask); - cpumask_assign_cpu(smp_processor_id(), mask, stale_cpu); + cpumask_assign_cpu(cpu, mask, stale_cpu); + put_cpu(); } #endif =20 @@ -239,14 +241,12 @@ int riscv_set_icache_flush_ctx(unsigned long ctx, uns= igned long scope) case PR_RISCV_CTX_SW_FENCEI_OFF: switch (scope) { case PR_RISCV_SCOPE_PER_PROCESS: - current->mm->context.force_icache_flush =3D false; - set_icache_stale_mask(); + current->mm->context.force_icache_flush =3D false; break; case PR_RISCV_SCOPE_PER_THREAD: - current->thread.force_icache_flush =3D false; - set_icache_stale_mask(); + current->thread.force_icache_flush =3D false; break; default: return -EINVAL; --- base-commit: 7c626ce4bae1ac14f60076d00eafe71af30450ba change-id: 20240812-fix_fencei_optimization-3f81ac200505 --=20 - Charlie