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Mon, 2 Sep 2024 13:46:00 +0000 From: Tarang Raval To: shawnguo@kernel.org, krzk+dt@kernel.org, robh@kernel.org, festevam@gmail.com Cc: Tarang Raval , Conor Dooley , Sascha Hauer , Pengutronix Kernel Team , Hugo Villeneuve , Hiago De Franco , Joao Paulo Goncalves , Gregor Herburger , Mathieu Othacehe , Alexander Stein , Josua Mayer , Parthiban Nallathambi , Yannic Moog , Li Yang , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 1/2] arm64: dts: imx8mp-var-som-symphony: Add Variscite Symphony board and VAR-SOM-MX8MP SoM Date: Mon, 2 Sep 2024 19:15:07 +0530 Message-Id: <20240902134512.16717-2-tarang.raval@siliconsignals.io> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240902134512.16717-1-tarang.raval@siliconsignals.io> References: <20240902134512.16717-1-tarang.raval@siliconsignals.io> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: PN2PR01CA0249.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:21a::9) To PN3P287MB1829.INDP287.PROD.OUTLOOK.COM (2603:1096:c01:199::7) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PN3P287MB1829:EE_|PN2P287MB0597:EE_ X-MS-Office365-Filtering-Correlation-Id: 5f24d421-65b9-41ae-ad6a-08dccb559441 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|376014|7416014|52116014|38350700014; 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charset="utf-8" Adds the DTSI file for the Variscite VAR-SOM-MX8MP System on Module which is delivered with the Variscite Symphony Evaluation Kit. Initial support includes: - Serial console - eMMC - SD card Signed-off-by: Tarang Raval Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mp-var-som-symphony.dts | 11 + .../boot/dts/freescale/imx8mp-var-som.dtsi | 359 ++++++++++++++++++ 3 files changed, 371 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.d= ts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index bd443c2bc5a4..03db6aef757d 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -177,6 +177,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-skov-revb-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-skov-revb-lt6.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-skov-revb-mi1010ait-1cp1.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-tqma8mpql-mba8mpxl.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-venice-gw71xx-2x.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-venice-gw72xx-2x.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-venice-gw73xx-2x.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/ar= ch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts new file mode 100644 index 000000000000..36d3eb865202 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 Variscite Ltd. + */ + +#include "imx8mp-var-som.dtsi" + +/ { + model =3D "Variscite VAR-SOM-MX8M-PLUS on Symphony-Board"; + compatible =3D "variscite,var-som-mx8mp-symphony", "variscite,var-som-mx8= mp", "fsl,imx8mp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi b/arch/arm64= /boot/dts/freescale/imx8mp-var-som.dtsi new file mode 100644 index 000000000000..f1bd2d9d585b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi @@ -0,0 +1,359 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 Variscite Ltd. + * + * Author: Tarang Raval + */ + +/dts-v1/; + +#include +#include +#include +#include "imx8mp.dtsi" + +/ { + model =3D "Variscite VAR-SOM-MX8M Plus module"; + + chosen { + stdout-path =3D &uart2; + }; +=09 + gpio-leds { + compatible =3D "gpio-leds"; +=09 + led-0 { + function =3D LED_FUNCTION_POWER; + gpios =3D <&pca9534 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + }; +=09 + memory@40000000 { + device_type =3D "memory"; + reg =3D <0x0 0x40000000 0 0xc0000000>, + <0x1 0x00000000 0 0xc0000000>; + }; + + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible =3D "regulator-fixed"; + regulator-name =3D "VSD_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpios =3D <&gpio4 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us =3D <100>; + off-on-delay-us =3D <12000>; + }; +}; + +&A53_0 { + cpu-supply =3D <&buck2>; +}; + +&A53_1 { + cpu-supply =3D <&buck2>; +}; + +&A53_2 { + cpu-supply =3D <&buck2>; +}; + +&A53_3 { + cpu-supply =3D <&buck2>; +}; + +&i2c1 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c1>; + status =3D "okay"; + + pmic@25 { + compatible =3D "nxp,pca9450c"; + reg =3D <0x25>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pmic>; + interrupt-parent =3D <&gpio5>; + interrupts =3D <4 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name =3D "BUCK1"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + }; + + buck2: BUCK2 { + regulator-name =3D "BUCK2"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + nxp,dvs-run-voltage =3D <950000>; + nxp,dvs-standby-voltage =3D <850000>; + }; + + buck4: BUCK4 { + regulator-name =3D "BUCK4"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name =3D "BUCK5"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name =3D "BUCK6"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name =3D "LDO1"; + regulator-min-microvolt =3D <1600000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name =3D "LDO2"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name =3D "LDO3"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name =3D "LDO4"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name =3D "LDO5"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + }; + }; +}; + +&i2c3 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c3>; + status =3D "okay"; + + /* GPIO expander */ + pca9534: gpio@20 { + compatible =3D "nxp,pca9534"; + reg =3D <0x20>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pca9534>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <15 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; +=09 + usb3-sata-sel-hog { + gpio-hog; + gpios =3D <4 0>; + output-low; + line-name =3D "usb3_sata_sel"; + }; + }; +}; + +/* Console */ +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart2>; + status =3D "okay"; +}; + +/* SD-card */ +&usdhc2 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios =3D <&gpio1 14 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <®_usdhc2_vmmc>; + bus-width =3D <4>; + status =3D "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc3>; + pinctrl-1 =3D <&pinctrl_usdhc3_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc3_200mhz>; + bus-width =3D <8>; + non-removable; + status =3D "okay"; +}; + +&wdog1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wdog>; + fsl,ext-reset-output; + status =3D "okay"; +}; + +&iomuxc { + + pinctrl_i2c1: i2c1grp { + fsl,pins =3D < + MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL = 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA = 0x400001c2 + >; + }; + + pinctrl_pca9534: pca9534grp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 = 0xc0 + >; + }; +=09 + pinctrl_pmic: pmicgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1c0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins =3D < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX = 0x40 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX = 0x40 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 = 0x1c4 + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 = 0x10 + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 = 0xc0 + >; + }; +=09 + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK = 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD = 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 = 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 = 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 = 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 = 0x1d0 + >; + }; +=09 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK = 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD = 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 = 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 = 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 = 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 = 0x1d4 + >; + }; +=09 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK = 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD = 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 = 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 = 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 = 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 = 0x1d6 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +}; --=20 2.34.1