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[75.164.215.68]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-715e569ef39sm7532701b3a.122.2024.09.02.21.08.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Sep 2024 21:08:52 -0700 (PDT) From: Drew Fustini Date: Mon, 02 Sep 2024 21:06:54 -0700 Subject: [PATCH 1/8] dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240902-th1520-pinctrl-v1-1-639bf83ef50a@tenstorrent.com> References: <20240902-th1520-pinctrl-v1-0-639bf83ef50a@tenstorrent.com> In-Reply-To: <20240902-th1520-pinctrl-v1-0-639bf83ef50a@tenstorrent.com> To: Drew Fustini , Guo Ren , Fu Wei , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Thomas Bonnefille , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini X-Mailer: b4 0.14.1 From: Emil Renner Berthing Add bindings for the pin controllers on the T-Head TH1520 RISC-V SoC. Tested-by: Thomas Bonnefille Signed-off-by: Emil Renner Berthing [dfustini: use a single compatible for all pin controller instances] Signed-off-by: Drew Fustini --- .../bindings/pinctrl/thead,th1520-pinctrl.yaml | 165 +++++++++++++++++= ++++ MAINTAINERS | 1 + 2 files changed, 166 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl= .yaml b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml new file mode 100644 index 000000000000..429cc0bc1100 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml @@ -0,0 +1,165 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/thead,th1520-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-Head TH1520 SoC pin controller + +maintainers: + - Emil Renner Berthing + +description: | + Pinmux and pinconf controller in the T-Head TH1520 RISC-V SoC. + + The TH1520 has 3 groups of pads each controlled from different memory ra= nges. + Confusingly the memory ranges are named + PADCTRL_AOSYS -> PAD Group 1 + PADCTRL1_APSYS -> PAD Group 2 + PADCTRL0_APSYS -> PAD Group 3 + + Each pad can be muxed individually to up to 6 different functions. For m= ost + pads only a few of those 6 configurations are valid though, and a few pa= ds in + group 1 does not support muxing at all. + + Pinconf is fairly regular except for a few pads in group 1 that either c= an't + be configured or has some special functions. The rest have configurable = drive + strength, input enable, schmitt trigger, slew rate, pull-up and pull-dow= n in + addition to a special strong pull up. + + Certain pads in group 1 can be muxed to AUDIO_PA0 - AUDIO_PA30 functions= and + are then meant to be used by the audio co-processor. Each such pad can t= hen + be further muxed to either audio GPIO or one of 4 functions such as UART= , I2C + and I2S. If the audio pad is muxed to one of the 4 functions then pincon= f is + also configured in different registers. All of this is done from a diffe= rent + AUDIO_IOCTRL memory range and is left to the audio co-processor for now. + +properties: + compatible: + enum: + - thead,th1520-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +patternProperties: + '-[0-9]+$': + type: object + + additionalProperties: false + + patternProperties: + '-pins$': + type: object + $ref: /schemas/pinctrl/pincfg-node.yaml + + additionalProperties: false + + description: + A pinctrl node should contain at least one subnode describing one + or more pads and their associated pinmux and pinconf settings. + + properties: + pins: + $ref: /schemas/pinctrl/pinmux-node.yaml#/properties/pins + description: List of pads that properties in the node apply to. + + function: + $ref: /schemas/pinctrl/pinmux-node.yaml#/properties/function + enum: [ gpio, pwm, uart, ir, i2c, spi, qspi, sdio, audio, i2s, + gmac0, gmac1, dpu0, dpu1, isp, hdmi, bootsel, debug, + clock, jtag, iso7816, efuse, reset ] + description: The mux function to select for the given pins. + + bias-disable: true + + bias-pull-up: + oneOf: + - type: boolean + description: Enable the regular 48kOhm pull-up + - enum: [ 2100, 48000 ] + description: Enable the strong 2.1kOhm pull-up or regular = 48kOhm pull-up + + bias-pull-down: + oneOf: + - type: boolean + - const: 44000 + description: Enable the regular 44kOhm pull-down + + drive-strength: + enum: [ 1, 2, 3, 5, 7, 8, 10, 12, 13, 15, 16, 18, 20, 21, 23, = 25 ] + description: Drive strength in mA + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + maximum: 1 + + required: + - pins + +required: + - compatible + - reg + - clocks + +additionalProperties: false + + +examples: + - | + padctrl0_apsys: pinctrl@ec007000 { + compatible =3D "thead,th1520-pinctrl"; + reg =3D <0xec007000 0x1000>; + clocks =3D <&apb_clk>; + + uart0_pins: uart0-0 { + tx-pins { + pins =3D "UART0_TXD"; + function =3D "uart"; + bias-disable; + drive-strength =3D <3>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + rx-pins { + pins =3D "UART0_RXD"; + function =3D "uart"; + bias-disable; + drive-strength =3D <1>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + }; + }; + + padctrl1_apsys: pinctrl@e7f3c000 { + compatible =3D "thead,th1520-pinctrl"; + reg =3D <0xe7f3c000 0x1000>; + clocks =3D <&apb_clk>; + + i2c5_pins: i2c5-0 { + i2c-pins { + pins =3D "QSPI1_CSN0", /* I2C5_SCL */ + "QSPI1_D0_MOSI"; /* I2C5_SDA */ + function =3D "i2c"; + bias-pull-up =3D <2100>; + drive-strength =3D <7>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 878dcd23b331..a73953c0f080 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19700,6 +19700,7 @@ L: linux-riscv@lists.infradead.org S: Maintained T: git https://github.com/pdp7/linux.git F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml +F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml F: arch/riscv/boot/dts/thead/ F: drivers/clk/thead/clk-th1520-ap.c F: include/dt-bindings/clock/thead,th1520-clk-ap.h --=20 2.34.1 From nobody Mon Feb 9 04:04:41 2026 Received: from mail-pf1-f169.google.com (mail-pf1-f169.google.com [209.85.210.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0BDBD13D52F for ; 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[75.164.215.68]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-715e569ef39sm7532701b3a.122.2024.09.02.21.08.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Sep 2024 21:08:53 -0700 (PDT) From: Drew Fustini Date: Mon, 02 Sep 2024 21:06:55 -0700 Subject: [PATCH 2/8] pinctrl: Add driver for the T-Head TH1520 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240902-th1520-pinctrl-v1-2-639bf83ef50a@tenstorrent.com> References: <20240902-th1520-pinctrl-v1-0-639bf83ef50a@tenstorrent.com> In-Reply-To: <20240902-th1520-pinctrl-v1-0-639bf83ef50a@tenstorrent.com> To: Drew Fustini , Guo Ren , Fu Wei , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Thomas Bonnefille , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini X-Mailer: b4 0.14.1 From: Emil Renner Berthing Add pinctrl driver for the T-Head TH1520 RISC-V SoC. Tested-by: Thomas Bonnefille Signed-off-by: Emil Renner Berthing [dfustini: check unit address to identify the pin controller instance] Signed-off-by: Drew Fustini --- MAINTAINERS | 1 + drivers/pinctrl/Kconfig | 13 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-th1520.c | 906 +++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 921 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a73953c0f080..d47c418dd43b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19703,6 +19703,7 @@ F: Documentation/devicetree/bindings/clock/thead,th= 1520-clk-ap.yaml F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml F: arch/riscv/boot/dts/thead/ F: drivers/clk/thead/clk-th1520-ap.c +F: drivers/pinctrl/pinctrl-th1520.c F: include/dt-bindings/clock/thead,th1520-clk-ap.h =20 RNBD BLOCK DRIVERS diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 7e4f93a3bc7a..8634bde3fe72 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -529,6 +529,19 @@ config PINCTRL_TPS6594 This driver can also be built as a module called tps6594-pinctrl. =20 +config PINCTRL_TH1520 + tristate "Pinctrl driver for the T-Head TH1520 SoC" + depends on ARCH_THEAD || COMPILE_TEST + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + select PINMUX + help + This is the driver for the pin controller blocks on the + T-Head TH1520 SoC. + + This driver is needed for RISC-V development boards like + the BeagleV Ahead and the LicheePi 4A. + config PINCTRL_ZYNQ bool "Pinctrl driver for Xilinx Zynq" depends on ARCH_ZYNQ diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index cc809669405a..b8c4cc6b19b4 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_PINCTRL_STMFX) +=3D pinctrl-stmfx.o obj-$(CONFIG_PINCTRL_SX150X) +=3D pinctrl-sx150x.o obj-$(CONFIG_PINCTRL_TB10X) +=3D pinctrl-tb10x.o obj-$(CONFIG_PINCTRL_TPS6594) +=3D pinctrl-tps6594.o +obj-$(CONFIG_PINCTRL_TH1520) +=3D pinctrl-th1520.o obj-$(CONFIG_PINCTRL_ZYNQMP) +=3D pinctrl-zynqmp.o obj-$(CONFIG_PINCTRL_ZYNQ) +=3D pinctrl-zynq.o =20 diff --git a/drivers/pinctrl/pinctrl-th1520.c b/drivers/pinctrl/pinctrl-th1= 520.c new file mode 100644 index 000000000000..678dc362a000 --- /dev/null +++ b/drivers/pinctrl/pinctrl-th1520.c @@ -0,0 +1,906 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Pinctrl driver for the T-Head TH1520 SoC + * + * Copyright (C) 2023 Emil Renner Berthing + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include "core.h" +#include "pinmux.h" +#include "pinconf.h" + +#define TH1520_PADCFG_IE BIT(9) +#define TH1520_PADCFG_SL BIT(8) +#define TH1520_PADCFG_ST BIT(7) +#define TH1520_PADCFG_SPU BIT(6) +#define TH1520_PADCFG_PS BIT(5) +#define TH1520_PADCFG_PE BIT(4) +#define TH1520_PADCFG_BIAS (TH1520_PADCFG_SPU | TH1520_PADCFG_PS | TH1520_= PADCFG_PE) +#define TH1520_PADCFG_DS GENMASK(3, 0) + +#define TH1520_PULL_DOWN_OHM 44000 /* typ. 44kOhm */ +#define TH1520_PULL_UP_OHM 48000 /* typ. 48kOhm */ +#define TH1520_PULL_STRONG_OHM 2100 /* typ. 2.1kOhm */ + +#define TH1520_PAD_NO_PADCFG BIT(30) +#define TH1520_PAD_MUXDATA GENMASK(29, 0) + +#define TH1520_PAD_GROUP1 "pinctrl@fffff4a000" +#define TH1520_PAD_GROUP2 "pinctrl@ffe7f3c000" +#define TH1520_PAD_GROUP3 "pinctrl@ffec007000" + +struct th1520_pad_group { + const char *name; + const struct pinctrl_pin_desc *pins; + unsigned int npins; +}; + +struct th1520_pinctrl { + struct pinctrl_desc desc; + struct mutex mutex; /* serialize adding functions */ + raw_spinlock_t lock; /* serialize register access */ + void __iomem *base; + struct pinctrl_dev *pctl; +}; + +static void __iomem *th1520_padcfg(struct th1520_pinctrl *thp, + unsigned int pin) +{ + return thp->base + 4 * (pin / 2); +} + +static unsigned int th1520_padcfg_shift(unsigned int pin) +{ + return 16 * (pin & BIT(0)); +} + +static void __iomem *th1520_muxcfg(struct th1520_pinctrl *thp, + unsigned int pin) +{ + return thp->base + 0x400 + 4 * (pin / 8); +} + +static unsigned int th1520_muxcfg_shift(unsigned int pin) +{ + return 4 * (pin & GENMASK(2, 0)); +} + +enum th1520_muxtype { + TH1520_MUX_____, + TH1520_MUX_GPIO, + TH1520_MUX_PWM, + TH1520_MUX_UART, + TH1520_MUX_IR, + TH1520_MUX_I2C, + TH1520_MUX_SPI, + TH1520_MUX_QSPI, + TH1520_MUX_SDIO, + TH1520_MUX_AUD, + TH1520_MUX_I2S, + TH1520_MUX_MAC0, + TH1520_MUX_MAC1, + TH1520_MUX_DPU0, + TH1520_MUX_DPU1, + TH1520_MUX_ISP, + TH1520_MUX_HDMI, + TH1520_MUX_BSEL, + TH1520_MUX_DBG, + TH1520_MUX_CLK, + TH1520_MUX_JTAG, + TH1520_MUX_ISO, + TH1520_MUX_FUSE, + TH1520_MUX_RST, +}; + +static const char *const th1520_muxtype_string[] =3D { + [TH1520_MUX_GPIO] =3D "gpio", + [TH1520_MUX_PWM] =3D "pwm", + [TH1520_MUX_UART] =3D "uart", + [TH1520_MUX_IR] =3D "ir", + [TH1520_MUX_I2C] =3D "i2c", + [TH1520_MUX_SPI] =3D "spi", + [TH1520_MUX_QSPI] =3D "qspi", + [TH1520_MUX_SDIO] =3D "sdio", + [TH1520_MUX_AUD] =3D "audio", + [TH1520_MUX_I2S] =3D "i2s", + [TH1520_MUX_MAC0] =3D "gmac0", + [TH1520_MUX_MAC1] =3D "gmac1", + [TH1520_MUX_DPU0] =3D "dpu0", + [TH1520_MUX_DPU1] =3D "dpu1", + [TH1520_MUX_ISP] =3D "isp", + [TH1520_MUX_HDMI] =3D "hdmi", + [TH1520_MUX_BSEL] =3D "bootsel", + [TH1520_MUX_DBG] =3D "debug", + [TH1520_MUX_CLK] =3D "clock", + [TH1520_MUX_JTAG] =3D "jtag", + [TH1520_MUX_ISO] =3D "iso7816", + [TH1520_MUX_FUSE] =3D "efuse", + [TH1520_MUX_RST] =3D "reset", +}; + +static enum th1520_muxtype th1520_muxtype_get(const char *str) +{ + enum th1520_muxtype mt; + + for (mt =3D TH1520_MUX_GPIO; mt < ARRAY_SIZE(th1520_muxtype_string); mt++= ) { + if (!strcmp(str, th1520_muxtype_string[mt])) + return mt; + } + return TH1520_MUX_____; +} + +#define TH1520_PAD(_nr, _name, m0, m1, m2, m3, m4, m5, _flags) \ + { .number =3D _nr, .name =3D #_name, .drv_data =3D (void *)((_flags) | \ + (TH1520_MUX_##m0 << 0) | (TH1520_MUX_##m1 << 5) | (TH1520_MUX_##m2 << = 10) | \ + (TH1520_MUX_##m3 << 15) | (TH1520_MUX_##m4 << 20) | (TH1520_MUX_##m5 << = 25)) } + +static const struct pinctrl_pin_desc th1520_group1_pins[] =3D { + TH1520_PAD(0, OSC_CLK_IN, ____, ____, ____, ____, ____, ____, TH1520_= PAD_NO_PADCFG), + TH1520_PAD(1, OSC_CLK_OUT, ____, ____, ____, ____, ____, ____, TH1520_= PAD_NO_PADCFG), + TH1520_PAD(2, SYS_RST_N, ____, ____, ____, ____, ____, ____, TH1520_= PAD_NO_PADCFG), + TH1520_PAD(3, RTC_CLK_IN, ____, ____, ____, ____, ____, ____, TH1520_= PAD_NO_PADCFG), + TH1520_PAD(4, RTC_CLK_OUT, ____, ____, ____, ____, ____, ____, TH1520_= PAD_NO_PADCFG), + /* skip number 5 so we can calculate register offsets and shifts from the= pin number */ + TH1520_PAD(6, TEST_MODE, ____, ____, ____, ____, ____, ____, TH1520_= PAD_NO_PADCFG), + TH1520_PAD(7, DEBUG_MODE, DBG, ____, ____, GPIO, ____, ____, TH1520_= PAD_NO_PADCFG), + TH1520_PAD(8, POR_SEL, ____, ____, ____, ____, ____, ____, TH1520_= PAD_NO_PADCFG), + TH1520_PAD(9, I2C_AON_SCL, I2C, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(10, I2C_AON_SDA, I2C, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(11, CPU_JTG_TCLK, JTAG, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(12, CPU_JTG_TMS, JTAG, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(13, CPU_JTG_TDI, JTAG, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(14, CPU_JTG_TDO, JTAG, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(15, CPU_JTG_TRST, JTAG, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(16, AOGPIO_7, CLK, AUD, ____, GPIO, ____, ____, 0), + TH1520_PAD(17, AOGPIO_8, UART, AUD, IR, GPIO, ____, ____, 0), + TH1520_PAD(18, AOGPIO_9, UART, AUD, IR, GPIO, ____, ____, 0), + TH1520_PAD(19, AOGPIO_10, CLK, AUD, ____, GPIO, ____, ____, 0), + TH1520_PAD(20, AOGPIO_11, GPIO, AUD, ____, ____, ____, ____, 0), + TH1520_PAD(21, AOGPIO_12, GPIO, AUD, ____, ____, ____, ____, 0), + TH1520_PAD(22, AOGPIO_13, GPIO, AUD, ____, ____, ____, ____, 0), + TH1520_PAD(23, AOGPIO_14, GPIO, AUD, ____, ____, ____, ____, 0), + TH1520_PAD(24, AOGPIO_15, GPIO, AUD, ____, ____, ____, ____, 0), + TH1520_PAD(25, AUDIO_PA0, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(26, AUDIO_PA1, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(27, AUDIO_PA2, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(28, AUDIO_PA3, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(29, AUDIO_PA4, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(30, AUDIO_PA5, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(31, AUDIO_PA6, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(32, AUDIO_PA7, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(33, AUDIO_PA8, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(34, AUDIO_PA9, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(35, AUDIO_PA10, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(36, AUDIO_PA11, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(37, AUDIO_PA12, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(38, AUDIO_PA13, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(39, AUDIO_PA14, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(40, AUDIO_PA15, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(41, AUDIO_PA16, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(42, AUDIO_PA17, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(43, AUDIO_PA27, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(44, AUDIO_PA28, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(45, AUDIO_PA29, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(46, AUDIO_PA30, AUD, RST, ____, GPIO, ____, ____, 0), +}; + +static const struct pinctrl_pin_desc th1520_group2_pins[] =3D { + TH1520_PAD(0, QSPI1_SCLK, QSPI, ISO, ____, GPIO, FUSE, ____, 0), + TH1520_PAD(1, QSPI1_CSN0, QSPI, ____, I2C, GPIO, FUSE, ____, 0), + TH1520_PAD(2, QSPI1_D0_MOSI, QSPI, ISO, I2C, GPIO, FUSE, ____, 0), + TH1520_PAD(3, QSPI1_D1_MISO, QSPI, ISO, ____, GPIO, FUSE, ____, 0), + TH1520_PAD(4, QSPI1_D2_WP, QSPI, ISO, UART, GPIO, FUSE, ____, 0), + TH1520_PAD(5, QSPI1_D3_HOLD, QSPI, ISO, UART, GPIO, ____, ____, 0), + TH1520_PAD(6, I2C0_SCL, I2C, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(7, I2C0_SDA, I2C, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(8, I2C1_SCL, I2C, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(9, I2C1_SDA, I2C, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(10, UART1_TXD, UART, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(11, UART1_RXD, UART, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(12, UART4_TXD, UART, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(13, UART4_RXD, UART, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(14, UART4_CTSN, UART, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(15, UART4_RTSN, UART, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(16, UART3_TXD, DBG, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(17, UART3_RXD, DBG, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(18, GPIO0_18, GPIO, I2C, ____, ____, ____, ____, 0), + TH1520_PAD(19, GPIO0_19, GPIO, I2C, ____, ____, ____, ____, 0), + TH1520_PAD(20, GPIO0_20, GPIO, UART, IR, ____, ____, ____, 0), + TH1520_PAD(21, GPIO0_21, GPIO, UART, IR, ____, DPU0, DPU1, 0), + TH1520_PAD(22, GPIO0_22, GPIO, JTAG, I2C, ____, DPU0, DPU1, 0), + TH1520_PAD(23, GPIO0_23, GPIO, JTAG, I2C, ____, DPU0, DPU1, 0), + TH1520_PAD(24, GPIO0_24, GPIO, JTAG, QSPI, ____, DPU0, DPU1, 0), + TH1520_PAD(25, GPIO0_25, GPIO, JTAG, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(26, GPIO0_26, GPIO, JTAG, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(27, GPIO0_27, GPIO, ____, I2C, ____, DPU0, DPU1, 0), + TH1520_PAD(28, GPIO0_28, GPIO, ____, I2C, ____, DPU0, DPU1, 0), + TH1520_PAD(29, GPIO0_29, GPIO, ____, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(30, GPIO0_30, GPIO, ____, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(31, GPIO0_31, GPIO, ____, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(32, GPIO1_0, GPIO, JTAG, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(33, GPIO1_1, GPIO, JTAG, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(34, GPIO1_2, GPIO, JTAG, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(35, GPIO1_3, GPIO, JTAG, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(36, GPIO1_4, GPIO, JTAG, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(37, GPIO1_5, GPIO, ____, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(38, GPIO1_6, GPIO, ____, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(39, GPIO1_7, GPIO, QSPI, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(40, GPIO1_8, GPIO, QSPI, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(41, GPIO1_9, GPIO, QSPI, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(42, GPIO1_10, GPIO, QSPI, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(43, GPIO1_11, GPIO, QSPI, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(44, GPIO1_12, GPIO, QSPI, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(45, GPIO1_13, GPIO, UART, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(46, GPIO1_14, GPIO, UART, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(47, GPIO1_15, GPIO, UART, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(48, GPIO1_16, GPIO, UART, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(49, CLK_OUT_0, BSEL, CLK, ____, GPIO, ____, ____, 0), + TH1520_PAD(50, CLK_OUT_1, BSEL, CLK, ____, GPIO, ____, ____, 0), + TH1520_PAD(51, CLK_OUT_2, BSEL, CLK, ____, GPIO, ____, ____, 0), + TH1520_PAD(52, CLK_OUT_3, BSEL, CLK, ____, GPIO, ____, ____, 0), + TH1520_PAD(53, GPIO1_21, GPIO, ____, ISP, ____, ____, ____, 0), + TH1520_PAD(54, GPIO1_22, GPIO, ____, ISP, ____, ____, ____, 0), + TH1520_PAD(55, GPIO1_23, GPIO, ____, ISP, ____, ____, ____, 0), + TH1520_PAD(56, GPIO1_24, GPIO, ____, ISP, ____, ____, ____, 0), + TH1520_PAD(57, GPIO1_25, GPIO, ____, ISP, ____, ____, ____, 0), + TH1520_PAD(58, GPIO1_26, GPIO, ____, ISP, ____, ____, ____, 0), + TH1520_PAD(59, GPIO1_27, GPIO, ____, ISP, ____, ____, ____, 0), + TH1520_PAD(60, GPIO1_28, GPIO, ____, ISP, ____, ____, ____, 0), + TH1520_PAD(61, GPIO1_29, GPIO, ____, ISP, ____, ____, ____, 0), + TH1520_PAD(62, GPIO1_30, GPIO, ____, ISP, ____, ____, ____, 0), +}; + +static const struct pinctrl_pin_desc th1520_group3_pins[] =3D { + TH1520_PAD(0, UART0_TXD, UART, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(1, UART0_RXD, UART, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(2, QSPI0_SCLK, QSPI, PWM, I2S, GPIO, ____, ____, 0), + TH1520_PAD(3, QSPI0_CSN0, QSPI, PWM, I2S, GPIO, ____, ____, 0), + TH1520_PAD(4, QSPI0_CSN1, QSPI, PWM, I2S, GPIO, ____, ____, 0), + TH1520_PAD(5, QSPI0_D0_MOSI, QSPI, PWM, I2S, GPIO, ____, ____, 0), + TH1520_PAD(6, QSPI0_D1_MISO, QSPI, PWM, I2S, GPIO, ____, ____, 0), + TH1520_PAD(7, QSPI0_D2_WP, QSPI, PWM, I2S, GPIO, ____, ____, 0), + TH1520_PAD(8, QSPI1_D3_HOLD, QSPI, ____, I2S, GPIO, ____, ____, 0), + TH1520_PAD(9, I2C2_SCL, I2C, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(10, I2C2_SDA, I2C, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(11, I2C3_SCL, I2C, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(12, I2C3_SDA, I2C, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(13, GPIO2_13, GPIO, SPI, ____, ____, ____, ____, 0), + TH1520_PAD(14, SPI_SCLK, SPI, UART, IR, GPIO, ____, ____, 0), + TH1520_PAD(15, SPI_CSN, SPI, UART, IR, GPIO, ____, ____, 0), + TH1520_PAD(16, SPI_MOSI, SPI, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(17, SPI_MISO, SPI, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(18, GPIO2_18, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(19, GPIO2_19, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(20, GPIO2_20, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(21, GPIO2_21, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(22, GPIO2_22, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(23, GPIO2_23, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(24, GPIO2_24, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(25, GPIO2_25, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(26, SDIO0_WPRTN, SDIO, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(27, SDIO0_DETN, SDIO, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(28, SDIO1_WPRTN, SDIO, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(29, SDIO1_DETN, SDIO, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(30, GPIO2_30, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(31, GPIO2_31, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(32, GPIO3_0, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(33, GPIO3_1, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(34, GPIO3_2, GPIO, PWM, ____, ____, ____, ____, 0), + TH1520_PAD(35, GPIO3_3, GPIO, PWM, ____, ____, ____, ____, 0), + TH1520_PAD(36, HDMI_SCL, HDMI, PWM, ____, GPIO, ____, ____, 0), + TH1520_PAD(37, HDMI_SDA, HDMI, PWM, ____, GPIO, ____, ____, 0), + TH1520_PAD(38, HDMI_CEC, HDMI, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(39, GMAC0_TX_CLK, MAC0, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(40, GMAC0_RX_CLK, MAC0, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(41, GMAC0_TXEN, MAC0, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(42, GMAC0_TXD0, MAC0, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(43, GMAC0_TXD1, MAC0, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(44, GMAC0_TXD2, MAC0, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(45, GMAC0_TXD3, MAC0, I2C, ____, GPIO, ____, ____, 0), + TH1520_PAD(46, GMAC0_RXDV, MAC0, I2C, ____, GPIO, ____, ____, 0), + TH1520_PAD(47, GMAC0_RXD0, MAC0, I2C, ____, GPIO, ____, ____, 0), + TH1520_PAD(48, GMAC0_RXD1, MAC0, I2C, ____, GPIO, ____, ____, 0), + TH1520_PAD(49, GMAC0_RXD2, MAC0, SPI, ____, GPIO, ____, ____, 0), + TH1520_PAD(50, GMAC0_RXD3, MAC0, SPI, ____, GPIO, ____, ____, 0), + TH1520_PAD(51, GMAC0_MDC, MAC0, SPI, MAC1, GPIO, ____, ____, 0), + TH1520_PAD(52, GMAC0_MDIO, MAC0, SPI, MAC1, GPIO, ____, ____, 0), + TH1520_PAD(53, GMAC0_COL, MAC0, PWM, ____, GPIO, ____, ____, 0), + TH1520_PAD(54, GMAC0_CRS, MAC0, PWM, ____, GPIO, ____, ____, 0), +}; + +static const struct th1520_pad_group th1520_group1 =3D { + .name =3D "th1520-group1", + .pins =3D th1520_group1_pins, + .npins =3D ARRAY_SIZE(th1520_group1_pins), +}; + +static const struct th1520_pad_group th1520_group2 =3D { + .name =3D "th1520-group2", + .pins =3D th1520_group2_pins, + .npins =3D ARRAY_SIZE(th1520_group2_pins), +}; + +static const struct th1520_pad_group th1520_group3 =3D { + .name =3D "th1520-group3", + .pins =3D th1520_group3_pins, + .npins =3D ARRAY_SIZE(th1520_group3_pins), +}; + +static int th1520_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct th1520_pinctrl *thp =3D pinctrl_dev_get_drvdata(pctldev); + + return thp->desc.npins; +} + +static const char *th1520_pinctrl_get_group_name(struct pinctrl_dev *pctld= ev, + unsigned int gsel) +{ + struct th1520_pinctrl *thp =3D pinctrl_dev_get_drvdata(pctldev); + + return thp->desc.pins[gsel].name; +} + +static int th1520_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int gsel, + const unsigned int **pins, + unsigned int *npins) +{ + struct th1520_pinctrl *thp =3D pinctrl_dev_get_drvdata(pctldev); + + *pins =3D &thp->desc.pins[gsel].number; + *npins =3D 1; + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static void th1520_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int pin) +{ + struct th1520_pinctrl *thp =3D pinctrl_dev_get_drvdata(pctldev); + void __iomem *padcfg =3D th1520_padcfg(thp, pin); + void __iomem *muxcfg =3D th1520_muxcfg(thp, pin); + u32 pad; + u32 mux; + + scoped_guard(raw_spinlock_irqsave, &thp->lock) { + pad =3D readl_relaxed(padcfg); + mux =3D readl_relaxed(muxcfg); + } + + seq_printf(s, "[PADCFG_%03u:0x%x=3D0x%07x MUXCFG_%03u:0x%x=3D0x%08x]", + 1 + pin / 2, 0x000 + 4 * (pin / 2), pad, + 1 + pin / 8, 0x400 + 4 * (pin / 8), mux); +} +#else +#define th1520_pin_dbg_show NULL +#endif + +static void th1520_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned int nmaps) +{ + unsigned long *seen =3D NULL; + unsigned int i; + + for (i =3D 0; i < nmaps; i++) { + if (map[i].type =3D=3D PIN_MAP_TYPE_CONFIGS_PIN && + map[i].data.configs.configs !=3D seen) { + seen =3D map[i].data.configs.configs; + kfree(seen); + } + } + + kfree(map); +} + +static int th1520_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **maps, + unsigned int *num_maps) +{ + struct th1520_pinctrl *thp =3D pinctrl_dev_get_drvdata(pctldev); + struct device_node *child; + struct pinctrl_map *map; + unsigned long *configs; + unsigned int nconfigs; + unsigned int nmaps; + int ret; + + nmaps =3D 0; + for_each_available_child_of_node(np, child) { + int npins =3D of_property_count_strings(child, "pins"); + + if (npins <=3D 0) { + of_node_put(child); + dev_err(thp->pctl->dev, "no pins selected for %pOFn.%pOFn\n", + np, child); + return -EINVAL; + } + nmaps +=3D npins; + if (of_property_present(child, "function")) + nmaps +=3D npins; + } + + map =3D kcalloc(nmaps, sizeof(*map), GFP_KERNEL); + if (!map) + return -ENOMEM; + + nmaps =3D 0; + mutex_lock(&thp->mutex); + for_each_available_child_of_node(np, child) { + unsigned int rollback =3D nmaps; + enum th1520_muxtype muxtype; + struct property *prop; + const char *funcname; + const char **pgnames; + const char *pinname; + int npins; + + ret =3D pinconf_generic_parse_dt_config(child, pctldev, &configs, &nconf= igs); + if (ret) { + dev_err(thp->pctl->dev, "%pOFn.%pOFn: error parsing pin config\n", + np, child); + goto put_child; + } + + if (!of_property_read_string(child, "function", &funcname)) { + muxtype =3D th1520_muxtype_get(funcname); + if (!muxtype) { + dev_err(thp->pctl->dev, "%pOFn.%pOFn: unknown function '%s'\n", + np, child, funcname); + ret =3D -EINVAL; + goto free_configs; + } + + funcname =3D devm_kasprintf(thp->pctl->dev, GFP_KERNEL, "%pOFn.%pOFn", + np, child); + if (!funcname) { + ret =3D -ENOMEM; + goto free_configs; + } + + npins =3D of_property_count_strings(child, "pins"); + pgnames =3D devm_kcalloc(thp->pctl->dev, npins, sizeof(*pgnames), GFP_K= ERNEL); + if (!pgnames) { + ret =3D -ENOMEM; + goto free_configs; + } + } else { + funcname =3D NULL; + } + + npins =3D 0; + of_property_for_each_string(child, "pins", prop, pinname) { + unsigned int i; + + for (i =3D 0; i < thp->desc.npins; i++) { + if (!strcmp(pinname, thp->desc.pins[i].name)) + break; + } + if (i =3D=3D thp->desc.npins) { + nmaps =3D rollback; + dev_err(thp->pctl->dev, "%pOFn.%pOFn: unknown pin '%s'\n", + np, child, pinname); + goto free_configs; + } + + if (nconfigs) { + map[nmaps].type =3D PIN_MAP_TYPE_CONFIGS_PIN; + map[nmaps].data.configs.group_or_pin =3D thp->desc.pins[i].name; + map[nmaps].data.configs.configs =3D configs; + map[nmaps].data.configs.num_configs =3D nconfigs; + nmaps +=3D 1; + } + if (funcname) { + pgnames[npins++] =3D thp->desc.pins[i].name; + map[nmaps].type =3D PIN_MAP_TYPE_MUX_GROUP; + map[nmaps].data.mux.function =3D funcname; + map[nmaps].data.mux.group =3D thp->desc.pins[i].name; + nmaps +=3D 1; + } + } + + if (funcname) { + ret =3D pinmux_generic_add_function(pctldev, funcname, pgnames, + npins, (void *)muxtype); + if (ret < 0) { + dev_err(thp->pctl->dev, "error adding function %s\n", funcname); + goto put_child; + } + } + } + + *maps =3D map; + *num_maps =3D nmaps; + mutex_unlock(&thp->mutex); + return 0; + +free_configs: + kfree(configs); +put_child: + of_node_put(child); + th1520_pinctrl_dt_free_map(pctldev, map, nmaps); + mutex_unlock(&thp->mutex); + return ret; +} + +static const struct pinctrl_ops th1520_pinctrl_ops =3D { + .get_groups_count =3D th1520_pinctrl_get_groups_count, + .get_group_name =3D th1520_pinctrl_get_group_name, + .get_group_pins =3D th1520_pinctrl_get_group_pins, + .pin_dbg_show =3D th1520_pin_dbg_show, + .dt_node_to_map =3D th1520_pinctrl_dt_node_to_map, + .dt_free_map =3D th1520_pinctrl_dt_free_map, +}; + +static const u8 th1520_drive_strength_in_ma[16] =3D { + 1, 2, 3, 5, 7, 8, 10, 12, 13, 15, 16, 18, 20, 21, 23, 25, +}; + +static u16 th1520_drive_strength_from_ma(u32 arg) +{ + u16 ds; + + for (ds =3D 0; ds < TH1520_PADCFG_DS; ds++) { + if (arg <=3D th1520_drive_strength_in_ma[ds]) + return ds; + } + return TH1520_PADCFG_DS; +} + +static int th1520_padcfg_rmw(struct th1520_pinctrl *thp, unsigned int pin, + u32 mask, u32 value) +{ + void __iomem *padcfg =3D th1520_padcfg(thp, pin); + unsigned int shift =3D th1520_padcfg_shift(pin); + u32 tmp; + + mask <<=3D shift; + value <<=3D shift; + + scoped_guard(raw_spinlock_irqsave, &thp->lock) { + tmp =3D readl_relaxed(padcfg); + tmp =3D (tmp & ~mask) | value; + writel_relaxed(tmp, padcfg); + } + return 0; +} + +static int th1520_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + struct th1520_pinctrl *thp =3D pinctrl_dev_get_drvdata(pctldev); + const struct pin_desc *desc =3D pin_desc_get(pctldev, pin); + bool enabled; + int param; + u32 value; + u32 arg; + + if ((uintptr_t)desc->drv_data & TH1520_PAD_NO_PADCFG) + return -EOPNOTSUPP; + + value =3D readl_relaxed(th1520_padcfg(thp, pin)); + value =3D (value >> th1520_padcfg_shift(pin)) & GENMASK(9, 0); + + param =3D pinconf_to_config_param(*config); + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + enabled =3D !(value & (TH1520_PADCFG_SPU | TH1520_PADCFG_PE)); + arg =3D 0; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + enabled =3D (value & TH1520_PADCFG_BIAS) =3D=3D TH1520_PADCFG_PE; + arg =3D enabled ? TH1520_PULL_DOWN_OHM : 0; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (value & TH1520_PADCFG_SPU) { + enabled =3D true; + arg =3D TH1520_PULL_STRONG_OHM; + } else if ((value & (TH1520_PADCFG_PE | TH1520_PADCFG_PS)) =3D=3D + (TH1520_PADCFG_PE | TH1520_PADCFG_PS)) { + enabled =3D true; + arg =3D TH1520_PULL_UP_OHM; + } else { + enabled =3D false; + arg =3D 0; + } + break; + case PIN_CONFIG_DRIVE_STRENGTH: + enabled =3D true; + arg =3D th1520_drive_strength_in_ma[value & TH1520_PADCFG_DS]; + break; + case PIN_CONFIG_INPUT_ENABLE: + enabled =3D value & TH1520_PADCFG_IE; + arg =3D enabled ? 1 : 0; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + enabled =3D value & TH1520_PADCFG_ST; + arg =3D enabled ? 1 : 0; + break; + case PIN_CONFIG_SLEW_RATE: + enabled =3D value & TH1520_PADCFG_SL; + arg =3D enabled ? 1 : 0; + break; + default: + return -EOPNOTSUPP; + } + + *config =3D pinconf_to_config_packed(param, arg); + return enabled ? 0 : -EINVAL; +} + +static int th1520_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int gsel, unsigned long *config) +{ + struct th1520_pinctrl *thp =3D pinctrl_dev_get_drvdata(pctldev); + unsigned int pin =3D thp->desc.pins[gsel].number; + + return th1520_pinconf_get(pctldev, pin, config); +} + +static int th1520_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pi= n, + unsigned long *configs, unsigned int num_configs) +{ + struct th1520_pinctrl *thp =3D pinctrl_dev_get_drvdata(pctldev); + const struct pin_desc *desc =3D pin_desc_get(pctldev, pin); + unsigned int i; + u16 mask, value; + + if ((uintptr_t)desc->drv_data & TH1520_PAD_NO_PADCFG) + return -EOPNOTSUPP; + + mask =3D 0; + value =3D 0; + for (i =3D 0; i < num_configs; i++) { + int param =3D pinconf_to_config_param(configs[i]); + u32 arg =3D pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + mask |=3D TH1520_PADCFG_BIAS; + value &=3D ~TH1520_PADCFG_BIAS; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (arg =3D=3D 0) + return -EOPNOTSUPP; + mask |=3D TH1520_PADCFG_BIAS; + value &=3D ~TH1520_PADCFG_BIAS; + value |=3D TH1520_PADCFG_PE; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (arg =3D=3D 0) + return -EOPNOTSUPP; + mask |=3D TH1520_PADCFG_BIAS; + value &=3D ~TH1520_PADCFG_BIAS; + if (arg =3D=3D TH1520_PULL_STRONG_OHM) + value |=3D TH1520_PADCFG_SPU; + else + value |=3D TH1520_PADCFG_PE | TH1520_PADCFG_PS; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + mask |=3D TH1520_PADCFG_DS; + value &=3D ~TH1520_PADCFG_DS; + value |=3D th1520_drive_strength_from_ma(arg); + break; + case PIN_CONFIG_INPUT_ENABLE: + mask |=3D TH1520_PADCFG_IE; + if (arg) + value |=3D TH1520_PADCFG_IE; + else + value &=3D ~TH1520_PADCFG_IE; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + mask |=3D TH1520_PADCFG_ST; + if (arg) + value |=3D TH1520_PADCFG_ST; + else + value &=3D ~TH1520_PADCFG_ST; + break; + case PIN_CONFIG_SLEW_RATE: + mask |=3D TH1520_PADCFG_SL; + if (arg) + value |=3D TH1520_PADCFG_SL; + else + value &=3D ~TH1520_PADCFG_SL; + break; + default: + return -EOPNOTSUPP; + } + } + + return th1520_padcfg_rmw(thp, pin, mask, value); +} + +static int th1520_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int gsel, + unsigned long *configs, + unsigned int num_configs) +{ + struct th1520_pinctrl *thp =3D pinctrl_dev_get_drvdata(pctldev); + unsigned int pin =3D thp->desc.pins[gsel].number; + + return th1520_pinconf_set(pctldev, pin, configs, num_configs); +} + +#ifdef CONFIG_DEBUG_FS +static void th1520_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int pin) +{ + struct th1520_pinctrl *thp =3D pinctrl_dev_get_drvdata(pctldev); + u32 value =3D readl_relaxed(th1520_padcfg(thp, pin)); + + value =3D (value >> th1520_padcfg_shift(pin)) & GENMASK(9, 0); + + seq_printf(s, " [0x%03x]", value); +} +#else +#define th1520_pinconf_dbg_show NULL +#endif + +static const struct pinconf_ops th1520_pinconf_ops =3D { + .pin_config_get =3D th1520_pinconf_get, + .pin_config_group_get =3D th1520_pinconf_group_get, + .pin_config_set =3D th1520_pinconf_set, + .pin_config_group_set =3D th1520_pinconf_group_set, + .pin_config_dbg_show =3D th1520_pinconf_dbg_show, + .is_generic =3D true, +}; + +static int th1520_pinmux_set(struct th1520_pinctrl *thp, unsigned int pin, + unsigned long muxdata, enum th1520_muxtype muxtype) +{ + void __iomem *muxcfg =3D th1520_muxcfg(thp, pin); + unsigned int shift =3D th1520_muxcfg_shift(pin); + u32 mask, value, tmp; + + for (value =3D 0; muxdata; muxdata >>=3D 5, value++) { + if ((muxdata & GENMASK(4, 0)) =3D=3D muxtype) + break; + } + if (!muxdata) { + dev_err(thp->pctl->dev, "invalid mux %s for pin %s\n", + th1520_muxtype_string[muxtype], pin_get_name(thp->pctl, pin)); + return -EINVAL; + } + + mask =3D GENMASK(3, 0) << shift; + value =3D value << shift; + + scoped_guard(raw_spinlock_irqsave, &thp->lock) { + tmp =3D readl_relaxed(muxcfg); + tmp =3D (tmp & ~mask) | value; + writel_relaxed(tmp, muxcfg); + } + return 0; +} + +static int th1520_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int fsel, unsigned int gsel) +{ + struct th1520_pinctrl *thp =3D pinctrl_dev_get_drvdata(pctldev); + const struct function_desc *func =3D pinmux_generic_get_function(pctldev,= fsel); + + return th1520_pinmux_set(thp, thp->desc.pins[gsel].number, + (uintptr_t)thp->desc.pins[gsel].drv_data & TH1520_PAD_MUXDATA, + (uintptr_t)func->data); +} + +static int th1520_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct th1520_pinctrl *thp =3D pinctrl_dev_get_drvdata(pctldev); + const struct pin_desc *desc =3D pin_desc_get(pctldev, offset); + + return th1520_pinmux_set(thp, offset, + (uintptr_t)desc->drv_data & TH1520_PAD_MUXDATA, + TH1520_MUX_GPIO); +} + +static int th1520_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset, bool input) +{ + struct th1520_pinctrl *thp =3D pinctrl_dev_get_drvdata(pctldev); + + return th1520_padcfg_rmw(thp, offset, TH1520_PADCFG_IE, + input ? TH1520_PADCFG_IE : 0); +} + +static const struct pinmux_ops th1520_pinmux_ops =3D { + .get_functions_count =3D pinmux_generic_get_function_count, + .get_function_name =3D pinmux_generic_get_function_name, + .get_function_groups =3D pinmux_generic_get_function_groups, + .set_mux =3D th1520_pinmux_set_mux, + .gpio_request_enable =3D th1520_gpio_request_enable, + .gpio_set_direction =3D th1520_gpio_set_direction, + .strict =3D true, +}; + +static int th1520_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + const struct th1520_pad_group *group; + struct device_node *np =3D dev->of_node; + struct th1520_pinctrl *thp; + struct clk *clk; + int ret; + + thp =3D devm_kzalloc(dev, sizeof(*thp), GFP_KERNEL); + if (!thp) + return -ENOMEM; + + thp->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(thp->base)) + return PTR_ERR(thp->base); + + clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "error getting clock\n"); + + if (strcmp(np->full_name, TH1520_PAD_GROUP1) =3D=3D 0) + group =3D &th1520_group1; + else if (strcmp(np->full_name, TH1520_PAD_GROUP2) =3D=3D 0) + group =3D &th1520_group2; + else if (strcmp(np->full_name, TH1520_PAD_GROUP3) =3D=3D 0) + group =3D &th1520_group3; + else + return dev_err_probe(dev, ret, "unit address did not match any pad group= \n"); + + thp->desc.name =3D group->name; + thp->desc.pins =3D group->pins; + thp->desc.npins =3D group->npins; + thp->desc.pctlops =3D &th1520_pinctrl_ops; + thp->desc.pmxops =3D &th1520_pinmux_ops; + thp->desc.confops =3D &th1520_pinconf_ops; + thp->desc.owner =3D THIS_MODULE; + mutex_init(&thp->mutex); + raw_spin_lock_init(&thp->lock); + + ret =3D devm_pinctrl_register_and_init(dev, &thp->desc, thp, &thp->pctl); + if (ret) + return dev_err_probe(dev, ret, "could not register pinctrl driver\n"); + + return pinctrl_enable(thp->pctl); +} + +static const struct of_device_id th1520_pinctrl_of_match[] =3D { + { .compatible =3D "thead,th1520-pinctrl"}, + { /* sentinel */ } +}; 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[75.164.215.68]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-715e569ef39sm7532701b3a.122.2024.09.02.21.08.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Sep 2024 21:08:54 -0700 (PDT) From: Drew Fustini Date: Mon, 02 Sep 2024 21:06:56 -0700 Subject: [PATCH 3/8] riscv: dts: thead: Add TH1520 pin control nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240902-th1520-pinctrl-v1-3-639bf83ef50a@tenstorrent.com> References: <20240902-th1520-pinctrl-v1-0-639bf83ef50a@tenstorrent.com> In-Reply-To: <20240902-th1520-pinctrl-v1-0-639bf83ef50a@tenstorrent.com> To: Drew Fustini , Guo Ren , Fu Wei , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Thomas Bonnefille , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini X-Mailer: b4 0.14.1 From: Emil Renner Berthing Add nodes for pin controllers on the T-Head TH1520 RISC-V SoC. Tested-by: Thomas Bonnefille Signed-off-by: Emil Renner Berthing Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ++++ .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ++++ arch/riscv/boot/dts/thead/th1520.dtsi | 24 ++++++++++++++++++= ++++ 3 files changed, 32 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/risc= v/boot/dts/thead/th1520-beaglev-ahead.dts index d9b4de9e4757..be85e3aee56e 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -44,6 +44,10 @@ &osc_32k { clock-frequency =3D <32768>; }; =20 +&aonsys_clk { + clock-frequency =3D <73728000>; +}; + &apb_clk { clock-frequency =3D <62500000>; }; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index 1365d3a512a3..530648ad64f6 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -25,6 +25,10 @@ &osc_32k { clock-frequency =3D <32768>; }; =20 +&aonsys_clk { + clock-frequency =3D <73728000>; +}; + &apb_clk { clock-frequency =3D <62500000>; }; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index 3c9974062c20..834dcd1fe7d8 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -215,6 +215,12 @@ osc_32k: 32k-oscillator { #clock-cells =3D <0>; }; =20 + aonsys_clk: aonsys-clk { + compatible =3D "fixed-clock"; + clock-output-names =3D "aonsys_clk"; + #clock-cells =3D <0>; + }; + apb_clk: apb-clk-clock { compatible =3D "fixed-clock"; clock-output-names =3D "apb_clk"; @@ -357,6 +363,12 @@ portd: gpio-controller@0 { }; }; =20 + padctrl1_apsys: pinctrl@ffe7f3c000 { + compatible =3D "thead,th1520-pinctrl"; + reg =3D <0xff 0xe7f3c000 0x0 0x1000>; + clocks =3D <&apb_clk>; + }; + gpio0: gpio@ffec005000 { compatible =3D "snps,dw-apb-gpio"; reg =3D <0xff 0xec005000 0x0 0x1000>; @@ -393,6 +405,12 @@ portb: gpio-controller@0 { }; }; =20 + padctrl0_apsys: pinctrl@ffec007000 { + compatible =3D "thead,th1520-pinctrl"; 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Adjust number of GPIOs available for the different controllers. Acked-by: Rob Herring Tested-by: Thomas Bonnefille Signed-off-by: Emil Renner Berthing Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index 834dcd1fe7d8..9889b557c494 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -338,6 +338,7 @@ portc: gpio-controller@0 { gpio-controller; #gpio-cells =3D <2>; ngpios =3D <32>; + gpio-ranges =3D <&padctrl0_apsys 0 0 32>; reg =3D <0>; interrupt-controller; #interrupt-cells =3D <2>; @@ -355,7 +356,8 @@ portd: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells =3D <2>; - ngpios =3D <32>; + ngpios =3D <23>; + gpio-ranges =3D <&padctrl0_apsys 0 32 23>; reg =3D <0>; interrupt-controller; #interrupt-cells =3D <2>; @@ -380,6 +382,7 @@ porta: gpio-controller@0 { gpio-controller; #gpio-cells =3D <2>; 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[75.164.215.68]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-715e569ef39sm7532701b3a.122.2024.09.02.21.08.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Sep 2024 21:08:56 -0700 (PDT) From: Drew Fustini Date: Mon, 02 Sep 2024 21:06:58 -0700 Subject: [PATCH 5/8] riscv: dts: thead: Adjust TH1520 GPIO labels Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240902-th1520-pinctrl-v1-5-639bf83ef50a@tenstorrent.com> References: <20240902-th1520-pinctrl-v1-0-639bf83ef50a@tenstorrent.com> In-Reply-To: <20240902-th1520-pinctrl-v1-0-639bf83ef50a@tenstorrent.com> To: Drew Fustini , Guo Ren , Fu Wei , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Thomas Bonnefille , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini X-Mailer: b4 0.14.1 From: Emil Renner Berthing Adjust labels for the TH1520 GPIO controllers such that GPIOs can be referenced by the names used by the documentation. Eg. GPIO0_X -> <&gpio0 X Y> GPIO1_X -> <&gpio1 X Y> GPIO2_X -> <&gpio2 X Y> GPIO3_X -> <&gpio3 X Y> GPIO4_X -> <&gpio4 X Y> AOGPIO_X -> <&aogpio X Y> Remove labels for the parent GPIO devices that shouldn't need to be referenced. Tested-by: Thomas Bonnefille Signed-off-by: Emil Renner Berthing Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 2 ++ arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts | 2 ++ arch/riscv/boot/dts/thead/th1520.dtsi | 24 +++++++++++-------= ---- 3 files changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/risc= v/boot/dts/thead/th1520-beaglev-ahead.dts index be85e3aee56e..c48f6fd6387b 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -17,6 +17,8 @@ aliases { gpio1 =3D &gpio1; gpio2 =3D &gpio2; gpio3 =3D &gpio3; + gpio4 =3D &gpio4; + gpio5 =3D &aogpio; serial0 =3D &uart0; serial1 =3D &uart1; serial2 =3D &uart2; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv= /boot/dts/thead/th1520-lichee-pi-4a.dts index 9a3884a73e13..0ae2c20d5641 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -14,6 +14,8 @@ aliases { gpio1 =3D &gpio1; gpio2 =3D &gpio2; gpio3 =3D &gpio3; + gpio4 =3D &gpio4; + gpio5 =3D &aogpio; serial0 =3D &uart0; serial1 =3D &uart1; serial2 =3D &uart2; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index 9889b557c494..ca93a265fa56 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -327,13 +327,13 @@ uart3: serial@ffe7f04000 { status =3D "disabled"; }; =20 - gpio2: gpio@ffe7f34000 { + gpio@ffe7f34000 { compatible =3D "snps,dw-apb-gpio"; reg =3D <0xff 0xe7f34000 0x0 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; =20 - portc: gpio-controller@0 { + gpio2: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells =3D <2>; @@ -346,13 +346,13 @@ portc: gpio-controller@0 { }; }; =20 - gpio3: gpio@ffe7f38000 { + gpio@ffe7f38000 { compatible =3D "snps,dw-apb-gpio"; reg =3D <0xff 0xe7f38000 0x0 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; =20 - portd: gpio-controller@0 { + gpio3: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells =3D <2>; @@ -371,13 +371,13 @@ padctrl1_apsys: pinctrl@ffe7f3c000 { clocks =3D <&apb_clk>; }; =20 - gpio0: gpio@ffec005000 { + gpio@ffec005000 { compatible =3D "snps,dw-apb-gpio"; reg =3D <0xff 0xec005000 0x0 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; =20 - porta: gpio-controller@0 { + gpio0: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells =3D <2>; @@ -390,13 +390,13 @@ porta: gpio-controller@0 { }; }; =20 - gpio1: gpio@ffec006000 { + gpio@ffec006000 { compatible =3D "snps,dw-apb-gpio"; reg =3D <0xff 0xec006000 0x0 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; =20 - portb: gpio-controller@0 { + gpio1: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells =3D <2>; @@ -533,13 +533,13 @@ timer7: timer@ffffc3303c { status =3D "disabled"; }; =20 - ao_gpio0: gpio@fffff41000 { + gpio@fffff41000 { compatible =3D "snps,dw-apb-gpio"; reg =3D <0xff 0xfff41000 0x0 0x1000>; #address-cells =3D <1>; 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[75.164.215.68]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-715e569ef39sm7532701b3a.122.2024.09.02.21.08.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Sep 2024 21:08:57 -0700 (PDT) From: Drew Fustini Date: Mon, 02 Sep 2024 21:06:59 -0700 Subject: [PATCH 6/8] riscv: dts: thead: Add Lichee Pi 4M GPIO line names Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240902-th1520-pinctrl-v1-6-639bf83ef50a@tenstorrent.com> References: <20240902-th1520-pinctrl-v1-0-639bf83ef50a@tenstorrent.com> In-Reply-To: <20240902-th1520-pinctrl-v1-0-639bf83ef50a@tenstorrent.com> To: Drew Fustini , Guo Ren , Fu Wei , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Thomas Bonnefille , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini X-Mailer: b4 0.14.1 From: Emil Renner Berthing Add names for the GPIO00-GPIO14 lines of the SO-DIMM module. Tested-by: Thomas Bonnefille Signed-off-by: Emil Renner Berthing Signed-off-by: Drew Fustini --- .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 39 ++++++++++++++++++= ++++ 1 file changed, 39 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index 530648ad64f6..276f7e8a2c9b 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -41,6 +41,12 @@ &uart_sclk { clock-frequency =3D <100000000>; }; =20 +&aogpio { + gpio-line-names =3D "", "", "", + "GPIO00", + "GPIO04"; +}; + &dmac0 { status =3D "okay"; }; @@ -60,3 +66,36 @@ &sdio0 { max-frequency =3D <198000000>; status =3D "okay"; }; + +&gpio0 { + gpio-line-names =3D "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", + "GPIO07", + "GPIO08", + "", + "GPIO01", + "GPIO02"; +}; + +&gpio1 { + gpio-line-names =3D "", "", "", + "GPIO11", + "GPIO12", + "GPIO13", + "GPIO14", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", + "GPIO06"; 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[75.164.215.68]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-715e569ef39sm7532701b3a.122.2024.09.02.21.08.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Sep 2024 21:08:58 -0700 (PDT) From: Drew Fustini Date: Mon, 02 Sep 2024 21:07:00 -0700 Subject: [PATCH 7/8] riscv: dts: thead: Add TH1520 pinctrl settings for UART0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240902-th1520-pinctrl-v1-7-639bf83ef50a@tenstorrent.com> References: <20240902-th1520-pinctrl-v1-0-639bf83ef50a@tenstorrent.com> In-Reply-To: <20240902-th1520-pinctrl-v1-0-639bf83ef50a@tenstorrent.com> To: Drew Fustini , Guo Ren , Fu Wei , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Thomas Bonnefille , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini X-Mailer: b4 0.14.1 From: Emil Renner Berthing Add pinctrl settings for UART0 used as the default debug console on both the Lichee Pi 4A and BeagleV Ahead boards. Tested-by: Thomas Bonnefille Signed-off-by: Emil Renner Berthing Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 26 ++++++++++++++++++= ++++ arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts | 26 ++++++++++++++++++= ++++ 2 files changed, 52 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/risc= v/boot/dts/thead/th1520-beaglev-ahead.dts index c48f6fd6387b..c5356f674f85 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -82,6 +82,32 @@ &sdio0 { status =3D "okay"; }; =20 +&padctrl0_apsys { + uart0_pins: uart0-0 { + tx-pins { + pins =3D "UART0_TXD"; + function =3D "uart"; + bias-disable; + drive-strength =3D <3>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + rx-pins { + pins =3D "UART0_RXD"; + function =3D "uart"; + bias-disable; + drive-strength =3D <1>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + }; +}; + &uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pins>; status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv= /boot/dts/thead/th1520-lichee-pi-4a.dts index 0ae2c20d5641..932838c55f90 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -29,6 +29,32 @@ chosen { }; }; =20 +&padctrl0_apsys { + uart0_pins: uart0-0 { + tx-pins { + pins =3D "UART0_TXD"; + function =3D "uart"; + bias-disable; + drive-strength =3D <3>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + rx-pins { + pins =3D "UART0_RXD"; + function =3D "uart"; + bias-disable; + drive-strength =3D <1>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + }; +}; + &uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pins>; status =3D "okay"; }; --=20 2.34.1 From nobody Mon Feb 9 04:04:41 2026 Received: from mail-pf1-f180.google.com (mail-pf1-f180.google.com [209.85.210.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDC1D1CFEA3 for ; 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[75.164.215.68]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-715e569ef39sm7532701b3a.122.2024.09.02.21.08.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Sep 2024 21:08:59 -0700 (PDT) From: Drew Fustini Date: Mon, 02 Sep 2024 21:07:01 -0700 Subject: [PATCH 8/8] riscv: dtb: thead: Add BeagleV Ahead LEDs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240902-th1520-pinctrl-v1-8-639bf83ef50a@tenstorrent.com> References: <20240902-th1520-pinctrl-v1-0-639bf83ef50a@tenstorrent.com> In-Reply-To: <20240902-th1520-pinctrl-v1-0-639bf83ef50a@tenstorrent.com> To: Drew Fustini , Guo Ren , Fu Wei , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Thomas Bonnefille , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini X-Mailer: b4 0.14.1 From: Emil Renner Berthing Add nodes for the 5 user controllable LEDs on the BeagleV Ahead board. Tested-by: Thomas Bonnefille Signed-off-by: Emil Renner Berthing Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 55 ++++++++++++++++++= ++++ 1 file changed, 55 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/risc= v/boot/dts/thead/th1520-beaglev-ahead.dts index c5356f674f85..823aa5b44efb 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -7,6 +7,8 @@ /dts-v1/; =20 #include "th1520.dtsi" +#include +#include =20 / { model =3D "BeagleV Ahead"; @@ -34,7 +36,42 @@ chosen { memory@0 { device_type =3D "memory"; reg =3D <0x0 0x00000000 0x1 0x00000000>; + }; + + leds { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&led_pins>; + compatible =3D "gpio-leds"; + + led-1 { + gpios =3D <&gpio4 8 GPIO_ACTIVE_LOW>; + color =3D ; + label =3D "led1"; + }; + + led-2 { + gpios =3D <&gpio4 9 GPIO_ACTIVE_LOW>; + color =3D ; + label =3D "led2"; + }; + + led-3 { + gpios =3D <&gpio4 10 GPIO_ACTIVE_LOW>; + color =3D ; + label =3D "led3"; + }; + + led-4 { + gpios =3D <&gpio4 11 GPIO_ACTIVE_LOW>; + color =3D ; + label =3D "led4"; + }; =20 + led-5 { + gpios =3D <&gpio4 12 GPIO_ACTIVE_LOW>; + color =3D ; + label =3D "led5"; + }; }; }; =20 @@ -82,6 +119,24 @@ &sdio0 { status =3D "okay"; }; =20 +&padctrl_aosys { + led_pins: led-0 { + led-pins { + pins =3D "AUDIO_PA8", /* GPIO4_8 */ + "AUDIO_PA9", /* GPIO4_9 */ + "AUDIO_PA10", /* GPIO4_10 */ + "AUDIO_PA11", /* GPIO4_11 */ + "AUDIO_PA12"; /* GPIO4_12 */ + function =3D "gpio"; + bias-disable; + drive-strength =3D <3>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + }; +}; + &padctrl0_apsys { uart0_pins: uart0-0 { tx-pins { --=20 2.34.1