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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240831-dts-nxp-imx6-pinctrl-v1-3-f5811032bd40@linaro.org> References: <20240831-dts-nxp-imx6-pinctrl-v1-0-f5811032bd40@linaro.org> In-Reply-To: <20240831-dts-nxp-imx6-pinctrl-v1-0-f5811032bd40@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=3663; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=vspvOoNdVly/5eQ+t11qHO7HcxpjaE+0iVeN2RnyGgg=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBm0vBJXUi51Ko8Il1rVfJDexnVawyZr3r+BI/MD +WOIrZntxSJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZtLwSQAKCRDBN2bmhouD 1x1ED/9PTXDsWsQs5Ve0Z465ZGBT6bPfNxJ/OcbV/Ma4iZM9Wh2veOT7I9p3aUYtTp1kCVBADzO 7MsYIefzrZy1YmMqV6p9jCvLBXPTw4vu6ewoJQ1j1UPaDc0N2VmUhEvU/gzeUZ8lWvvwzZlLn1H AO+YPXYPpUrClsRQSVKOQSlih9YhzjG+PlWUhM/ju0CeA8ILFuJt2xgkajKUZ9lnFAnwMnaYVa1 hDalGF0lLK92xj+6x5JZ88b1+oBbE15DAlP/VgqXFlhDS/5/uHoatJ/57+bHmg6sWvLJo4Rcaot xeuyxuHyFYGEPmcih4KquV3PXs9AeIBa6ZN/8mTM3FPm/ux9vDC6D29Vovkrl+MNdTuXG321Hrm UqVsuqPiU6Gyi/1wcWV+c6aCG2vp8p7c3qVpQ9GzRbdxbIvus4uvvj9xNOKRP7M/rg6MUezAHH0 MP10sfaTrn8Va2mTwkWDTae3TFPjRM0KM07+tAkySWOTXNnP7Woh6rVl0wLvs9UXA+61X6on1+G P7IdlWC2zWyu2pseTkgYqq2xHKgxWk3MVCnO45szNoN+XIE8/zOyUzkxePONKxt0MI0tnJx3Omb 8vCDfwDTsUESnubqZZOvlDAyZKC5sdkCAHn1XmCQlxoYK8KlfiVqz4ki/jbcx6VLbpZPrgvEIWZ cYdKSYwuK4anzRw== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Bindings for other NXP pin controllers expect pin configuration nodes in pinctrl to match certain naming, so adjust these as well, even though their bindings are not yet in dtschema format. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts | 12 ++++++------ arch/arm/boot/dts/nxp/imx/imx6sl-warp.dts | 8 ++++---- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts b/arch/arm/boot/dts/n= xp/imx/imx6sl-evk.dts index 31eee0419af7..7c899291ab0d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts @@ -457,7 +457,7 @@ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059 >; }; =20 - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { fsl,pins =3D < MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9 @@ -472,7 +472,7 @@ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9 >; }; =20 - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { fsl,pins =3D < MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9 @@ -498,7 +498,7 @@ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 >; }; =20 - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { fsl,pins =3D < MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9 @@ -509,7 +509,7 @@ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 >; }; =20 - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { fsl,pins =3D < MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9 @@ -531,7 +531,7 @@ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059 >; }; =20 - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { fsl,pins =3D < MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9 @@ -542,7 +542,7 @@ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 >; }; =20 - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { fsl,pins =3D < MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9 diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-warp.dts b/arch/arm/boot/dts/= nxp/imx/imx6sl-warp.dts index 9d7c8884892a..2545c0fe47c8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sl-warp.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sl-warp.dts @@ -166,7 +166,7 @@ MX6SL_PAD_SD2_RST__SD2_RESET 0x417059 >; }; =20 - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { fsl,pins =3D < MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170b9 MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100b9 @@ -182,7 +182,7 @@ MX6SL_PAD_SD2_RST__SD2_RESET 0x4170b9 >; }; =20 - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { fsl,pins =3D < MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170f9 MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100f9 @@ -209,7 +209,7 @@ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x417059 >; }; =20 - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { fsl,pins =3D < MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170b9 MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100b9 @@ -220,7 +220,7 @@ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170b9 >; }; =20 - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { fsl,pins =3D < MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170f9 MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100f9 --=20 2.43.0