From nobody Fri Dec 19 07:24:11 2025 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 331FC192D80 for ; Fri, 30 Aug 2024 11:04:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725015842; cv=none; b=aC7mSW+5WalbUT29z1QEv1O5YRkD7qxE3VKNNq2WHggjPv2efE5oaY0xyBPW4pLFn6y3OFx6My+UERKiK1DD8RjQhj1sx2zUAT8cmpheTjiNcaMnPnLevAaSJrfxyMb/ze1jdO0IHH4bUOqzSydrXZlpD1dnPCgVei21C3F7AwA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725015842; c=relaxed/simple; bh=+K0m8Z/tfxXArd2ca1OsFLwOmWFwm4/wH1OpiRtKoks=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=AP9CWtjMFknJshs4icQmF4xRiOzHiAHdh72NvkxbrI5DEBdJvk2cB/tFXTs39r3QLX1da2Rr4J0y+W3Q0xDmhyJ482Xl8JeuCM/NaO8QeY0PfDFawL6ewi+iIBn+NLcw3/zTvpkcX3JcSrd7WJbNXvRWnnQOuUmnrE/qsOuCjDQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--smostafa.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=vpSJMhIk; arc=none smtp.client-ip=209.85.128.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--smostafa.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="vpSJMhIk" Received: by mail-yw1-f201.google.com with SMTP id 00721157ae682-6d4bd76f5a8so823007b3.0 for ; Fri, 30 Aug 2024 04:04:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1725015840; x=1725620640; darn=vger.kernel.org; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:from:to:cc:subject:date:message-id :reply-to; bh=Ic37IELEQRRYuBS18VKDjuHeMlY5e56pj2JA+eqlY6M=; b=vpSJMhIkQphVoJiPZN9lf+Tu5LHoEUwey9OUGFj14bH9K7Qm2LK8nL9wFJn2fgEcy2 KirN2jG7TKZf2IsQrSZLzfvtKkj40BYk1wvfuAdlQgs50hdF5vRyG2pnxZU74NEi+uJn JZUXJIj9ixdnwLKYCeKaYqgN5i4X0oTRvIZiNU4p+iiENF10hABWpDbQU2PBIiaq8Iwf qk9hKTkMmLeuOKRzY4KRQFutYAfGktciE0R5LXIsxhQ/K8Eec4IObDL/TdXjRqVlV9Jb n8ZJA8ciVlTm5Z4MTXh922UQSEX71TRQzL1YxX9eo7EOgqTtbPnJOGu8nDeC5zwPbstw TKjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1725015840; x=1725620640; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to; bh=Ic37IELEQRRYuBS18VKDjuHeMlY5e56pj2JA+eqlY6M=; b=jTTlWN3Z4djS6tQ9//EolCni0dM0THIvUIeOtyOq0KPYPfZ3pRqELQC3RJ89Non9hc KmzCEBXdVeMCFaQ/yNOKkZZPeRzEeyzI+PyDCb/5GBYAq1rj05U8YW4g1hkxHHHaRZBx Zy3kyBERy7VdDzB3qUVAc5vRQr/hg5zf+WYvGoeQKCbDSfe11kZ8us/wMiYEtuSbeVAK IgfEwkdjT+5b+VniCvkDZBqr4sGJJJulChYKzSTibVz1Ubety1whRtuuYDBcIVMOkwKV fnviAbEhuRe+uKSexwH6tM7Cx6Kc20HE6jO3fTZG6PPpdIc1MLQL8BBN5bHGPT9kSMn/ SgXQ== X-Gm-Message-State: AOJu0Yx6bOpl7TeEk3H2MZnFUw8PuUVqQ/jXXE813G6/t9u0G/+vTwfE STmVQV2ynMw6BgQe4/80YHrgp1ECYOiH8L4jElyorHfgNtpjj0IOP2ObZgOOsV/X42GVRwc4J+F F8gJ8tjNt4CCDoIhX2urEdwkRwx2tgm8WhfVGoJAr/f1RZRFqpNBfRPoZFgmCfivk3hV6DY+wRl g/Lrbprg9N7mhQQE0hSvewL6Hj2ii2x8VMWne1K6m6S52gPPYdPgI= X-Google-Smtp-Source: AGHT+IEhIgqCCVpoJF04izZWNpGhj9w4DRkBO4N4vRbTNO83ovpMlTZbUepHXnCpHONa5Hk4mWllX9/lH0OXjQ== X-Received: from mostafa.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:333c]) (user=smostafa job=sendgmr) by 2002:a05:690c:3744:b0:64b:5cc7:bcb7 with SMTP id 00721157ae682-6d40d890122mr37757b3.1.1725015839642; Fri, 30 Aug 2024 04:03:59 -0700 (PDT) Date: Fri, 30 Aug 2024 11:03:47 +0000 In-Reply-To: <20240830110349.797399-1-smostafa@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240830110349.797399-1-smostafa@google.com> X-Mailer: git-send-email 2.46.0.469.g59c65b2a67-goog Message-ID: <20240830110349.797399-2-smostafa@google.com> Subject: [PATCH v4 1/2] iommu/arm-smmu-v3: Match Stall behaviour for S2 From: Mostafa Saleh To: linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, will@kernel.org, robin.murphy@arm.com, joro@8bytes.org Cc: jean-philippe@linaro.org, jgg@ziepe.ca, nicolinc@nvidia.com, mshavit@google.com, Mostafa Saleh Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" According to the spec (ARM IHI 0070 F.b), in "5.5 Fault configuration (A, R, S bits)": A STE with stage 2 translation enabled and STE.S2S =3D=3D 0 is considered ILLEGAL if SMMU_IDR0.STALL_MODEL =3D=3D 0b10. Also described in the pseudocode =E2=80=9CSteIllegal()=E2=80=9D if STE.Config =3D=3D '11x' then [..] if eff_idr0_stall_model =3D=3D '10' && STE.S2S =3D=3D '0' then // stall_model forcing stall, but S2S =3D=3D 0 return TRUE; Which means, S2S must be set when stall model is "ARM_SMMU_FEAT_STALL_FORCE", but currently the driver ignores that. Although, the driver can do the minimum and only set S2S for =E2=80=9CARM_SMMU_FEAT_STALL_FORCE=E2=80=9D, it is more consistent to match= S1 behaviour, which also sets it for =E2=80=9CARM_SMMU_FEAT_STALL=E2=80=9D if = the master has requested stalls. Also, since S2 stalls are enabled now, report them to the IOMMU layer and for VFIO devices it will fail anyway as VFIO doesn=E2=80=99t register an iopf handler. Signed-off-by: Mostafa Saleh Reviewed-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 8 +++----- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index a31460f9f3d4..a0044ff2facf 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1012,7 +1012,8 @@ void arm_smmu_get_ste_used(const __le64 *ent, __le64 = *used_bits) used_bits[2] |=3D cpu_to_le64(STRTAB_STE_2_S2VMID | STRTAB_STE_2_VTCR | STRTAB_STE_2_S2AA64 | STRTAB_STE_2_S2ENDI | - STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2R); + STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2S | + STRTAB_STE_2_S2R); used_bits[3] |=3D cpu_to_le64(STRTAB_STE_3_S2TTB_MASK); } =20 @@ -1646,6 +1647,7 @@ void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste = *target, STRTAB_STE_2_S2ENDI | #endif STRTAB_STE_2_S2PTW | + (master->stall_enabled ? STRTAB_STE_2_S2S : 0) | STRTAB_STE_2_S2R); =20 target->data[3] =3D cpu_to_le64(pgtbl_cfg->arm_lpae_s2_cfg.vttbr & @@ -1739,10 +1741,6 @@ static int arm_smmu_handle_evt(struct arm_smmu_devic= e *smmu, u64 *evt) return -EOPNOTSUPP; } =20 - /* Stage-2 is always pinned at the moment */ - if (evt[1] & EVTQ_1_S2) - return -EFAULT; - if (!(evt[1] & EVTQ_1_STALL)) return -EOPNOTSUPP; =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 14bca41a981b..0dc7ad43c64c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -267,6 +267,7 @@ struct arm_smmu_ste { #define STRTAB_STE_2_S2AA64 (1UL << 51) #define STRTAB_STE_2_S2ENDI (1UL << 52) #define STRTAB_STE_2_S2PTW (1UL << 54) +#define STRTAB_STE_2_S2S (1UL << 57) #define STRTAB_STE_2_S2R (1UL << 58) =20 #define STRTAB_STE_3_S2TTB_MASK GENMASK_ULL(51, 4) --=20 2.46.0.469.g59c65b2a67-goog From nobody Fri Dec 19 07:24:11 2025 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D42D179652 for ; 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Fri, 30 Aug 2024 04:04:02 -0700 (PDT) Date: Fri, 30 Aug 2024 11:03:48 +0000 In-Reply-To: <20240830110349.797399-1-smostafa@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240830110349.797399-1-smostafa@google.com> X-Mailer: git-send-email 2.46.0.469.g59c65b2a67-goog Message-ID: <20240830110349.797399-3-smostafa@google.com> Subject: [PATCH v4 2/2] iommu/arm-smmu-v3-test: Test masters with stall enabled From: Mostafa Saleh To: linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, will@kernel.org, robin.murphy@arm.com, joro@8bytes.org Cc: jean-philippe@linaro.org, jgg@ziepe.ca, nicolinc@nvidia.com, mshavit@google.com, Mostafa Saleh Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" At the moment, the SMMUv3 unit tests assume ATS is always enabled, although this is sufficient to test hitless/non-hitless transitions, but exercising other features is useful to check ste/cd population logic (for example the .get_used logic). Add an enum where bits define features per-master, at the moment there is only ATS and STALLs which are mutually exclusive, but this would make it easier to extend with other features in the future. Also, Add 2 more tests for s1 <-> s2 transitions with stalls enabled. Signed-off-by: Mostafa Saleh --- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 83 ++++++++++++++----- 1 file changed, 62 insertions(+), 21 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index cceb737a7001..84baa021370a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -30,6 +30,11 @@ static struct mm_struct sva_mm =3D { .pgd =3D (void *)0xdaedbeefdeadbeefULL, }; =20 +enum arm_smmu_test_master_feat { + ARM_SMMU_MASTER_TEST_ATS =3D BIT(0), + ARM_SMMU_MASTER_TEST_STALL =3D BIT(1), +}; + static bool arm_smmu_entry_differs_in_used_bits(const __le64 *entry, const __le64 *used_bits, const __le64 *target, @@ -164,16 +169,22 @@ static const dma_addr_t fake_cdtab_dma_addr =3D 0xF0F= 0F0F0F0F0; =20 static void arm_smmu_test_make_cdtable_ste(struct arm_smmu_ste *ste, unsigned int s1dss, - const dma_addr_t dma_addr) + const dma_addr_t dma_addr, + enum arm_smmu_test_master_feat feat) { + bool ats_enabled =3D feat & ARM_SMMU_MASTER_TEST_ATS; + bool stall_enabled =3D feat & ARM_SMMU_MASTER_TEST_STALL; + struct arm_smmu_master master =3D { + .ats_enabled =3D ats_enabled, .cd_table.cdtab_dma =3D dma_addr, .cd_table.s1cdmax =3D 0xFF, .cd_table.s1fmt =3D STRTAB_STE_0_S1FMT_64K_L2, .smmu =3D &smmu, + .stall_enabled =3D stall_enabled, }; =20 - arm_smmu_make_cdtable_ste(ste, &master, true, s1dss); + arm_smmu_make_cdtable_ste(ste, &master, ats_enabled, s1dss); } =20 static void arm_smmu_v3_write_ste_test_bypass_to_abort(struct kunit *test) @@ -204,7 +215,7 @@ static void arm_smmu_v3_write_ste_test_cdtable_to_abort= (struct kunit *test) struct arm_smmu_ste ste; =20 arm_smmu_test_make_cdtable_ste(&ste, STRTAB_STE_1_S1DSS_SSID0, - fake_cdtab_dma_addr); + fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_ATS); arm_smmu_v3_test_ste_expect_hitless_transition(test, &ste, &abort_ste, NUM_EXPECTED_SYNCS(2)); } @@ -214,7 +225,7 @@ static void arm_smmu_v3_write_ste_test_abort_to_cdtable= (struct kunit *test) struct arm_smmu_ste ste; =20 arm_smmu_test_make_cdtable_ste(&ste, STRTAB_STE_1_S1DSS_SSID0, - fake_cdtab_dma_addr); + fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_ATS); arm_smmu_v3_test_ste_expect_hitless_transition(test, &abort_ste, &ste, NUM_EXPECTED_SYNCS(2)); } @@ -224,7 +235,7 @@ static void arm_smmu_v3_write_ste_test_cdtable_to_bypas= s(struct kunit *test) struct arm_smmu_ste ste; =20 arm_smmu_test_make_cdtable_ste(&ste, STRTAB_STE_1_S1DSS_SSID0, - fake_cdtab_dma_addr); + fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_ATS); arm_smmu_v3_test_ste_expect_hitless_transition(test, &ste, &bypass_ste, NUM_EXPECTED_SYNCS(3)); } @@ -234,7 +245,7 @@ static void arm_smmu_v3_write_ste_test_bypass_to_cdtabl= e(struct kunit *test) struct arm_smmu_ste ste; =20 arm_smmu_test_make_cdtable_ste(&ste, STRTAB_STE_1_S1DSS_SSID0, - fake_cdtab_dma_addr); + fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_ATS); arm_smmu_v3_test_ste_expect_hitless_transition(test, &bypass_ste, &ste, NUM_EXPECTED_SYNCS(3)); } @@ -245,9 +256,9 @@ static void arm_smmu_v3_write_ste_test_cdtable_s1dss_ch= ange(struct kunit *test) struct arm_smmu_ste s1dss_bypass; =20 arm_smmu_test_make_cdtable_ste(&ste, STRTAB_STE_1_S1DSS_SSID0, - fake_cdtab_dma_addr); + fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_ATS); arm_smmu_test_make_cdtable_ste(&s1dss_bypass, STRTAB_STE_1_S1DSS_BYPASS, - fake_cdtab_dma_addr); + fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_ATS); =20 /* * Flipping s1dss on a CD table STE only involves changes to the second @@ -265,7 +276,7 @@ arm_smmu_v3_write_ste_test_s1dssbypass_to_stebypass(str= uct kunit *test) struct arm_smmu_ste s1dss_bypass; =20 arm_smmu_test_make_cdtable_ste(&s1dss_bypass, STRTAB_STE_1_S1DSS_BYPASS, - fake_cdtab_dma_addr); + fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_ATS); arm_smmu_v3_test_ste_expect_hitless_transition( test, &s1dss_bypass, &bypass_ste, NUM_EXPECTED_SYNCS(2)); } @@ -276,16 +287,20 @@ arm_smmu_v3_write_ste_test_stebypass_to_s1dssbypass(s= truct kunit *test) struct arm_smmu_ste s1dss_bypass; =20 arm_smmu_test_make_cdtable_ste(&s1dss_bypass, STRTAB_STE_1_S1DSS_BYPASS, - fake_cdtab_dma_addr); + fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_ATS); arm_smmu_v3_test_ste_expect_hitless_transition( test, &bypass_ste, &s1dss_bypass, NUM_EXPECTED_SYNCS(2)); } =20 static void arm_smmu_test_make_s2_ste(struct arm_smmu_ste *ste, - bool ats_enabled) + enum arm_smmu_test_master_feat feat) { + bool ats_enabled =3D feat & ARM_SMMU_MASTER_TEST_ATS; + bool stall_enabled =3D feat & ARM_SMMU_MASTER_TEST_STALL; struct arm_smmu_master master =3D { + .ats_enabled =3D ats_enabled, .smmu =3D &smmu, + .stall_enabled =3D stall_enabled, }; struct io_pgtable io_pgtable =3D {}; struct arm_smmu_domain smmu_domain =3D { @@ -308,7 +323,7 @@ static void arm_smmu_v3_write_ste_test_s2_to_abort(stru= ct kunit *test) { struct arm_smmu_ste ste; =20 - arm_smmu_test_make_s2_ste(&ste, true); + arm_smmu_test_make_s2_ste(&ste, ARM_SMMU_MASTER_TEST_ATS); arm_smmu_v3_test_ste_expect_hitless_transition(test, &ste, &abort_ste, NUM_EXPECTED_SYNCS(2)); } @@ -317,7 +332,7 @@ static void arm_smmu_v3_write_ste_test_abort_to_s2(stru= ct kunit *test) { struct arm_smmu_ste ste; =20 - arm_smmu_test_make_s2_ste(&ste, true); + arm_smmu_test_make_s2_ste(&ste, ARM_SMMU_MASTER_TEST_ATS); arm_smmu_v3_test_ste_expect_hitless_transition(test, &abort_ste, &ste, NUM_EXPECTED_SYNCS(2)); } @@ -326,7 +341,7 @@ static void arm_smmu_v3_write_ste_test_s2_to_bypass(str= uct kunit *test) { struct arm_smmu_ste ste; =20 - arm_smmu_test_make_s2_ste(&ste, true); + arm_smmu_test_make_s2_ste(&ste, ARM_SMMU_MASTER_TEST_ATS); arm_smmu_v3_test_ste_expect_hitless_transition(test, &ste, &bypass_ste, NUM_EXPECTED_SYNCS(2)); } @@ -335,7 +350,7 @@ static void arm_smmu_v3_write_ste_test_bypass_to_s2(str= uct kunit *test) { struct arm_smmu_ste ste; =20 - arm_smmu_test_make_s2_ste(&ste, true); + arm_smmu_test_make_s2_ste(&ste, ARM_SMMU_MASTER_TEST_ATS); arm_smmu_v3_test_ste_expect_hitless_transition(test, &bypass_ste, &ste, NUM_EXPECTED_SYNCS(2)); } @@ -346,8 +361,8 @@ static void arm_smmu_v3_write_ste_test_s1_to_s2(struct = kunit *test) struct arm_smmu_ste s2_ste; =20 arm_smmu_test_make_cdtable_ste(&s1_ste, STRTAB_STE_1_S1DSS_SSID0, - fake_cdtab_dma_addr); - arm_smmu_test_make_s2_ste(&s2_ste, true); + fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_ATS); + arm_smmu_test_make_s2_ste(&s2_ste, ARM_SMMU_MASTER_TEST_ATS); arm_smmu_v3_test_ste_expect_hitless_transition(test, &s1_ste, &s2_ste, NUM_EXPECTED_SYNCS(3)); } @@ -358,8 +373,8 @@ static void arm_smmu_v3_write_ste_test_s2_to_s1(struct = kunit *test) struct arm_smmu_ste s2_ste; =20 arm_smmu_test_make_cdtable_ste(&s1_ste, STRTAB_STE_1_S1DSS_SSID0, - fake_cdtab_dma_addr); - arm_smmu_test_make_s2_ste(&s2_ste, true); + fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_ATS); + arm_smmu_test_make_s2_ste(&s2_ste, ARM_SMMU_MASTER_TEST_ATS); arm_smmu_v3_test_ste_expect_hitless_transition(test, &s2_ste, &s1_ste, NUM_EXPECTED_SYNCS(3)); } @@ -375,9 +390,9 @@ static void arm_smmu_v3_write_ste_test_non_hitless(stru= ct kunit *test) * s1 dss field in the same update. */ arm_smmu_test_make_cdtable_ste(&ste, STRTAB_STE_1_S1DSS_SSID0, - fake_cdtab_dma_addr); + fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_ATS); arm_smmu_test_make_cdtable_ste(&ste_2, STRTAB_STE_1_S1DSS_BYPASS, - 0x4B4B4b4B4B); + 0x4B4B4b4B4B, ARM_SMMU_MASTER_TEST_ATS); arm_smmu_v3_test_ste_expect_non_hitless_transition( test, &ste, &ste_2, NUM_EXPECTED_SYNCS(3)); } @@ -503,6 +518,30 @@ static void arm_smmu_test_make_sva_release_cd(struct a= rm_smmu_cd *cd, arm_smmu_make_sva_cd(cd, &master, NULL, asid); } =20 +static void arm_smmu_v3_write_ste_test_s1_to_s2_stall(struct kunit *test) +{ + struct arm_smmu_ste s1_ste; + struct arm_smmu_ste s2_ste; + + arm_smmu_test_make_cdtable_ste(&s1_ste, STRTAB_STE_1_S1DSS_SSID0, + fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_STALL); + arm_smmu_test_make_s2_ste(&s2_ste, ARM_SMMU_MASTER_TEST_STALL); + arm_smmu_v3_test_ste_expect_hitless_transition(test, &s1_ste, &s2_ste, + NUM_EXPECTED_SYNCS(3)); +} + +static void arm_smmu_v3_write_ste_test_s2_to_s1_stall(struct kunit *test) +{ + struct arm_smmu_ste s1_ste; + struct arm_smmu_ste s2_ste; + + arm_smmu_test_make_cdtable_ste(&s1_ste, STRTAB_STE_1_S1DSS_SSID0, + fake_cdtab_dma_addr, ARM_SMMU_MASTER_TEST_STALL); + arm_smmu_test_make_s2_ste(&s2_ste, ARM_SMMU_MASTER_TEST_STALL); + arm_smmu_v3_test_ste_expect_hitless_transition(test, &s2_ste, &s1_ste, + NUM_EXPECTED_SYNCS(3)); +} + static void arm_smmu_v3_write_cd_test_sva_clear(struct kunit *test) { struct arm_smmu_cd cd =3D {}; @@ -547,6 +586,8 @@ static struct kunit_case arm_smmu_v3_test_cases[] =3D { KUNIT_CASE(arm_smmu_v3_write_ste_test_non_hitless), KUNIT_CASE(arm_smmu_v3_write_cd_test_s1_clear), KUNIT_CASE(arm_smmu_v3_write_cd_test_s1_change_asid), + KUNIT_CASE(arm_smmu_v3_write_ste_test_s1_to_s2_stall), + KUNIT_CASE(arm_smmu_v3_write_ste_test_s2_to_s1_stall), KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_clear), KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_release), {}, --=20 2.46.0.469.g59c65b2a67-goog