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[2001:b400:e338:dab5:746d:1a82:f21e:bb0a]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-715e575b7dfsm1866058b3a.190.2024.08.29.20.49.09 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 29 Aug 2024 20:49:10 -0700 (PDT) From: Tyrone Ting X-Google-Original-From: Tyrone Ting To: avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com, andi.shyti@kernel.org, andriy.shevchenko@linux.intel.com, wsa@kernel.org, rand.sec96@gmail.com, wsa+renesas@sang-engineering.com, warp5tw@gmail.com, tali.perry@nuvoton.com, Avi.Fishman@nuvoton.com, tomer.maimon@nuvoton.com, KWLIU@nuvoton.com, JJLIU0@nuvoton.com, kfting@nuvoton.com Cc: openbmc@lists.ozlabs.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/7] i2c: npcm: use i2c frequency table Date: Fri, 30 Aug 2024 11:46:39 +0800 Message-Id: <20240830034640.7049-7-kfting@nuvoton.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240830034640.7049-1-kfting@nuvoton.com> References: <20240830034640.7049-1-kfting@nuvoton.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Modify i2c frequency from table parameters for NPCM i2c modules. Supported frequencies are: 1. 100KHz 2. 400KHz 3. 1MHz Signed-off-by: Tyrone Ting --- drivers/i2c/busses/i2c-npcm7xx.c | 230 +++++++++++++++++++------------ 1 file changed, 144 insertions(+), 86 deletions(-) diff --git a/drivers/i2c/busses/i2c-npcm7xx.c b/drivers/i2c/busses/i2c-npcm= 7xx.c index 67d156ed29b9..cac4ea0b69b8 100644 --- a/drivers/i2c/busses/i2c-npcm7xx.c +++ b/drivers/i2c/busses/i2c-npcm7xx.c @@ -263,6 +263,121 @@ static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] =3D { #define I2C_FREQ_MIN_HZ 10000 #define I2C_FREQ_MAX_HZ I2C_MAX_FAST_MODE_PLUS_FREQ =20 +struct SMB_TIMING_T { + u32 core_clk; + u8 hldt; + u8 dbcnt; + u16 sclfrq; + u8 scllt; + u8 sclht; + bool fast_mode; +}; + +static struct SMB_TIMING_T SMB_TIMING_100KHZ[] =3D { + {.core_clk =3D 100000000, .hldt =3D 0x2A, .dbcnt =3D 0x4, .sclfrq =3D 0xF= B, .scllt =3D 0x0, + .sclht =3D 0x0, .fast_mode =3D false }, + {.core_clk =3D 62500000, .hldt =3D 0x2A, .dbcnt =3D 0x1, .sclfrq =3D 0x9= D, .scllt =3D 0x0, + .sclht =3D 0x0, .fast_mode =3D false }, + {.core_clk =3D 50000000, .hldt =3D 0x2A, .dbcnt =3D 0x1, .sclfrq =3D 0x7= E, .scllt =3D 0x0, + .sclht =3D 0x0, .fast_mode =3D false }, + {.core_clk =3D 48000000, .hldt =3D 0x2A, .dbcnt =3D 0x1, .sclfrq =3D 0x7= 9, .scllt =3D 0x0, + .sclht =3D 0x0, .fast_mode =3D false }, + {.core_clk =3D 40000000, .hldt =3D 0x2A, .dbcnt =3D 0x1, .sclfrq =3D 0x6= 5, .scllt =3D 0x0, + .sclht =3D 0x0, .fast_mode =3D false }, + {.core_clk =3D 30000000, .hldt =3D 0x2A, .dbcnt =3D 0x1, .sclfrq =3D 0x4= C, .scllt =3D 0x0, + .sclht =3D 0x0, .fast_mode =3D false }, + {.core_clk =3D 29000000, .hldt =3D 0x2A, .dbcnt =3D 0x1, .sclfrq =3D 0x4= 9, .scllt =3D 0x0, + .sclht =3D 0x0, .fast_mode =3D false }, + {.core_clk =3D 26000000, .hldt =3D 0x2A, .dbcnt =3D 0x1, .sclfrq =3D 0x4= 2, .scllt =3D 0x0, + .sclht =3D 0x0, .fast_mode =3D false }, + {.core_clk =3D 25000000, .hldt =3D 0x2A, .dbcnt =3D 0x1, .sclfrq =3D 0x3= F, .scllt =3D 0x0, + .sclht =3D 0x0, .fast_mode =3D false }, + {.core_clk =3D 24000000, .hldt =3D 0x2A, .dbcnt =3D 0x1, .sclfrq =3D 0x3= D, .scllt =3D 0x0, + .sclht =3D 0x0, .fast_mode =3D false }, + {.core_clk =3D 20000000, .hldt =3D 0x2A, .dbcnt =3D 0x1, .sclfrq =3D 0x3= 3, .scllt =3D 0x0, + .sclht =3D 0x0, .fast_mode =3D false }, + {.core_clk =3D 16180000, .hldt =3D 0x2A, .dbcnt =3D 0x1, .sclfrq =3D 0x2= 9, .scllt =3D 0x0, + .sclht =3D 0x0, .fast_mode =3D false }, + {.core_clk =3D 15000000, .hldt =3D 0x23, .dbcnt =3D 0x1, .sclfrq =3D 0x2= 6, .scllt =3D 0x0, + .sclht =3D 0x0, .fast_mode =3D false }, + {.core_clk =3D 13000000, .hldt =3D 0x1D, .dbcnt =3D 0x1, .sclfrq =3D 0x2= 1, .scllt =3D 0x0, + .sclht =3D 0x0, .fast_mode =3D false }, + {.core_clk =3D 12000000, .hldt =3D 0x1B, .dbcnt =3D 0x1, .sclfrq =3D 0x1= F, .scllt =3D 0x0, + .sclht =3D 0x0, .fast_mode =3D false }, + {.core_clk =3D 10000000, .hldt =3D 0x18, .dbcnt =3D 0x1, .sclfrq =3D 0x1= A, .scllt =3D 0x0, + .sclht =3D 0x0, .fast_mode =3D false }, + {.core_clk =3D 9000000, .hldt =3D 0x16, .dbcnt =3D 0x1, .sclfrq =3D 0x1= 7, .scllt =3D 0x0, + .sclht =3D 0x0, .fast_mode =3D false }, + {.core_clk =3D 8090000, .hldt =3D 0x14, .dbcnt =3D 0x1, .sclfrq =3D 0x1= 5, .scllt =3D 0x0, + .sclht =3D 0x0, .fast_mode =3D false }, + {.core_clk =3D 7500000, .hldt =3D 0x7, .dbcnt =3D 0x1, .sclfrq =3D 0x1= 3, .scllt =3D 0x0, + .sclht =3D 0x0, .fast_mode =3D false }, + {.core_clk =3D 6500000, .hldt =3D 0xE, .dbcnt =3D 0x1, .sclfrq =3D 0x1= 1, .scllt =3D 0x0, + .sclht =3D 0x0, .fast_mode =3D false }, + {.core_clk =3D 4000000, .hldt =3D 0x9, .dbcnt =3D 0x1, .sclfrq =3D 0xB= , .scllt =3D 0x0, + .sclht =3D 0x0, .fast_mode =3D false } +}; + +static struct SMB_TIMING_T SMB_TIMING_400KHZ[] =3D { + {.core_clk =3D 100000000, .hldt =3D 0x2A, .dbcnt =3D 0x3, .sclfrq =3D 0x0= , .scllt =3D 0x47, + .sclht =3D 0x35, .fast_mode =3D true }, + {.core_clk =3D 62500000, .hldt =3D 0x2A, .dbcnt =3D 0x2, .sclfrq =3D 0x0= , .scllt =3D 0x2C, + .sclht =3D 0x22, .fast_mode =3D true }, + {.core_clk =3D 50000000, .hldt =3D 0x21, .dbcnt =3D 0x1, .sclfrq =3D 0x0= , .scllt =3D 0x24, + .sclht =3D 0x1B, .fast_mode =3D true }, + {.core_clk =3D 48000000, .hldt =3D 0x1E, .dbcnt =3D 0x1, .sclfrq =3D 0x0= , .scllt =3D 0x24, + .sclht =3D 0x19, .fast_mode =3D true }, + {.core_clk =3D 40000000, .hldt =3D 0x1B, .dbcnt =3D 0x1, .sclfrq =3D 0x0= , .scllt =3D 0x1E, + .sclht =3D 0x14, .fast_mode =3D true }, + {.core_clk =3D 33000000, .hldt =3D 0x15, .dbcnt =3D 0x1, .sclfrq =3D 0x0= , .scllt =3D 0x19, + .sclht =3D 0x11, .fast_mode =3D true }, + {.core_clk =3D 30000000, .hldt =3D 0x15, .dbcnt =3D 0x1, .sclfrq =3D 0x0= , .scllt =3D 0x19, + .sclht =3D 0xD, .fast_mode =3D true }, + {.core_clk =3D 29000000, .hldt =3D 0x11, .dbcnt =3D 0x1, .sclfrq =3D 0x0= , .scllt =3D 0x15, + .sclht =3D 0x10, .fast_mode =3D true }, + {.core_clk =3D 26000000, .hldt =3D 0x10, .dbcnt =3D 0x1, .sclfrq =3D 0x0= , .scllt =3D 0x13, + .sclht =3D 0xE, .fast_mode =3D true }, + {.core_clk =3D 25000000, .hldt =3D 0xF, .dbcnt =3D 0x1, .sclfrq =3D 0x0= , .scllt =3D 0x13, + .sclht =3D 0xD, .fast_mode =3D true }, + {.core_clk =3D 24000000, .hldt =3D 0xD, .dbcnt =3D 0x1, .sclfrq =3D 0x0= , .scllt =3D 0x12, + .sclht =3D 0xD, .fast_mode =3D true }, + {.core_clk =3D 20000000, .hldt =3D 0xB, .dbcnt =3D 0x1, .sclfrq =3D 0x0= , .scllt =3D 0xF, + .sclht =3D 0xA, .fast_mode =3D true }, + {.core_clk =3D 16180000, .hldt =3D 0xA, .dbcnt =3D 0x1, .sclfrq =3D 0x0= , .scllt =3D 0xC, + .sclht =3D 0x9, .fast_mode =3D true }, + {.core_clk =3D 15000000, .hldt =3D 0x9, .dbcnt =3D 0x1, .sclfrq =3D 0x0= , .scllt =3D 0xB, + .sclht =3D 0x8, .fast_mode =3D true }, + {.core_clk =3D 13000000, .hldt =3D 0x7, .dbcnt =3D 0x1, .sclfrq =3D 0x0= , .scllt =3D 0xA, + .sclht =3D 0x7, .fast_mode =3D true }, + {.core_clk =3D 12000000, .hldt =3D 0x7, .dbcnt =3D 0x1, .sclfrq =3D 0x0= , .scllt =3D 0xA, + .sclht =3D 0x6, .fast_mode =3D true }, + {.core_clk =3D 10000000, .hldt =3D 0x6, .dbcnt =3D 0x1, .sclfrq =3D 0x0= , .scllt =3D 0x8, + .sclht =3D 0x5, .fast_mode =3D true }, +}; + +static struct SMB_TIMING_T SMB_TIMING_1000KHZ[] =3D { + {.core_clk =3D 100000000, .hldt =3D 0x15, .dbcnt =3D 0x4, .sclfrq =3D 0x0= , .scllt =3D 0x1C, + .sclht =3D 0x15, .fast_mode =3D true }, + {.core_clk =3D 62500000, .hldt =3D 0xF, .dbcnt =3D 0x3, .sclfrq =3D 0x0= , .scllt =3D 0x11, + .sclht =3D 0xE, .fast_mode =3D true }, + {.core_clk =3D 50000000, .hldt =3D 0xA, .dbcnt =3D 0x2, .sclfrq =3D 0x0= , .scllt =3D 0xE, + .sclht =3D 0xB, .fast_mode =3D true }, + {.core_clk =3D 48000000, .hldt =3D 0x9, .dbcnt =3D 0x2, .sclfrq =3D 0x0= , .scllt =3D 0xD, + .sclht =3D 0xB, .fast_mode =3D true }, + {.core_clk =3D 41000000, .hldt =3D 0x9, .dbcnt =3D 0x2, .sclfrq =3D 0x0= , .scllt =3D 0xC, + .sclht =3D 0x9, .fast_mode =3D true }, + {.core_clk =3D 40000000, .hldt =3D 0x8, .dbcnt =3D 0x2, .sclfrq =3D 0x0= , .scllt =3D 0xB, + .sclht =3D 0x9, .fast_mode =3D true }, + {.core_clk =3D 33000000, .hldt =3D 0x7, .dbcnt =3D 0x1, .sclfrq =3D 0x0= , .scllt =3D 0xA, + .sclht =3D 0x7, .fast_mode =3D true }, + {.core_clk =3D 25000000, .hldt =3D 0x4, .dbcnt =3D 0x1, .sclfrq =3D 0x0= , .scllt =3D 0x7, + .sclht =3D 0x6, .fast_mode =3D true }, + {.core_clk =3D 24000000, .hldt =3D 0x7, .dbcnt =3D 0x1, .sclfrq =3D 0x0= , .scllt =3D 0x8, + .sclht =3D 0x5, .fast_mode =3D true }, + {.core_clk =3D 20000000, .hldt =3D 0x4, .dbcnt =3D 0x1, .sclfrq =3D 0x0= , .scllt =3D 0x6, + .sclht =3D 0x4, .fast_mode =3D true }, +}; + struct npcm_i2c_data { u8 fifo_size; u32 segctl_init_val; @@ -1805,102 +1920,45 @@ static void npcm_i2c_recovery_init(struct i2c_adap= ter *_adap) */ static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz) { - u32 k1 =3D 0; - u32 k2 =3D 0; - u8 dbnct =3D 0; - u32 sclfrq =3D 0; - u8 hldt =3D 7; + struct SMB_TIMING_T *smb_timing; + u8 scl_table_cnt =3D 0, table_size =3D 0; u8 fast_mode =3D 0; - u32 src_clk_khz; - u32 bus_freq_khz; =20 - src_clk_khz =3D bus->apb_clk / 1000; - bus_freq_khz =3D bus_freq_hz / 1000; bus->bus_freq =3D bus_freq_hz; =20 - /* 100KHz and below: */ - if (bus_freq_hz <=3D I2C_MAX_STANDARD_MODE_FREQ) { - sclfrq =3D src_clk_khz / (bus_freq_khz * 4); - - if (sclfrq < SCLFRQ_MIN || sclfrq > SCLFRQ_MAX) - return -EDOM; - - if (src_clk_khz >=3D 40000) - hldt =3D 17; - else if (src_clk_khz >=3D 12500) - hldt =3D 15; - else - hldt =3D 7; - } - - /* 400KHz: */ - else if (bus_freq_hz <=3D I2C_MAX_FAST_MODE_FREQ) { - sclfrq =3D 0; + switch (bus_freq_hz) { + case I2C_MAX_STANDARD_MODE_FREQ: + smb_timing =3D SMB_TIMING_100KHZ; + table_size =3D ARRAY_SIZE(SMB_TIMING_100KHZ); + break; + case I2C_MAX_FAST_MODE_FREQ: + smb_timing =3D SMB_TIMING_400KHZ; + table_size =3D ARRAY_SIZE(SMB_TIMING_400KHZ); fast_mode =3D I2CCTL3_400K_MODE; - - if (src_clk_khz < 7500) - /* 400KHZ cannot be supported for core clock < 7.5MHz */ - return -EDOM; - - else if (src_clk_khz >=3D 50000) { - k1 =3D 80; - k2 =3D 48; - hldt =3D 12; - dbnct =3D 7; - } - - /* Master or Slave with frequency > 25MHz */ - else if (src_clk_khz > 25000) { - hldt =3D clk_coef(src_clk_khz, 300) + 7; - k1 =3D clk_coef(src_clk_khz, 1600); - k2 =3D clk_coef(src_clk_khz, 900); - } - } - - /* 1MHz: */ - else if (bus_freq_hz <=3D I2C_MAX_FAST_MODE_PLUS_FREQ) { - sclfrq =3D 0; + break; + case I2C_MAX_FAST_MODE_PLUS_FREQ: + smb_timing =3D SMB_TIMING_1000KHZ; + table_size =3D ARRAY_SIZE(SMB_TIMING_1000KHZ); fast_mode =3D I2CCTL3_400K_MODE; - - /* 1MHZ cannot be supported for core clock < 24 MHz */ - if (src_clk_khz < 24000) - return -EDOM; - - k1 =3D clk_coef(src_clk_khz, 620); - k2 =3D clk_coef(src_clk_khz, 380); - - /* Core clk > 40 MHz */ - if (src_clk_khz > 40000) { - /* - * Set HLDT: - * SDA hold time: (HLDT-7) * T(CLK) >=3D 120 - * HLDT =3D 120/T(CLK) + 7 =3D 120 * FREQ(CLK) + 7 - */ - hldt =3D clk_coef(src_clk_khz, 120) + 7; - } else { - hldt =3D 7; - dbnct =3D 2; - } + break; + default: + return -EINVAL; } =20 - /* Frequency larger than 1 MHz is not supported */ - else - return -EINVAL; + for (scl_table_cnt =3D 0 ; scl_table_cnt < table_size ; scl_table_cnt++) + if (bus->apb_clk >=3D smb_timing[scl_table_cnt].core_clk) + break; =20 - if (bus_freq_hz >=3D I2C_MAX_FAST_MODE_FREQ) { - k1 =3D round_up(k1, 2); - k2 =3D round_up(k2 + 1, 2); - if (k1 < SCLFRQ_MIN || k1 > SCLFRQ_MAX || - k2 < SCLFRQ_MIN || k2 > SCLFRQ_MAX) - return -EDOM; - } + if (scl_table_cnt =3D=3D table_size) + return -EINVAL; =20 /* write sclfrq value. bits [6:0] are in I2CCTL2 reg */ - iowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, sclfrq & 0x7F), + iowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, smb_timing[scl_table_cnt].sclfrq &= 0x7F), bus->reg + NPCM_I2CCTL2); =20 /* bits [8:7] are in I2CCTL3 reg */ - iowrite8(fast_mode | FIELD_PREP(I2CCTL3_SCLFRQ8_7, (sclfrq >> 7) & 0x3), + iowrite8(fast_mode | FIELD_PREP(I2CCTL3_SCLFRQ8_7, (smb_timing[scl_table_= cnt].sclfrq >> 7) + & 0x3), bus->reg + NPCM_I2CCTL3); =20 /* Select Bank 0 to access NPCM_I2CCTL4/NPCM_I2CCTL5 */ @@ -1912,13 +1970,13 @@ static int npcm_i2c_init_clk(struct npcm_i2c *bus, = u32 bus_freq_hz) * k1 =3D 2 * SCLLT7-0 -> Low Time =3D k1 / 2 * k2 =3D 2 * SCLLT7-0 -> High Time =3D k2 / 2 */ - iowrite8(k1 / 2, bus->reg + NPCM_I2CSCLLT); - iowrite8(k2 / 2, bus->reg + NPCM_I2CSCLHT); + iowrite8(smb_timing[scl_table_cnt].scllt, bus->reg + NPCM_I2CSCLLT); + iowrite8(smb_timing[scl_table_cnt].sclht, bus->reg + NPCM_I2CSCLHT); =20 - iowrite8(dbnct, bus->reg + NPCM_I2CCTL5); + iowrite8(smb_timing[scl_table_cnt].dbcnt, bus->reg + NPCM_I2CCTL5); } =20 - iowrite8(hldt, bus->reg + NPCM_I2CCTL4); + iowrite8(smb_timing[scl_table_cnt].hldt, bus->reg + NPCM_I2CCTL4); =20 /* Return to Bank 1, and stay there by default: */ npcm_i2c_select_bank(bus, I2C_BANK_1); --=20 2.34.1