From nobody Thu Dec 18 23:40:16 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F7211BA88F; Thu, 29 Aug 2024 20:26:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724963171; cv=none; b=fqypdcj1moHN7ly50faPiM2cvwNGPLHXQQQCe4CfexxODrY1Z2gj6mqIkXM++q1dZfatkiFcaufsUDIREKFTtx1dlj2/sNpW+AA54o7BodZWF5EARi3JbfHf6/ftxgiWcLowNjm0z4wmWkzHSrO1dgeaV4fnLX+tiayzrTWIQpA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724963171; c=relaxed/simple; bh=RlsFXO6KatDsM7/49cx/GSZQ9BgWcaXezSg0o3At/h0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lJ2dhMW6CK0f3+z7WuN+OLXIJ4GHZG+eWrbfhMKIceHeTE7k6NKICuJTUqTAuPRSYlRJ+hChpBp6JxJIABZkQXd4GtFLeo1hF3O0EZ8w0LCEUoa9re4x6FphZM6N8T3c2ttcsWcEZ7qi2vAYvk4VZX7gLb05oxcvSvembdNIsfc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=i3l7IouF; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="i3l7IouF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1724963167; bh=RlsFXO6KatDsM7/49cx/GSZQ9BgWcaXezSg0o3At/h0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=i3l7IouF+s1UpEa2L7+qaXO296mVBKobWHSB2ihmSLDlW2UVpNIOkXxBEZWyvPenV itpTBBTmLqX+ABwHw0ap3KDWbkzx/U7dpuP1rYv5VU3Lv+B/jqI+gaR05zEeNmtloC ZKvXZDNlnxsPxfKudSGgrj0nSNYx3f+4IR+BA19iw3nfqDUlUYxSNkFBI6gsRmJO93 FJXy6oloTGPXSPJpDwKVxsLUiwuSxUWx/ZnEKrSP1upHgxaa08JZ8KX4+f21iVzmW9 UiZZ8Z1JG3b9PdE+LgouZm6w8XpNhr4HRUAMewg3nvmFEqiEnxpI9vW0FRquhsEFGQ kps7fiY8614Gg== Received: from trenzalore.hitronhub.home (unknown [23.233.251.139]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: detlev) by bali.collaboradmins.com (Postfix) with ESMTPSA id C2A0317E0FF5; Thu, 29 Aug 2024 22:26:05 +0200 (CEST) From: Detlev Casanova To: linux-kernel@vger.kernel.org Cc: Ulf Hansson , Heiko Stuebner , Detlev Casanova , Geert Uytterhoeven , Linus Walleij , Finley Xiao , Rob Herring , linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, kernel@collabora.com Subject: [PATCH 1/2] pmdomain: rockchip: Add gating support Date: Thu, 29 Aug 2024 16:20:47 -0400 Message-ID: <20240829202732.75961-2-detlev.casanova@collabora.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240829202732.75961-1-detlev.casanova@collabora.com> References: <20240829202732.75961-1-detlev.casanova@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some rockchip SoC need to ungate power domains before their power status can be changed. Each power domain has a gate mask that is set to 1 to ungate it when manipulating power status, then set back to 0 to gate it again. Signed-off-by: Detlev Casanova --- drivers/pmdomain/rockchip/pm-domains.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rock= chip/pm-domains.c index 64b4d7120d832..5b601efadd2e0 100644 --- a/drivers/pmdomain/rockchip/pm-domains.c +++ b/drivers/pmdomain/rockchip/pm-domains.c @@ -46,6 +46,7 @@ struct rockchip_domain_info { bool active_wakeup; int pwr_w_mask; int req_w_mask; + int clk_ungate_mask; int mem_status_mask; int repair_status_mask; u32 pwr_offset; @@ -63,6 +64,7 @@ struct rockchip_pmu_info { u32 chain_status_offset; u32 mem_status_offset; u32 repair_status_offset; + u32 clk_ungate_offset; =20 u32 core_pwrcnt_offset; u32 gpu_pwrcnt_offset; @@ -303,6 +305,26 @@ static unsigned int rockchip_pmu_read_ack(struct rockc= hip_pmu *pmu) return val; } =20 +static int rockchip_pmu_ungate_clk(struct rockchip_pm_domain *pd, bool ung= ate) +{ + const struct rockchip_domain_info *pd_info =3D pd->info; + struct rockchip_pmu *pmu =3D pd->pmu; + unsigned int val; + int clk_ungate_w_mask =3D pd_info->clk_ungate_mask << 16; + + if (!pd_info->clk_ungate_mask) + return 0; + + if (!pmu->info->clk_ungate_offset) + return 0; + + val =3D ungate ? (pd_info->clk_ungate_mask | clk_ungate_w_mask) : + clk_ungate_w_mask; + regmap_write(pmu->regmap, pmu->info->clk_ungate_offset, val); + + return 0; +} + static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd, bool idle) { @@ -543,6 +565,8 @@ static int rockchip_pd_power(struct rockchip_pm_domain = *pd, bool power_on) return ret; } =20 + rockchip_pmu_ungate_clk(pd, true); + if (!power_on) { rockchip_pmu_save_qos(pd); =20 @@ -559,6 +583,7 @@ static int rockchip_pd_power(struct rockchip_pm_domain = *pd, bool power_on) rockchip_pmu_restore_qos(pd); } =20 + rockchip_pmu_ungate_clk(pd, false); clk_bulk_disable(pd->num_clks, pd->clks); } =20 --=20 2.46.0 From nobody Thu Dec 18 23:40:16 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E78D1BB68F; Thu, 29 Aug 2024 20:26:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724963173; cv=none; b=Ah+6gldZgIG34zn+fnP/u/8Y/8SQw0qMkdIyIrCVMQdc8lmTouuqN1vuwqJDc7QljqZFmrx30xCR6u2Rop4yrw+3MQhii2kqsxaJW5Ysb6iQKk1vib9/FmwyT6Xpu5tgmCFtXD1hguaN6IPrdIbMOSnzGCzodK5TRG7cGev/OQI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724963173; c=relaxed/simple; bh=sQE61qiplUVQwvO+oRXKg1alqgEO6GT2ZbgV3dVP5dM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TSllaQQxJD3Zlf+wqLx6Jtc+ECsDa/CWCHQ3kZI8yKQusXMtnIrg5X9cQ1ztKqB8DZpi0wpQHbT/bPYW61VjC0GSdkRydU7MeZqx6F7TSNuDlhuatsbFP6oJphTjKXGp47EWCkAYDeYyIHJwebcL8ul8H0qSoGuBzuoxQ+SxvBc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=m+3wxnG5; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="m+3wxnG5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1724963169; bh=sQE61qiplUVQwvO+oRXKg1alqgEO6GT2ZbgV3dVP5dM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m+3wxnG5exmXtAEqCUCBPpytsEHDSwDuLl+NSwV04IOKUw+82TeeTXQH9O99M+Zw0 zV6FGaU9/3PGvETIS4hI4EK+USEBFdd3DLk4V9KmcCs1E1AOtffokk70jGv2/QtH56 PBbWKEBMbTHfP+JYNUP38SqVLdEqn0hQRBc/ezSLexQ+C2gGJNH522LoBx3On9z3wL ZuQgHds0Nwr1wzUJZnNcbmqTwBkWTzUKJUCiJUdezEkrne0ZOo36eA9HNl15iD4Z9a bip6hxCy36fcILQ6zrNb5dsA3Pw56beEOa9ocJIMmUruGSiI99vmZvloaLPgpx5A1+ K4/aH/0elPEPA== Received: from trenzalore.hitronhub.home (unknown [23.233.251.139]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: detlev) by bali.collaboradmins.com (Postfix) with ESMTPSA id 94AEB17E1034; Thu, 29 Aug 2024 22:26:07 +0200 (CEST) From: Detlev Casanova To: linux-kernel@vger.kernel.org Cc: Ulf Hansson , Heiko Stuebner , Detlev Casanova , Geert Uytterhoeven , Linus Walleij , Finley Xiao , Rob Herring , linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, kernel@collabora.com Subject: [PATCH 2/2] pmdomain: rockchip: Add gating masks for rk3576 Date: Thu, 29 Aug 2024 16:20:48 -0400 Message-ID: <20240829202732.75961-3-detlev.casanova@collabora.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240829202732.75961-1-detlev.casanova@collabora.com> References: <20240829202732.75961-1-detlev.casanova@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RK3576 SoC needs to ungate the power domains before their status can be modified. The values have been taken from the rockchip downstream driver. Signed-off-by: Detlev Casanova --- drivers/pmdomain/rockchip/pm-domains.c | 62 +++++++++++++++++--------- 1 file changed, 41 insertions(+), 21 deletions(-) diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rock= chip/pm-domains.c index 5b601efadd2e0..ab2d34f21718b 100644 --- a/drivers/pmdomain/rockchip/pm-domains.c +++ b/drivers/pmdomain/rockchip/pm-domains.c @@ -147,6 +147,25 @@ struct rockchip_pmu { .active_wakeup =3D wakeup, \ } =20 +#define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status, r= _status, r_offset, req, idle, ack, g_mask, wakeup) \ +{ \ + .name =3D _name, \ + .pwr_offset =3D p_offset, \ + .pwr_w_mask =3D (pwr) << 16, \ + .pwr_mask =3D (pwr), \ + .status_mask =3D (status), \ + .mem_offset =3D m_offset, \ + .mem_status_mask =3D (m_status), \ + .repair_status_mask =3D (r_status), \ + .req_offset =3D r_offset, \ + .req_w_mask =3D (req) << 16, \ + .req_mask =3D (req), \ + .idle_mask =3D (idle), \ + .clk_ungate_mask =3D (g_mask), \ + .ack_mask =3D (ack), \ + .active_wakeup =3D wakeup, \ +} + #define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \ { \ .name =3D _name, \ @@ -178,8 +197,8 @@ struct rockchip_pmu { #define DOMAIN_RK3568(name, pwr, req, wakeup) \ DOMAIN_M(name, pwr, pwr, req, req, req, wakeup) =20 -#define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req= , idle, wakeup) \ - DOMAIN_M_O_R(name, p_offset, pwr, status, 0, r_status, r_status, r_offset= , req, idle, idle, wakeup) +#define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req= , idle, g_mask, wakeup) \ + DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offs= et, req, idle, idle, g_mask, wakeup) =20 /* * Dynamic Memory Controller may need to coordinate with us -- see @@ -1136,25 +1155,25 @@ static const struct rockchip_domain_info rk3568_pm_= domains[] =3D { }; =20 static const struct rockchip_domain_info rk3576_pm_domains[] =3D { - [RK3576_PD_NPU] =3D DOMAIN_RK3576("npu", 0x0, BIT(0), BIT(0), 0, = 0x0, 0, 0, false), - [RK3576_PD_NVM] =3D DOMAIN_RK3576("nvm", 0x0, BIT(6), 0, BIT(6)= , 0x4, BIT(2), BIT(18), false), - [RK3576_PD_SDGMAC] =3D DOMAIN_RK3576("sdgmac", 0x0, BIT(7), 0, BIT(= 7), 0x4, BIT(1), BIT(17), false), - [RK3576_PD_AUDIO] =3D DOMAIN_RK3576("audio", 0x0, BIT(8), 0, BIT(8= ), 0x4, BIT(0), BIT(16), false), - [RK3576_PD_PHP] =3D DOMAIN_RK3576("php", 0x0, BIT(9), 0, BIT(9)= , 0x0, BIT(15), BIT(15), false), - [RK3576_PD_SUBPHP] =3D DOMAIN_RK3576("subphp", 0x0, BIT(10), 0, BIT(= 10), 0x0, 0, 0, false), - [RK3576_PD_VOP] =3D DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(11= ), 0x0, 0x6000, 0x6000, false), - [RK3576_PD_VO1] =3D DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(14= ), 0x0, BIT(12), BIT(12), false), - [RK3576_PD_VO0] =3D DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(15= ), 0x0, BIT(11), BIT(11), false), - [RK3576_PD_USB] =3D DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(16= ), 0x0, BIT(10), BIT(10), true), - [RK3576_PD_VI] =3D DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(17)= , 0x0, BIT(9), BIT(9), false), - [RK3576_PD_VEPU0] =3D DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT(1= 8), 0x0, BIT(7), BIT(7), false), - [RK3576_PD_VEPU1] =3D DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT(1= 9), 0x0, BIT(8), BIT(8), false), - [RK3576_PD_VDEC] =3D DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(20= ), 0x0, BIT(6), BIT(6), false), - [RK3576_PD_VPU] =3D DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(21= ), 0x0, BIT(5), BIT(5), false), - [RK3576_PD_NPUTOP] =3D DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BIT(= 22), 0x0, 0x18, 0x18, false), - [RK3576_PD_NPU0] =3D DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(23= ), 0x0, BIT(1), BIT(1), false), - [RK3576_PD_NPU1] =3D DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(24= ), 0x0, BIT(2), BIT(2), false), - [RK3576_PD_GPU] =3D DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(25= ), 0x0, BIT(0), BIT(0), false), + [RK3576_PD_NPU] =3D DOMAIN_RK3576("npu", 0x0, BIT(0), BIT(0), 0, = 0x0, 0, 0, 0, false), + [RK3576_PD_NVM] =3D DOMAIN_RK3576("nvm", 0x0, BIT(6), 0, BIT(6)= , 0x4, BIT(2), BIT(18), BIT(2), false), + [RK3576_PD_SDGMAC] =3D DOMAIN_RK3576("sdgmac", 0x0, BIT(7), 0, BIT(= 7), 0x4, BIT(1), BIT(17), 0x6, false), + [RK3576_PD_AUDIO] =3D DOMAIN_RK3576("audio", 0x0, BIT(8), 0, BIT(8= ), 0x4, BIT(0), BIT(16), BIT(0), false), + [RK3576_PD_PHP] =3D DOMAIN_RK3576("php", 0x0, BIT(9), 0, BIT(9)= , 0x0, BIT(15), BIT(15), BIT(15), false), + [RK3576_PD_SUBPHP] =3D DOMAIN_RK3576("subphp", 0x0, BIT(10), 0, BIT(= 10), 0x0, 0, 0, 0, false), + [RK3576_PD_VOP] =3D DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(11= ), 0x0, 0x6000, 0x6000, 0x6000, false), + [RK3576_PD_VO1] =3D DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(14= ), 0x0, BIT(12), BIT(12), 0x7000, false), + [RK3576_PD_VO0] =3D DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(15= ), 0x0, BIT(11), BIT(11), 0x6800, false), + [RK3576_PD_USB] =3D DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(16= ), 0x0, BIT(10), BIT(10), 0x6400, true), + [RK3576_PD_VI] =3D DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(17)= , 0x0, BIT(9), BIT(9), BIT(9), false), + [RK3576_PD_VEPU0] =3D DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT(1= 8), 0x0, BIT(7), BIT(7), 0x280, false), + [RK3576_PD_VEPU1] =3D DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT(1= 9), 0x0, BIT(8), BIT(8), BIT(8), false), + [RK3576_PD_VDEC] =3D DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(20= ), 0x0, BIT(6), BIT(6), BIT(6), false), + [RK3576_PD_VPU] =3D DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(21= ), 0x0, BIT(5), BIT(5), BIT(5), false), + [RK3576_PD_NPUTOP] =3D DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BIT(= 22), 0x0, 0x18, 0x18, 0x18, false), + [RK3576_PD_NPU0] =3D DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(23= ), 0x0, BIT(1), BIT(1), 0x1a, false), + [RK3576_PD_NPU1] =3D DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(24= ), 0x0, BIT(2), BIT(2), 0x1c, false), + [RK3576_PD_GPU] =3D DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(25= ), 0x0, BIT(0), BIT(0), BIT(0), false), }; =20 static const struct rockchip_domain_info rk3588_pm_domains[] =3D { @@ -1345,6 +1364,7 @@ static const struct rockchip_pmu_info rk3576_pmu =3D { .idle_offset =3D 0x128, .ack_offset =3D 0x120, .repair_status_offset =3D 0x570, + .clk_ungate_offset =3D 0x140, =20 .num_domains =3D ARRAY_SIZE(rk3576_pm_domains), .domain_info =3D rk3576_pm_domains, --=20 2.46.0