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There are three feature levels: - A7-A10: No fast IPI - A11: fast IPI, global only - M1: fast IPI with local and global support Each feature level is an extension of the previous. For example, M1 will also work with the A7 feature level. Signed-off-by: Nick Chan --- .../bindings/interrupt-controller/apple,aic.yaml | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,a= ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.= yaml index 698588e9aa86..28e09b933087 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml @@ -36,9 +36,18 @@ allOf: =20 properties: compatible: - items: - - const: apple,t8103-aic - - const: apple,aic + oneOf: + - const: apple,s5l8960x-aic + - items: + - enum: + - apple,s8000-aic + - apple,t7000-aic + - apple,t8010-aic + - const: apple,s5l8960x-aic + - items: + - const: apple,t8103-aic + - const: apple,t8015-aic + - const: apple,aic =20 interrupt-controller: true =20 --=20 2.46.0 From nobody Thu Dec 18 23:47:09 2025 Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CC1918EFED; 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Thu, 29 Aug 2024 02:27:20 -0700 (PDT) Received: from localhost.localdomain ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-20515552b6dsm7469245ad.249.2024.08.29.02.27.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Aug 2024 02:27:20 -0700 (PDT) From: Nick Chan To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, Nick Chan , Konrad Dybcio Subject: [PATCH 2/3] irqchip/apple-aic: Only access IPI sysregs when use_fast_ipi is true Date: Thu, 29 Aug 2024 17:03:12 +0800 Message-ID: <20240829092610.89731-3-towinchenmi@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240829092610.89731-1-towinchenmi@gmail.com> References: <20240829092610.89731-1-towinchenmi@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Starting from the A11 (T8015) SoC, Apple introuced system registers for fast IPI and UNCORE PMC control. These sysregs do not exist on earlier A7-A10 SoCs and trying to access them results in an instant crash. Restrict sysreg access within the AIC driver to configurations where use_fast_ipi is true to allow AIC to function properly on A7-A10 SoCs. While at it, remove the IPI-always-ack path on aic_handle_fiq. If we are able to reach there, we are on an IPI-capable system and should be using one of the IPI-capable compatibles, anyway. Signed-off-by: Konrad Dybcio Signed-off-by: Nick Chan --- drivers/irqchip/irq-apple-aic.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/irqchip/irq-apple-aic.c b/drivers/irqchip/irq-apple-ai= c.c index 5c534d9fd2b0..626aaeafa96c 100644 --- a/drivers/irqchip/irq-apple-aic.c +++ b/drivers/irqchip/irq-apple-aic.c @@ -234,6 +234,7 @@ enum fiq_hwirq { AIC_NR_FIQ }; =20 +/* True if UNCORE/UNCORE2 and Sn_... IPI registers are present and used (A= 11+) */ static DEFINE_STATIC_KEY_TRUE(use_fast_ipi); =20 struct aic_info { @@ -532,13 +533,9 @@ static void __exception_irq_entry aic_handle_fiq(struc= t pt_regs *regs) * we check for everything here, even things we don't support yet. */ =20 - if (read_sysreg_s(SYS_IMP_APL_IPI_SR_EL1) & IPI_SR_PENDING) { - if (static_branch_likely(&use_fast_ipi)) { - aic_handle_ipi(regs); - } else { - pr_err_ratelimited("Fast IPI fired. Acking.\n"); - write_sysreg_s(IPI_SR_PENDING, SYS_IMP_APL_IPI_SR_EL1); - } + if (static_branch_likely(&use_fast_ipi) && + (read_sysreg_s(SYS_IMP_APL_IPI_SR_EL1) & IPI_SR_PENDING)) { + aic_handle_ipi(regs); } =20 if (TIMER_FIRING(read_sysreg(cntp_ctl_el0))) @@ -574,8 +571,9 @@ static void __exception_irq_entry aic_handle_fiq(struct= pt_regs *regs) AIC_FIQ_HWIRQ(irq)); } =20 - if (FIELD_GET(UPMCR0_IMODE, read_sysreg_s(SYS_IMP_APL_UPMCR0_EL1)) =3D=3D= UPMCR0_IMODE_FIQ && - (read_sysreg_s(SYS_IMP_APL_UPMSR_EL1) & UPMSR_IACT)) { + if (static_branch_likely(&use_fast_ipi) && + (FIELD_GET(UPMCR0_IMODE, read_sysreg_s(SYS_IMP_APL_UPMCR0_EL1)) =3D= =3D UPMCR0_IMODE_FIQ) && + (read_sysreg_s(SYS_IMP_APL_UPMSR_EL1) & UPMSR_IACT)) { /* Same story with uncore PMCs */ pr_err_ratelimited("Uncore PMC FIQ fired. Masking.\n"); sysreg_clear_set_s(SYS_IMP_APL_UPMCR0_EL1, UPMCR0_IMODE, @@ -811,7 +809,8 @@ static int aic_init_cpu(unsigned int cpu) /* Mask all hard-wired per-CPU IRQ/FIQ sources */ =20 /* Pending Fast IPI FIQs */ - write_sysreg_s(IPI_SR_PENDING, SYS_IMP_APL_IPI_SR_EL1); + if (static_branch_likely(&use_fast_ipi)) + write_sysreg_s(IPI_SR_PENDING, SYS_IMP_APL_IPI_SR_EL1); =20 /* Timer FIQs */ sysreg_clear_set(cntp_ctl_el0, 0, ARCH_TIMER_CTRL_IT_MASK); @@ -832,8 +831,9 @@ static int aic_init_cpu(unsigned int cpu) FIELD_PREP(PMCR0_IMODE, PMCR0_IMODE_OFF)); =20 /* Uncore PMC FIQ */ - sysreg_clear_set_s(SYS_IMP_APL_UPMCR0_EL1, UPMCR0_IMODE, - FIELD_PREP(UPMCR0_IMODE, UPMCR0_IMODE_OFF)); + if (static_branch_likely(&use_fast_ipi)) + sysreg_clear_set_s(SYS_IMP_APL_UPMCR0_EL1, UPMCR0_IMODE, + FIELD_PREP(UPMCR0_IMODE, UPMCR0_IMODE_OFF)); =20 /* Commit all of the above */ isb(); --=20 2.46.0 From nobody Thu Dec 18 23:47:09 2025 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3E5218E371; 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Thu, 29 Aug 2024 02:27:24 -0700 (PDT) Received: from localhost.localdomain ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-20515552b6dsm7469245ad.249.2024.08.29.02.27.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Aug 2024 02:27:23 -0700 (PDT) From: Nick Chan To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, Nick Chan Subject: [PATCH 3/3] irqchip/apple-aic: Add a new "Global fast IPIs only" feature level Date: Thu, 29 Aug 2024 17:03:13 +0800 Message-ID: <20240829092610.89731-4-towinchenmi@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240829092610.89731-1-towinchenmi@gmail.com> References: <20240829092610.89731-1-towinchenmi@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Starting with the A11 (T8015) SoC, Apple began using arm64 sysregs for fast IPIs. However, on A11, there is no such things as "Local" fast IPIs, as the SYS_IMP_APL_IPI_RR_LOCAL_EL1 register does not seem to exist. Add a new feature level, used by the compatible "apple,t8015-aic", controlled by a static branch key named use_local_fast_ipi. When use_fast_ipi is true and use_local_fast_ipi is false, fast IPIs are used but all IPIs goes through the register SYS_IMP_APL_IPI_RR_GLOBAL_EL1, as "global" IPIs. Signed-off-by: Nick Chan --- drivers/irqchip/irq-apple-aic.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-apple-aic.c b/drivers/irqchip/irq-apple-ai= c.c index 626aaeafa96c..9248ecff42a3 100644 --- a/drivers/irqchip/irq-apple-aic.c +++ b/drivers/irqchip/irq-apple-aic.c @@ -236,6 +236,8 @@ enum fiq_hwirq { =20 /* True if UNCORE/UNCORE2 and Sn_... IPI registers are present and used (A= 11+) */ static DEFINE_STATIC_KEY_TRUE(use_fast_ipi); +/* True if SYS_IMP_APL_IPI_RR_LOCAL_EL1 exists (M1+) */ +static DEFINE_STATIC_KEY_TRUE(use_local_fast_ipi); =20 struct aic_info { int version; @@ -253,6 +255,7 @@ struct aic_info { =20 /* Features */ bool fast_ipi; + bool local_fast_ipi; }; =20 static const struct aic_info aic1_info __initconst =3D { @@ -271,6 +274,16 @@ static const struct aic_info aic1_fipi_info __initcons= t =3D { .fast_ipi =3D true, }; =20 +static const struct aic_info aic1_local_fipi_info __initconst =3D { + .version =3D 1, + + .event =3D AIC_EVENT, + .target_cpu =3D AIC_TARGET_CPU, + + .fast_ipi =3D true, + .local_fast_ipi =3D true, +}; + static const struct aic_info aic2_info __initconst =3D { .version =3D 2, =20 @@ -282,6 +295,10 @@ static const struct aic_info aic2_info __initconst =3D= { static const struct of_device_id aic_info_match[] =3D { { .compatible =3D "apple,t8103-aic", + .data =3D &aic1_local_fipi_info, + }, + { + .compatible =3D "apple,t8015-aic", .data =3D &aic1_fipi_info, }, { @@ -748,7 +765,8 @@ static void aic_ipi_send_fast(int cpu) u64 cluster =3D MPIDR_CLUSTER(mpidr); u64 idx =3D MPIDR_CPU(mpidr); =20 - if (MPIDR_CLUSTER(my_mpidr) =3D=3D cluster) + if (static_branch_likely(&use_local_fast_ipi) && + MPIDR_CLUSTER(my_mpidr) =3D=3D cluster) write_sysreg_s(FIELD_PREP(IPI_RR_CPU, idx), SYS_IMP_APL_IPI_RR_LOCAL_EL1); else @@ -992,6 +1010,11 @@ static int __init aic_of_ic_init(struct device_node *= node, struct device_node *p else static_branch_disable(&use_fast_ipi); =20 + if (irqc->info.local_fast_ipi) + static_branch_enable(&use_local_fast_ipi); + else + static_branch_disable(&use_local_fast_ipi); + irqc->info.die_stride =3D off - start_off; =20 irqc->hw_domain =3D irq_domain_create_tree(of_node_to_fwnode(node), --=20 2.46.0