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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Aug 2024 09:17:50.0249 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 297e6cd2-19a8-4784-8313-08dcc80b7467 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DF.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7096 Content-Type: text/plain; charset="utf-8" The current driver code lacks the necessary plumbing for ACPI IDs, preventing the mipi-i3c-hci driver from being loaded on x86 platforms that advertise I3C ACPI support. Add the AMDI5017 ACPI ID to the list of supported IDs. Reviewed-by: Andy Shevchenko Signed-off-by: Shyam Sundar S K Reviewed-by: Jarkko Nikula --- drivers/i3c/master/mipi-i3c-hci/core.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index 4e7d6a43ee9b..07de1cecfa30 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -834,12 +834,19 @@ static const __maybe_unused struct of_device_id i3c_h= ci_of_match[] =3D { }; MODULE_DEVICE_TABLE(of, i3c_hci_of_match); =20 +static const struct acpi_device_id i3c_hci_acpi_match[] =3D { + { "AMDI5017" }, + {} +}; +MODULE_DEVICE_TABLE(acpi, i3c_hci_acpi_match); + static struct platform_driver i3c_hci_driver =3D { .probe =3D i3c_hci_probe, .remove_new =3D i3c_hci_remove, .driver =3D { .name =3D "mipi-i3c-hci", .of_match_table =3D of_match_ptr(i3c_hci_of_match), + .acpi_match_table =3D i3c_hci_acpi_match, }, }; module_platform_driver(i3c_hci_driver); --=20 2.25.1 From nobody Thu Sep 19 01:04:54 2024 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2046.outbound.protection.outlook.com [40.107.93.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1EB0C18DF76 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Aug 2024 09:17:52.7435 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f973ab79-4632-4754-70a4-08dcc80b75fa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DF.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7587 Content-Type: text/plain; charset="utf-8" The HC_CONTROL_PIO_MODE bit was introduced in the HC_CONTROL register starting from version 1.1. Therefore, checking the HC_CONTROL_PIO_MODE bit on hardware that adheres to older specification revisions (i.e., versions earlier than 1.1) is incorrect. To address this, add an additional check to read the HCI version before attempting to read the HC_CONTROL_PIO_MODE status. Signed-off-by: Shyam Sundar S K Reviewed-by: Jarkko Nikula --- drivers/i3c/master/mipi-i3c-hci/core.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index 07de1cecfa30..a6781cfeebb8 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -630,8 +630,8 @@ static irqreturn_t i3c_hci_irq_handler(int irq, void *d= ev_id) =20 static int i3c_hci_init(struct i3c_hci *hci) { + bool size_in_dwords, mode_selector; u32 regval, offset; - bool size_in_dwords; int ret; =20 /* Validate HCI hardware version */ @@ -753,10 +753,13 @@ static int i3c_hci_init(struct i3c_hci *hci) return -EINVAL; } =20 + mode_selector =3D hci->version_major > 1 || + (hci->version_major =3D=3D 1 && hci->version_minor > 0); + /* Try activating DMA operations first */ if (hci->RHS_regs) { reg_clear(HC_CONTROL, HC_CONTROL_PIO_MODE); - if (reg_read(HC_CONTROL) & HC_CONTROL_PIO_MODE) { + if (mode_selector && (reg_read(HC_CONTROL) & HC_CONTROL_PIO_MODE)) { dev_err(&hci->master.dev, "PIO mode is stuck\n"); ret =3D -EIO; } else { @@ -768,7 +771,7 @@ static int i3c_hci_init(struct i3c_hci *hci) /* If no DMA, try PIO */ if (!hci->io && hci->PIO_regs) { reg_set(HC_CONTROL, HC_CONTROL_PIO_MODE); - if (!(reg_read(HC_CONTROL) & HC_CONTROL_PIO_MODE)) { + if (mode_selector && !(reg_read(HC_CONTROL) & HC_CONTROL_PIO_MODE)) { dev_err(&hci->master.dev, "DMA mode is stuck\n"); ret =3D -EIO; } else { --=20 2.25.1 From nobody Thu Sep 19 01:04:54 2024 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2068.outbound.protection.outlook.com [40.107.102.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E453D18E02F for ; Thu, 29 Aug 2024 09:17:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.102.68 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724923081; cv=fail; b=DzLLCBAQnv6ZtCZKM75410yUQq4ZLofjgvxJf94oYGL+pdLNAdKwYWpmuTNFo+Vr0iGL7MaBa1fSimRjcvb1FJxoXf1mJir2WVwzM+1LQ1W44AgdYs+WBlpsmWFb4mQRUkmIzYFcFdLPJz/TLQFrlUCS3N2d+i2SmbWxeO2kR00= ARC-Message-Signature: i=2; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Aug 2024 09:17:55.4935 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cd9101fc-f263-4390-9824-08dcc80b77a7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DF.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6362 Content-Type: text/plain; charset="utf-8" The AMD HCI controller currently only supports PIO mode but exposes DMA rings to the OS, which leads to the controller being configured in DMA mode. To address this, add a quirk to avoid configuring the controller in DMA mode and default to PIO mode. Additionally, introduce a generic quirk infrastructure to the mipi-i3c-hci driver to facilitate seamless future quirk additions. Reviewed-by: Jarkko Nikula Co-developed-by: Krishnamoorthi M Signed-off-by: Krishnamoorthi M Co-developed-by: Guruvendra Punugupati Signed-off-by: Guruvendra Punugupati Signed-off-by: Shyam Sundar S K --- drivers/i3c/master/mipi-i3c-hci/core.c | 8 +++++++- drivers/i3c/master/mipi-i3c-hci/hci.h | 1 + 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index a6781cfeebb8..23abf91b277b 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -756,6 +756,10 @@ static int i3c_hci_init(struct i3c_hci *hci) mode_selector =3D hci->version_major > 1 || (hci->version_major =3D=3D 1 && hci->version_minor > 0); =20 + /* Quirk for HCI_QUIRK_PIO_MODE on AMD platforms */ + if (hci->quirks & HCI_QUIRK_PIO_MODE) + hci->RHS_regs =3D NULL; + /* Try activating DMA operations first */ if (hci->RHS_regs) { reg_clear(HC_CONTROL, HC_CONTROL_PIO_MODE); @@ -806,6 +810,8 @@ static int i3c_hci_probe(struct platform_device *pdev) /* temporary for dev_printk's, to be replaced in i3c_master_register */ hci->master.dev.init_name =3D dev_name(&pdev->dev); =20 + hci->quirks =3D (unsigned long)device_get_match_data(&pdev->dev); + ret =3D i3c_hci_init(hci); if (ret) return ret; @@ -838,7 +844,7 @@ static const __maybe_unused struct of_device_id i3c_hci= _of_match[] =3D { MODULE_DEVICE_TABLE(of, i3c_hci_of_match); =20 static const struct acpi_device_id i3c_hci_acpi_match[] =3D { - { "AMDI5017" }, + { "AMDI5017", HCI_QUIRK_PIO_MODE }, {} }; MODULE_DEVICE_TABLE(acpi, i3c_hci_acpi_match); diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index f94d95e024be..c56b838fb431 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -135,6 +135,7 @@ struct i3c_hci_dev_data { =20 /* list of quirks */ #define HCI_QUIRK_RAW_CCC BIT(1) /* CCC framing must be explicit */ +#define HCI_QUIRK_PIO_MODE BIT(2) /* Set PIO mode for AMD platforms */ =20 =20 /* global functions */ --=20 2.25.1 From nobody Thu Sep 19 01:04:54 2024 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2063.outbound.protection.outlook.com [40.107.92.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC51C18E050 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Aug 2024 09:17:58.1654 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4878e49e-dd29-4121-4a86-08dcc80b793f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DF.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8938 Content-Type: text/plain; charset="utf-8" The reg_* helper macros are currently limited to core.c. Moving them to hci.h will allow their functionality to be utilized in other files outside of core.c. Reviewed-by: Jarkko Nikula Co-developed-by: Guruvendra Punugupati Signed-off-by: Guruvendra Punugupati Signed-off-by: Shyam Sundar S K --- drivers/i3c/master/mipi-i3c-hci/core.c | 6 ------ drivers/i3c/master/mipi-i3c-hci/hci.h | 5 +++++ 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index 23abf91b277b..c03e86690073 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -27,11 +26,6 @@ * Host Controller Capabilities and Operation Registers */ =20 -#define reg_read(r) readl(hci->base_regs + (r)) -#define reg_write(r, v) writel(v, hci->base_regs + (r)) -#define reg_set(r, v) reg_write(r, reg_read(r) | (v)) -#define reg_clear(r, v) reg_write(r, reg_read(r) & ~(v)) - #define HCI_VERSION 0x00 /* HCI Version (in BCD) */ =20 #define HC_CONTROL 0x04 diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index c56b838fb431..76658789b018 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -10,6 +10,7 @@ #ifndef HCI_H #define HCI_H =20 +#include =20 /* Handy logging macro to save on line length */ #define DBG(x, ...) pr_devel("%s: " x "\n", __func__, ##__VA_ARGS__) @@ -26,6 +27,10 @@ #define W2_BIT_(x) BIT((x) - 64) #define W3_BIT_(x) BIT((x) - 96) =20 +#define reg_read(r) readl(hci->base_regs + (r)) +#define reg_write(r, v) writel(v, hci->base_regs + (r)) +#define reg_set(r, v) reg_write(r, reg_read(r) | (v)) +#define reg_clear(r, v) reg_write(r, reg_read(r) & ~(v)) =20 struct hci_cmd_ops; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Aug 2024 09:18:03.1498 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d73b7506-9024-4cc0-ed4e-08dcc80b7c2b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DF.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6122 Content-Type: text/plain; charset="utf-8" The AMD HCI controller is currently unstable at 12.5 MHz. To address this, a quirk is added to configure the clock rate to 9 MHz as a workaround, with proportional adjustments to the Open-Drain (OD) and Push-Pull (PP) values. Reviewed-by: Jarkko Nikula Co-developed-by: Guruvendra Punugupati Signed-off-by: Guruvendra Punugupati Signed-off-by: Shyam Sundar S K --- drivers/i3c/master/mipi-i3c-hci/Makefile | 3 +- drivers/i3c/master/mipi-i3c-hci/core.c | 6 +++- drivers/i3c/master/mipi-i3c-hci/hci.h | 2 ++ drivers/i3c/master/mipi-i3c-hci/hci_quirks.c | 33 ++++++++++++++++++++ 4 files changed, 42 insertions(+), 2 deletions(-) create mode 100644 drivers/i3c/master/mipi-i3c-hci/hci_quirks.c diff --git a/drivers/i3c/master/mipi-i3c-hci/Makefile b/drivers/i3c/master/= mipi-i3c-hci/Makefile index a658e7b8262c..1f8cd5c48fde 100644 --- a/drivers/i3c/master/mipi-i3c-hci/Makefile +++ b/drivers/i3c/master/mipi-i3c-hci/Makefile @@ -3,4 +3,5 @@ obj-$(CONFIG_MIPI_I3C_HCI) +=3D mipi-i3c-hci.o mipi-i3c-hci-y :=3D core.o ext_caps.o pio.o dma.o \ cmd_v1.o cmd_v2.o \ - dat_v1.o dct_v1.o + dat_v1.o dct_v1.o \ + hci_quirks.o diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index c03e86690073..f9ce0ee2cfd5 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -785,6 +785,10 @@ static int i3c_hci_init(struct i3c_hci *hci) return ret; } =20 + /* Configure OD and PP timings for AMD platforms */ + if (hci->quirks & HCI_QUIRK_OD_PP_TIMING) + amd_set_od_pp_timing(hci); + return 0; } =20 @@ -838,7 +842,7 @@ static const __maybe_unused struct of_device_id i3c_hci= _of_match[] =3D { MODULE_DEVICE_TABLE(of, i3c_hci_of_match); =20 static const struct acpi_device_id i3c_hci_acpi_match[] =3D { - { "AMDI5017", HCI_QUIRK_PIO_MODE }, + { "AMDI5017", HCI_QUIRK_PIO_MODE | HCI_QUIRK_OD_PP_TIMING }, {} }; MODULE_DEVICE_TABLE(acpi, i3c_hci_acpi_match); diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index 76658789b018..361e1366fe38 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -141,11 +141,13 @@ struct i3c_hci_dev_data { /* list of quirks */ #define HCI_QUIRK_RAW_CCC BIT(1) /* CCC framing must be explicit */ #define HCI_QUIRK_PIO_MODE BIT(2) /* Set PIO mode for AMD platforms */ +#define HCI_QUIRK_OD_PP_TIMING BIT(3) /* Set OD and PP timings for AMD p= latforms */ =20 =20 /* global functions */ void mipi_i3c_hci_resume(struct i3c_hci *hci); void mipi_i3c_hci_pio_reset(struct i3c_hci *hci); void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci); +void amd_set_od_pp_timing(struct i3c_hci *hci); =20 #endif diff --git a/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c b/drivers/i3c/mas= ter/mipi-i3c-hci/hci_quirks.c new file mode 100644 index 000000000000..e8ea4d101f66 --- /dev/null +++ b/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * I3C HCI Quirks + * + * Copyright 2024 Advanced Micro Devices, Inc. + * + * Authors: Shyam Sundar S K + * Guruvendra Punugupati + */ + +#include +#include "hci.h" + +/* Timing registers */ +#define HCI_SCL_I3C_OD_TIMING 0x214 +#define HCI_SCL_I3C_PP_TIMING 0x218 +#define HCI_SDA_HOLD_SWITCH_DLY_TIMING 0x230 + +/* Timing values to configure 9MHz frequency */ +#define AMD_SCL_I3C_OD_TIMING 0x00cf00cf +#define AMD_SCL_I3C_PP_TIMING 0x00160016 + +void amd_set_od_pp_timing(struct i3c_hci *hci) +{ + u32 data; + + reg_write(HCI_SCL_I3C_OD_TIMING, AMD_SCL_I3C_OD_TIMING); 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Thu, 29 Aug 2024 09:18:06 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN2PEPF000055DF.mail.protection.outlook.com (10.167.245.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7939.2 via Frontend Transport; Thu, 29 Aug 2024 09:18:05 +0000 Received: from jatayu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 29 Aug 2024 04:18:01 -0500 From: Shyam Sundar S K To: Alexandre Belloni , Jarkko Nikula CC: Guruvendra Punugupati , Krishnamoorthi M , , , Shyam Sundar S K Subject: [PATCH v6 6/6] i3c: mipi-i3c-hci: Add a quirk to set Response buffer threshold Date: Thu, 29 Aug 2024 14:47:13 +0530 Message-ID: <20240829091713.736217-7-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240829091713.736217-1-Shyam-sundar.S-k@amd.com> References: <20240829091713.736217-1-Shyam-sundar.S-k@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000055DF:EE_|DS7PR12MB6261:EE_ X-MS-Office365-Filtering-Correlation-Id: d1a3b967-c155-41e0-1523-08dcc80b7dd9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Aug 2024 09:18:05.9467 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d1a3b967-c155-41e0-1523-08dcc80b7dd9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DF.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6261 Content-Type: text/plain; charset="utf-8" The current driver sets the response buffer threshold value to 1 (N+1, 2 DWORDS) in the QUEUE THRESHOLD register. However, the AMD I3C controller only generates interrupts when the response buffer threshold value is set to 0 (1 DWORD). Therefore, a quirk is added to set the response buffer threshold value to 0. Reviewed-by: Jarkko Nikula Co-developed-by: Krishnamoorthi M Signed-off-by: Krishnamoorthi M Co-developed-by: Guruvendra Punugupati Signed-off-by: Guruvendra Punugupati Signed-off-by: Shyam Sundar S K --- drivers/i3c/master/mipi-i3c-hci/core.c | 6 +++++- drivers/i3c/master/mipi-i3c-hci/hci.h | 2 ++ drivers/i3c/master/mipi-i3c-hci/hci_quirks.c | 11 +++++++++++ 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index f9ce0ee2cfd5..a82c47c9986d 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -146,6 +146,10 @@ static int i3c_hci_bus_init(struct i3c_master_controll= er *m) if (ret) return ret; =20 + /* Set RESP_BUF_THLD to 0(n) to get 1(n+1) response */ + if (hci->quirks & HCI_QUIRK_RESP_BUF_THLD) + amd_set_resp_buf_thld(hci); + reg_set(HC_CONTROL, HC_CONTROL_BUS_ENABLE); DBG("HC_CONTROL =3D %#x", reg_read(HC_CONTROL)); =20 @@ -842,7 +846,7 @@ static const __maybe_unused struct of_device_id i3c_hci= _of_match[] =3D { MODULE_DEVICE_TABLE(of, i3c_hci_of_match); =20 static const struct acpi_device_id i3c_hci_acpi_match[] =3D { - { "AMDI5017", HCI_QUIRK_PIO_MODE | HCI_QUIRK_OD_PP_TIMING }, + { "AMDI5017", HCI_QUIRK_PIO_MODE | HCI_QUIRK_OD_PP_TIMING | HCI_QUIRK_RES= P_BUF_THLD }, {} }; MODULE_DEVICE_TABLE(acpi, i3c_hci_acpi_match); diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index 361e1366fe38..aaa47ac47381 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -142,6 +142,7 @@ struct i3c_hci_dev_data { #define HCI_QUIRK_RAW_CCC BIT(1) /* CCC framing must be explicit */ #define HCI_QUIRK_PIO_MODE BIT(2) /* Set PIO mode for AMD platforms */ #define HCI_QUIRK_OD_PP_TIMING BIT(3) /* Set OD and PP timings for AMD p= latforms */ +#define HCI_QUIRK_RESP_BUF_THLD BIT(4) /* Set resp buf thld to 0 for AMD= platforms */ =20 =20 /* global functions */ @@ -149,5 +150,6 @@ void mipi_i3c_hci_resume(struct i3c_hci *hci); void mipi_i3c_hci_pio_reset(struct i3c_hci *hci); void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci); void amd_set_od_pp_timing(struct i3c_hci *hci); +void amd_set_resp_buf_thld(struct i3c_hci *hci); =20 #endif diff --git a/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c b/drivers/i3c/mas= ter/mipi-i3c-hci/hci_quirks.c index e8ea4d101f66..3b9c6e76c536 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c +++ b/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c @@ -20,6 +20,8 @@ #define AMD_SCL_I3C_OD_TIMING 0x00cf00cf #define AMD_SCL_I3C_PP_TIMING 0x00160016 =20 +#define QUEUE_THLD_CTRL 0xD0 + void amd_set_od_pp_timing(struct i3c_hci *hci) { u32 data; @@ -31,3 +33,12 @@ void amd_set_od_pp_timing(struct i3c_hci *hci) data |=3D W0_MASK(18, 16); reg_write(HCI_SDA_HOLD_SWITCH_DLY_TIMING, data); } + +void amd_set_resp_buf_thld(struct i3c_hci *hci) +{ + u32 data; + + data =3D reg_read(QUEUE_THLD_CTRL); + data =3D data & ~W0_MASK(15, 8); + reg_write(QUEUE_THLD_CTRL, data); +} --=20 2.25.1