From nobody Thu Dec 18 23:43:28 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD538159565; Thu, 29 Aug 2024 06:09:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724911788; cv=none; b=ZKc7LO2eb6FFBkZEqT6EtOAbY9AW8OFvWR0fUbpHQrPLkHwTrdJB+pMkiN/FLxSApdu+hcItfBeGb/NTG+UOXqLa+WRHx+g5H8Et2sufZaSMNc/hQLh8+l9BbqYidyfp1+Sg5oC1s5OkImiHnJ61XtDYGFwvcXCBnv4+oXaSIZ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724911788; c=relaxed/simple; bh=P6URFCyILLuvQKGjCRmRtPmHCG8HTjO1EBgsdE7kBjI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qiZT/2T8nI78g0/vGV+8DpSaWxi0l5W1Z9csOJ8K7r9aAKzNnpIUCk39qdN2CYgCC9pbfSG/oxYQm4wO8/Y11lCLdl+IBq37xH2vrm62rQ90MfYMURGwXgtxhIDggJ89grXBH6XF9HHIXIVkhudFUJEWNn0QbhKEOOjbf85taIg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=nKPMTnqb; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="nKPMTnqb" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 47T69f9w099448; Thu, 29 Aug 2024 01:09:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1724911781; bh=okC2TvE0zEjed1VKpRCxWIShXFgdJubfvoCN/k85K+4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nKPMTnqbQ0KeMWa1P3qxwDqfVEkNfxMMF4KF4YdEpumMQRPL0gSSVnlFXfh8n+wVA gILWAgHf8mqV7opzwi9BJbG1rxkcb+YQ3Wflnwb5qB+0bRJP4qF/a+eIspoya6UyjJ Q1EK24zFDbstLJdv8y4yWk1wD6SUv3UnO75ky3zs= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 47T69f04120566 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 29 Aug 2024 01:09:41 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 29 Aug 2024 01:09:40 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 29 Aug 2024 01:09:41 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.227.151]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47T69XCJ126434; Thu, 29 Aug 2024 01:09:37 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , Subject: [PATCH v4 1/2] arm64: dts: ti: k3-j722s-main: Add R5F and C7x remote processor nodes Date: Thu, 29 Aug 2024 11:39:31 +0530 Message-ID: <20240829060932.3441295-2-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240829060932.3441295-1-b-padhi@ti.com> References: <20240829060932.3441295-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Apurva Nandan The K3 J722S SoCs have one single-core Arm Cortex-R5F processor in each of the WAKEUP, MCU and MAIN voltage domain, and two C71x DSP subsystems in MAIN voltage domain. Add the DT nodes to support Inter-Processor Communication. Signed-off-by: Apurva Nandan [ refactoring changes to k3-j722s-main.dtsi ] Signed-off-by: Beleswar Padhi Reviewed-by: Andrew Davis Reviewed-by: Udit Kumar --- v4: Changelog: 1) Put standard properties (resets, firmware-name) before vendor specific properties in added DT Nodes. (Nishanth) Link to v3: https://lore.kernel.org/all/20240828112713.2668526-2-b-padhi@ti.com/ v3: Changelog: 1) None to this patch. Link to v2: https://lore.kernel.org/all/20240612112259.1131653-2-b-padhi@ti.com/ v2: Changelog: 1) Refactored changes from k3-j722s.dtsi to k3-j722s-main.dtsi. (Andrew) Link to v1: https://lore.kernel.org/all/20240607090433.488454-2-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 61 +++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j722s-main.dtsi index cadb4f7c2ea9..ed6f4ba08afc 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -153,6 +153,67 @@ usb1: usb@31200000{ dr_mode =3D "otg"; }; }; + + main_r5fss0: r5fss@78400000 { + compatible =3D "ti,am62-r5fss"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x78400000 0x00 0x78400000 0x8000>, + <0x78500000 0x00 0x78500000 0x8000>; + power-domains =3D <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + + main_r5fss0_core0: r5f@78400000 { + compatible =3D "ti,am62-r5f"; + reg =3D <0x78400000 0x00008000>, + <0x78500000 0x00008000>; + reg-names =3D "atcm", "btcm"; + resets =3D <&k3_reset 262 1>; + firmware-name =3D "j722s-main-r5f0_0-fw"; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <262>; + ti,sci-proc-ids =3D <0x04 0xff>; + ti,atcm-enable =3D <1>; + ti,btcm-enable =3D <1>; + ti,loczrama =3D <1>; + }; + }; + + c7x_0: dsp@7e000000 { + compatible =3D "ti,am62a-c7xv-dsp"; + reg =3D <0x00 0x7e000000 0x00 0x00200000>; + reg-names =3D "l2sram"; + resets =3D <&k3_reset 208 1>; + firmware-name =3D "j722s-c71_0-fw"; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <208>; + ti,sci-proc-ids =3D <0x30 0xff>; + status =3D "disabled"; + }; + + c7x_1: dsp@7e200000 { + compatible =3D "ti,am62a-c7xv-dsp"; + reg =3D <0x00 0x7e200000 0x00 0x00200000>; + reg-names =3D "l2sram"; + resets =3D <&k3_reset 268 1>; + firmware-name =3D "j722s-c71_1-fw"; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <268>; + ti,sci-proc-ids =3D <0x31 0xff>; + status =3D "disabled"; + }; +}; + +/* MCU domain overrides */ + +&mcu_r5fss0_core0 { + firmware-name =3D "j722s-mcu-r5f0_0-fw"; +}; + +/* Wakeup domain overrides */ + +&wkup_r5fss0_core0 { + firmware-name =3D "j722s-wkup-r5f0_0-fw"; }; =20 &main_conf { --=20 2.34.1 From nobody Thu Dec 18 23:43:28 2025 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F5A614B96F; Thu, 29 Aug 2024 06:09:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724911792; cv=none; b=ary3fQrVf+SWjQiBj6SgeYIs25423FedEA6CBucjq0nRuaE2B9RDVe6drAma55HG69xAFxTTeaQWfRnFtqbfPUy9az9bhkBMOI44edFJ8Ij8WAyqE9JzwI5HbWSiMrwAJ/hSVzMIH2nqeqQwI+T1fwlB7ADf9PlGR0Whxdw+skw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724911792; c=relaxed/simple; bh=E18KCSEO1P6gK1opFctjc1u2+ZEMHv98uvCXZhRWb+I=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=H16wbqkDdVhX+a3ANTqyrPltw+Xnt7DMaJvGVtPr57WW2btxrzcZ3sIf29lNYCCBOr9K7Z6WH0xGh/VQPH+GWh1leQU7DSNZL7jXqh5ng2RB8vmP+2Bj95Q7+yD9awGRJzEF1ZzataP+cSRJBuczkU6fSUyHFZLTnNmqeh0S544= ARC-Authentication-Results: i=1; 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Thu, 29 Aug 2024 01:09:44 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 29 Aug 2024 01:09:44 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 29 Aug 2024 01:09:44 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.227.151]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47T69XCK126434; Thu, 29 Aug 2024 01:09:41 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , Subject: [PATCH v4 2/2] arm64: dts: ti: k3-j722s-evm: Enable Inter-Processor Communication Date: Thu, 29 Aug 2024 11:39:32 +0530 Message-ID: <20240829060932.3441295-3-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240829060932.3441295-1-b-padhi@ti.com> References: <20240829060932.3441295-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Apurva Nandan The K3 J722S-EVM platform is based on the J722S SoC which has one single-core Arm Cortex-R5F processor in each of the WAKEUP, MCU and MAIN voltage domain, and two C71x DSP subsystems in MAIN voltage domain. The Inter-Processor communication between the A72 cores and these R5F and DSP remote cores is achieved through shared memory and Mailboxes. Thus, add the memory carveouts and enable the mailbox clusters required for communication. Also, The remoteproc firmware like of R5F and DSPs in the MAIN voltage domain use timers. Therefore, change the status of the timer nodes to "reserved" to avoid any clash during booting of remotecores. Usage is described as below: +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D+ | Remoteproc Node | Timer Node | +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D+ | main_r5fss0_core0 | main_timer0 | +-------------------+-------------+ | c7x_0 | main_timer1 | +-------------------+-------------+ | c7x_1 | main_timer2 | +-------------------+-------------+ Signed-off-by: Apurva Nandan [ Enabled mailbox instances and Reserved timer nodes ] Signed-off-by: Beleswar Padhi --- v4: Changelog: 1) Moved "status" property to the end in all the extended DT nodes added in this patch. 2) Preceded child-nodes by a single blank line in the extended DT nodes added in this patch. Link to v3: https://lore.kernel.org/all/20240828112713.2668526-3-b-padhi@ti.com/ v3: Changelog: 1) Reserved conflicting timer nodes with remoteproc firmware (reflected the= same in commit message). 2) Simplified $subject to clarify that this patch enables IPC and transferr= ed the details into commit message. Link to v2: https://lore.kernel.org/all/20240612112259.1131653-3-b-padhi@ti.com/ v2: Changelog: 1) Squashed Patch 2 and 3 from V1 into Patch 2 in V2 as they were doing the same logical thing. Links to v1: https://lore.kernel.org/all/20240607090433.488454-3-b-padhi@ti.com/ https://lore.kernel.org/all/20240607090433.488454-4-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 157 ++++++++++++++++++++++++ 1 file changed, 157 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/= ti/k3-j722s-evm.dts index dd3b5f7039d7..38620c76c3be 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -51,12 +51,71 @@ secure_ddr: optee@9e800000 { no-map; }; =20 + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; =20 + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000= { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a20000= 00 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + c7x_0_dma_memory_region: c7x-dma-memory@a3000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: c7x-memory@a3100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + c7x_1_dma_memory_region: c7x-dma-memory@a4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + c7x_1_memory_region: c7x-memory@a4100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a5000000 { + reg =3D <0x00 0xa5000000 0x00 0x1c00000>; + alignment =3D <0x1000>; + no-map; + }; }; =20 vmain_pd: regulator-0 { @@ -494,6 +553,104 @@ &sdhci1 { bootph-all; }; =20 +&mailbox0_cluster0 { + status =3D "okay"; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status =3D "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + status =3D "okay"; + + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster3 { + status =3D "okay"; + + mbox_main_r5_0: mbox-main-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_c7x_1: mbox-c7x-1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status =3D "reserved"; +}; + +&main_timer1 { + status =3D "reserved"; +}; + +&main_timer2 { + status =3D "reserved"; +}; + +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&main_r5fss0 { + status =3D "okay"; +}; + +&main_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster3 &mbox_main_r5_0>; + memory-region =3D <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&c7x_0 { + mboxes =3D <&mailbox0_cluster2 &mbox_c7x_0>; + memory-region =3D <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; + status =3D "okay"; +}; + +&c7x_1 { + mboxes =3D <&mailbox0_cluster3 &mbox_c7x_1>; + memory-region =3D <&c7x_1_dma_memory_region>, + <&c7x_1_memory_region>; + status =3D "okay"; +}; + &serdes_ln_ctrl { idle-states =3D , ; --=20 2.34.1