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a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Support quad pipe in general operations with unified method. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 87 +++++++++++++++++----------= ---- 1 file changed, 47 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index c38c1bedd40fb..c3ea97b4ce439 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -619,6 +619,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdp= u, struct msm_drm_private *priv =3D plane->dev->dev_private; struct dpu_plane_state *pstate =3D to_dpu_plane_state(plane->state); u32 fill_color =3D (color & 0xFFFFFF) | ((alpha & 0xFF) << 24); + int i; =20 DPU_DEBUG_PLANE(pdpu, "\n"); =20 @@ -632,12 +633,11 @@ static void _dpu_plane_color_fill(struct dpu_plane *p= dpu, return; =20 /* update sspp */ - _dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_r= ect, - fill_color, fmt); - - if (pstate->r_pipe.sspp) - _dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg.= dst_rect, - fill_color, fmt); + for (i =3D 0; i < PIPES_PER_STAGE; i++) + if (pstate->pipe[i].sspp) + _dpu_plane_color_fill_pipe(pstate, &pstate->pipe[i], + &pstate->pipe_cfg[i].dst_rect, + fill_color, fmt); } =20 static int dpu_plane_prepare_fb(struct drm_plane *plane, @@ -1279,8 +1279,11 @@ void dpu_plane_flush(struct drm_plane *plane) /* force 100% alpha */ _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); else { - dpu_plane_flush_csc(pdpu, &pstate->pipe); - dpu_plane_flush_csc(pdpu, &pstate->r_pipe); + int i; + + for (i =3D 0; i < PIPES_PER_STAGE; i++) + if (pstate->pipe_cfg[i].visible) + dpu_plane_flush_csc(pdpu, &pstate->pipe[i]); } =20 /* flag h/w flush complete */ @@ -1380,20 +1383,17 @@ static void dpu_plane_sspp_atomic_update(struct drm= _plane *plane) struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct drm_plane_state *state =3D plane->state; struct dpu_plane_state *pstate =3D to_dpu_plane_state(state); - struct dpu_sw_pipe *pipe =3D &pstate->pipe; - struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; struct drm_crtc *crtc =3D state->crtc; struct drm_framebuffer *fb =3D state->fb; bool is_rt_pipe; const struct msm_format *fmt =3D msm_framebuffer_format(fb); - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; + struct dpu_sw_pipe_cfg *pipe_cfg; struct dpu_kms *kms =3D _dpu_plane_get_kms(&pdpu->base); struct msm_gem_address_space *aspace =3D kms->base.aspace; struct dpu_hw_fmt_layout layout; bool layout_valid =3D false; - int ret; + int ret, i; =20 ret =3D dpu_format_populate_layout(aspace, fb, &layout); if (ret) @@ -1412,28 +1412,28 @@ static void dpu_plane_sspp_atomic_update(struct drm= _plane *plane) crtc->base.id, DRM_RECT_ARG(&state->dst), &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt)); =20 - dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt, - drm_mode_vrefresh(&crtc->mode), - layout_valid ? &layout : NULL); - - if (r_pipe->sspp) { - dpu_plane_sspp_update_pipe(plane, r_pipe, r_pipe_cfg, fmt, - drm_mode_vrefresh(&crtc->mode), - layout_valid ? &layout : NULL); + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (pstate->pipe_cfg[i].visible && pstate->pipe[i].sspp) + dpu_plane_sspp_update_pipe(plane, &pstate->pipe[i], + &pstate->pipe_cfg[i], fmt, + drm_mode_vrefresh(&crtc->mode), + layout_valid ? &layout : NULL); } =20 if (pstate->needs_qos_remap) pstate->needs_qos_remap =3D false; =20 - pstate->plane_fetch_bw =3D _dpu_plane_calc_bw(pdpu->catalog, fmt, - &crtc->mode, pipe_cfg); - - pstate->plane_clk =3D _dpu_plane_calc_clk(&crtc->mode, pipe_cfg); - - if (r_pipe->sspp) { - pstate->plane_fetch_bw +=3D _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc= ->mode, r_pipe_cfg); + pstate->plane_fetch_bw =3D 0; + pstate->plane_clk =3D 0; + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + pipe_cfg =3D &pstate->pipe_cfg[i]; + if (pipe_cfg->visible) { + pstate->plane_fetch_bw +=3D _dpu_plane_calc_bw(pdpu->catalog, fmt, + &crtc->mode, pipe_cfg); =20 - pstate->plane_clk =3D max(pstate->plane_clk, _dpu_plane_calc_clk(&crtc->= mode, r_pipe_cfg)); + pstate->plane_clk =3D max(pstate->plane_clk, + _dpu_plane_calc_clk(&crtc->mode, pipe_cfg)); + } } } =20 @@ -1441,17 +1441,21 @@ static void _dpu_plane_atomic_disable(struct drm_pl= ane *plane) { struct drm_plane_state *state =3D plane->state; struct dpu_plane_state *pstate =3D to_dpu_plane_state(state); - struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; + struct dpu_sw_pipe *pipe; + int i; =20 - trace_dpu_plane_disable(DRMID(plane), false, - pstate->pipe.multirect_mode); + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + pipe =3D &pstate->pipe[i]; + if (pipe->multirect_index =3D=3D DPU_SSPP_RECT_1) { + trace_dpu_plane_disable(DRMID(plane), false, + pstate->pipe[i - 1].multirect_mode); =20 - if (r_pipe->sspp) { - r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; =20 - if (r_pipe->sspp->ops.setup_multirect) - r_pipe->sspp->ops.setup_multirect(r_pipe); + if (pipe->sspp && pipe->sspp->ops.setup_multirect) + pipe->sspp->ops.setup_multirect(pipe); + } } =20 pstate->pending =3D true; @@ -1607,14 +1611,17 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane = *plane, bool enable) struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(plane->state); struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); + int i; =20 if (!pdpu->is_rt_pipe) return; =20 pm_runtime_get_sync(&dpu_kms->pdev->dev); - _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable); - if (pstate->r_pipe.sspp) - _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable); + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (!pstate->pipe_cfg[i].visible) + break; + _dpu_plane_set_qos_ctrl(plane, &pstate->pipe[i], enable); + } pm_runtime_put_sync(&dpu_kms->pdev->dev); } #endif --=20 2.34.1