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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240829-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-8-v1-14-bdb05b4b5a2e@linaro.org> References: <20240829-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-8-v1-0-bdb05b4b5a2e@linaro.org> In-Reply-To: <20240829-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-8-v1-0-bdb05b4b5a2e@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724926736; l=6676; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=7i2tZ6lsHlQvWtNNIv33X2jDrdBkZS2b+kzYUWO0fMI=; b=C6t5JxSLHz+r3FxGXyme5vAaHho61+PC/rRPPm+gGMljnzAh5OkDyqUlIUQJKDLPB5ANtLE6L 1Q7bIVmclZrBssFJaeh+hTvIJjBVyUs/Yjv5HDdU8jFVZlVYwrE8yD5 X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Support quad-pipe in SSPP checking with unified method Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 108 ++++++++++++++------------= ---- 1 file changed, 51 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 4df7cfed4d230..78bf8f0292f62 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -738,12 +738,40 @@ static int dpu_plane_check_inline_rotation(struct dpu= _plane *pdpu, static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe, struct dpu_sw_pipe_cfg *pipe_cfg, - const struct msm_format *fmt, - const struct drm_display_mode *mode) + const struct drm_display_mode *mode, + struct drm_plane_state *new_plane_state) { uint32_t min_src_size; struct dpu_kms *kms =3D _dpu_plane_get_kms(&pdpu->base); int ret; + const struct msm_format *fmt; + uint32_t supported_rotations; + const struct dpu_sspp_cfg *pipe_hw_caps; + const struct dpu_sspp_sub_blks *sblk; + + pipe_hw_caps =3D pipe->sspp->cap; + sblk =3D pipe->sspp->cap->sblk; + + /* + * We already have verified scaling against platform limitations. + * Now check if the SSPP supports scaling at all. + */ + if (!sblk->scaler_blk.len && + ((drm_rect_width(&new_plane_state->src) >> 16 !=3D + drm_rect_width(&new_plane_state->dst)) || + (drm_rect_height(&new_plane_state->src) >> 16 !=3D + drm_rect_height(&new_plane_state->dst)))) + return -ERANGE; + + fmt =3D msm_framebuffer_format(new_plane_state->fb); + + supported_rotations =3D DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; + + if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) + supported_rotations |=3D DRM_MODE_ROTATE_90; + + pipe_cfg->rotation =3D drm_rotation_simplify(new_plane_state->rotation, + supported_rotations); =20 min_src_size =3D MSM_FORMAT_IS_YUV(fmt) ? 2 : 1; =20 @@ -886,8 +914,7 @@ static int dpu_plane_atomic_check_nopipe(struct drm_pla= ne *plane, return 0; } =20 -static int dpu_plane_is_multirect_parallel_capable(struct dpu_sw_pipe *pip= e, - struct dpu_sw_pipe_cfg *pipe_cfg, +static int dpu_plane_is_multirect_parallel_capable(struct dpu_sw_pipe_cfg = *pipe_cfg, const struct msm_format *fmt, uint32_t max_linewidth) { @@ -916,49 +943,19 @@ static int dpu_plane_atomic_check_pipes(struct drm_pl= ane *plane, drm_atomic_get_new_plane_state(state, plane); struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); - struct dpu_sw_pipe *pipe =3D &pstate->pipe; - struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; - const struct msm_format *fmt; - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; - uint32_t supported_rotations; - const struct dpu_sspp_cfg *pipe_hw_caps; - const struct dpu_sspp_sub_blks *sblk; - int ret =3D 0; - - pipe_hw_caps =3D pipe->sspp->cap; - sblk =3D pipe->sspp->cap->sblk; - - /* - * We already have verified scaling against platform limitations. - * Now check if the SSPP supports scaling at all. - */ - if (!sblk->scaler_blk.len && - ((drm_rect_width(&new_plane_state->src) >> 16 !=3D - drm_rect_width(&new_plane_state->dst)) || - (drm_rect_height(&new_plane_state->src) >> 16 !=3D - drm_rect_height(&new_plane_state->dst)))) - return -ERANGE; - - fmt =3D msm_framebuffer_format(new_plane_state->fb); - - supported_rotations =3D DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; - - if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) - supported_rotations |=3D DRM_MODE_ROTATE_90; - - pipe_cfg->rotation =3D drm_rotation_simplify(new_plane_state->rotation, - supported_rotations); - r_pipe_cfg->rotation =3D pipe_cfg->rotation; - - ret =3D dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt, - &crtc_state->adjusted_mode); - if (ret) - return ret; + struct dpu_sw_pipe *pipe; + struct dpu_sw_pipe_cfg *pipe_cfg; + int ret =3D 0, i; =20 - if (drm_rect_width(&r_pipe_cfg->src_rect) !=3D 0) { - ret =3D dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt, - &crtc_state->adjusted_mode); + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + pipe =3D &pstate->pipe[i]; + pipe_cfg =3D &pstate->pipe_cfg[i]; + if (!pipe_cfg->visible || !pipe->sspp) + break; + DPU_DEBUG_PLANE(pdpu, "pipe %d is in use, validate it\n", i); + ret =3D dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, + &crtc_state->adjusted_mode, + new_plane_state); if (ret) return ret; } @@ -975,10 +972,10 @@ static int dpu_plane_atomic_check(struct drm_plane *p= lane, struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); - struct dpu_sw_pipe *pipe =3D &pstate->pipe; - struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; + struct dpu_sw_pipe *pipe =3D &pstate->pipe[0]; + struct dpu_sw_pipe *r_pipe =3D &pstate->pipe[1]; + struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg[0]; + struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->pipe_cfg[1]; const struct drm_crtc_state *crtc_state =3D NULL; =20 if (new_plane_state->crtc) @@ -1033,13 +1030,10 @@ static int dpu_plane_atomic_check(struct drm_plane = *plane, return -E2BIG; } =20 - /* - * Use multirect for wide plane. We do not support dynamic - * assignment of SSPPs, so we know the configuration. - */ pipe->multirect_index =3D DPU_SSPP_RECT_0; pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_PARALLEL; =20 + r_pipe->sspp =3D pipe->sspp; r_pipe->multirect_index =3D DPU_SSPP_RECT_1; r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_PARALLEL; } @@ -1056,7 +1050,7 @@ static int dpu_plane_virtual_atomic_check(struct drm_= plane *plane, drm_atomic_get_old_plane_state(state, plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(plane_state); struct drm_crtc_state *crtc_state; - int ret; + int ret, i; =20 if (plane_state->crtc) crtc_state =3D drm_atomic_get_new_crtc_state(state, @@ -1071,8 +1065,8 @@ static int dpu_plane_virtual_atomic_check(struct drm_= plane *plane, * resources are freed by dpu_crtc_assign_plane_resources(), * but clean them here. */ - pstate->pipe.sspp =3D NULL; - pstate->r_pipe.sspp =3D NULL; + for (i =3D 0; i < PIPES_PER_STAGE; i++) + pstate->pipe[i].sspp =3D NULL; =20 return 0; } --=20 2.34.1