From nobody Mon Feb 9 09:09:16 2026 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13EAD1B4C2F for ; Thu, 29 Aug 2024 12:35:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724934919; cv=none; b=c+afABDmDLxJePHlL2nxM2xI/JX5G2tpYp3wcbbwAPHrJWAxaFeWPpOMyfdOpQP1iBktOteS3cJJ6iSzFQa82bArl/ggR5VfbzPOmruZgyEed3rumHSFC2vpthQAqLXH1zoGOC5DW1JcWWXX+uzXWkq1uVsJlNZhOwPOMp+22CM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724934919; c=relaxed/simple; bh=P39S0xWGxif30WD1UKDRfbbud3uciFtE/rLUEAb4cIs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TlBxNBrMX71M3ZVv7u7JQGLQGQIrhWDxkU9+E6mmWbWXRQ9AvpDDUZl+wANiHcThdkzEBhVEiE6jQbea1JB148upA1RmFtbzKWpKlDT1zbHD4KmxWrcxxunNM1BWNhQbO5lFHWC/OE+okLflvp/NG7n25v2cSr2MOPOUnpwfwmg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=WagV9jzm; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="WagV9jzm" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-42ba79ae3beso911615e9.3 for ; Thu, 29 Aug 2024 05:35:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1724934915; x=1725539715; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=HtZQMCUxJF90XHx7mBzRmkvuAg8yISi1s5y8keOdRpY=; b=WagV9jzmCbAzdIMX+wayEv/U1CQVh+TbMPSsIwOWnMuZBe+HR+6YYa3ms2kVZ6GfHt Z+UZuFZTzW83M+dntT7D5WDY3xpNRHD+FneBKw3XxqmWu5RwcEUxKObkhqI+seaiai0N 50xeQzQv59eOhJ/eEKNoPYzKoun9WaJ284yfoytKeGNzrCnzugozV2jne9yXmHrZ8mS1 sORX/A6u85JoXmeDAtk2NKNmKvv13vUz0YXMACPrvdeNUDCNZ/hevehW42qi/SHETmpr 4ViDGu0N9Nc2ZXjdpA+if7+Ygv0HpMTR4O5rcHlILp7aQ9wiRNTHv1oJtazMzSM9GHr5 FaSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724934915; x=1725539715; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HtZQMCUxJF90XHx7mBzRmkvuAg8yISi1s5y8keOdRpY=; b=w3pIFMrrlhoaZ+X1Xh5zVo5YXtNCIA7ptf91tgFlzDl9GZrN5l25D5Pj2Yo/3osHt2 9MCNFphZ53/8FNAiWRBePubPl7d1DoZW2KR+tXW2+fPlMu4fX5FsJoX5o0A0sKFnKQUx l1pwSSUY/fwAeVTcQkJ/hwYhEPWSmSMzUhT75YFXkJeHkjczKKOc477fkLMEKuw93dQa /j5qsAirxdebWZrLpo4R7zyWRCcdNOBeB9JddjYYGQ4fvnkzrWV5SYZpkVd4RtF/56ei /G+cFj4sTOA1RSrpWurm3Xt8pg+9/I3l41MP+/00u+6RqRPam4434z7oqvezl9yHI//9 3TAQ== X-Forwarded-Encrypted: i=1; AJvYcCWk6Rdf42s7u5Qp5UjtYPr514mytxO5BHsxkF/Uho+bkipcH+bEOw3FqrI1QVyMKBcMgfWwjBlGY5rWbXI=@vger.kernel.org X-Gm-Message-State: AOJu0YxNPkKBEX/1iL3u1f4Rnfdq7d0SbNdB0n+6EeBRDkarv2w0+/fX wmFg32BYt9I3Xmgvu8++E+OU92f3mSJktb0ZSu9OH9QOU/uAhLPKzZSsShcFt2E= X-Google-Smtp-Source: AGHT+IHMCny/BXrKQLClrHAVa0bXylD+v3GOBAlKy2cTPgEk0L3KGGJBHGUHi88jj30y+EeSMfndiA== X-Received: by 2002:a05:600c:3c82:b0:424:ac9f:5c61 with SMTP id 5b1f17b1804b1-42bb0205099mr13458775e9.3.1724934915260; Thu, 29 Aug 2024 05:35:15 -0700 (PDT) Received: from [127.0.1.1] ([178.197.222.82]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3749ee4a55fsm1322270f8f.10.2024.08.29.05.35.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Aug 2024 05:35:14 -0700 (PDT) From: Krzysztof Kozlowski Date: Thu, 29 Aug 2024 14:34:42 +0200 Subject: [PATCH v2 07/17] arm64: dts: qcom: sm6115: change labels to lower-case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240829-dts-qcom-label-v2-7-5deaada3e6b2@linaro.org> References: <20240829-dts-qcom-label-v2-0-5deaada3e6b2@linaro.org> In-Reply-To: <20240829-dts-qcom-label-v2-0-5deaada3e6b2@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=12301; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=P39S0xWGxif30WD1UKDRfbbud3uciFtE/rLUEAb4cIs=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBm0GrrGO5AAWdCMzl1CaGiVOrRQDuhYFg8Vi5UR XMvG3JPdnSJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZtBq6wAKCRDBN2bmhouD 1zTaD/wJAqeKXqkMXTqs30kF9xLpMYbY8OJlfvpaUYuVwvpyu8bG1uKOO9GFNf7yBi/EgyGO2Pm cJI3wGBTPQpTucJidDM2tkJtWN92D9Oj1Z0l+Z8GsNoxcgmpmu3pHCR4RzQ2vPPJqi3r7JBefJt 5rv6yf690uCCT2S5jtE1VZ2kU10TuRsh70niRBd9wnoiYOB9ydeVFNRJISsHIUN9l7pZatS8fDE PjeEwj4WYxc3JpFN7l9u/CZj0cV4JTJlcju9gF967cQECCsl2/Gm/UqB2Gb8h9KT1K7LyQj+hdD gECu0GG9cAi6u1G+WhBVl4K6Y5nQtXWFRYpCGB5RoN/I9uZ9xkIasVgUjn2QjgAHi5NVqPy1snY TOJsqjX1ujlMosTu2TRP+Sy87ckWM8BGz42mBUBp5C01/B51IDb8Whw+lezTWfnvR4ATA/4PgMU 6MzwnwrWZXkoPMHYvCaJSQKH0cQlOOcLlsk9WlNgA6GYP57e/K0Ms+y6qGLNFHO93jbLrXDohn5 /3surqWJPgu/ZGTE6EyAhvvyjMTf00V9Y/2uOannk9CyIsGJodFa83VocoAlxwGbmzCNnF8lIAJ Cc50zHKiMoA/xC4AnQQwwekVMqQiQG42Hvl7WIZQTA0FVGF9c3Gukr8h2qZMrBRzcETLh1X3bE8 bOPUyDuYBo/mScg== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm4250.dtsi | 16 ++-- arch/arm64/boot/dts/qcom/sm6115.dtsi | 152 +++++++++++++++++--------------= ---- 2 files changed, 84 insertions(+), 84 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm4250.dtsi b/arch/arm64/boot/dts/qco= m/sm4250.dtsi index c5add8f44fc0..a0ed61925e12 100644 --- a/arch/arm64/boot/dts/qcom/sm4250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4250.dtsi @@ -5,34 +5,34 @@ =20 #include "sm6115.dtsi" =20 -&CPU0 { +&cpu0 { compatible =3D "qcom,kryo240"; }; =20 -&CPU1 { +&cpu1 { compatible =3D "qcom,kryo240"; }; =20 -&CPU2 { +&cpu2 { compatible =3D "qcom,kryo240"; }; =20 -&CPU3 { +&cpu3 { compatible =3D "qcom,kryo240"; }; =20 -&CPU4 { +&cpu4 { compatible =3D "qcom,kryo240"; }; =20 -&CPU5 { +&cpu5 { compatible =3D "qcom,kryo240"; }; =20 -&CPU6 { +&cpu6 { compatible =3D "qcom,kryo240"; }; =20 -&CPU7 { +&cpu7 { compatible =3D "qcom,kryo240"; }; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qco= m/sm6115.dtsi index 41216cc319d6..abaabeb41439 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -40,7 +40,7 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "qcom,kryo260"; reg =3D <0x0 0x0>; @@ -48,18 +48,18 @@ CPU0: cpu@0 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,freq-domain =3D <&cpufreq_hw 0>; - power-domains =3D <&CPU_PD0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU1: cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "qcom,kryo260"; reg =3D <0x0 0x1>; @@ -67,13 +67,13 @@ CPU1: cpu@1 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,freq-domain =3D <&cpufreq_hw 0>; - power-domains =3D <&CPU_PD1>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; }; =20 - CPU2: cpu@2 { + cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "qcom,kryo260"; reg =3D <0x0 0x2>; @@ -81,13 +81,13 @@ CPU2: cpu@2 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,freq-domain =3D <&cpufreq_hw 0>; - power-domains =3D <&CPU_PD2>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; }; =20 - CPU3: cpu@3 { + cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "qcom,kryo260"; reg =3D <0x0 0x3>; @@ -95,13 +95,13 @@ CPU3: cpu@3 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,freq-domain =3D <&cpufreq_hw 0>; - power-domains =3D <&CPU_PD3>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; }; =20 - CPU4: cpu@100 { + cpu4: cpu@100 { device_type =3D "cpu"; compatible =3D "qcom,kryo260"; reg =3D <0x0 0x100>; @@ -109,18 +109,18 @@ CPU4: cpu@100 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1638>; dynamic-power-coefficient =3D <282>; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; qcom,freq-domain =3D <&cpufreq_hw 1>; - power-domains =3D <&CPU_PD4>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; - L2_1: l2-cache { + l2_1: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; }; }; =20 - CPU5: cpu@101 { + cpu5: cpu@101 { device_type =3D "cpu"; compatible =3D "qcom,kryo260"; reg =3D <0x0 0x101>; @@ -128,13 +128,13 @@ CPU5: cpu@101 { capacity-dmips-mhz =3D <1638>; dynamic-power-coefficient =3D <282>; enable-method =3D "psci"; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; qcom,freq-domain =3D <&cpufreq_hw 1>; - power-domains =3D <&CPU_PD5>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; }; =20 - CPU6: cpu@102 { + cpu6: cpu@102 { device_type =3D "cpu"; compatible =3D "qcom,kryo260"; reg =3D <0x0 0x102>; @@ -142,13 +142,13 @@ CPU6: cpu@102 { capacity-dmips-mhz =3D <1638>; dynamic-power-coefficient =3D <282>; enable-method =3D "psci"; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; qcom,freq-domain =3D <&cpufreq_hw 1>; - power-domains =3D <&CPU_PD6>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; }; =20 - CPU7: cpu@103 { + cpu7: cpu@103 { device_type =3D "cpu"; compatible =3D "qcom,kryo260"; reg =3D <0x0 0x103>; @@ -156,46 +156,46 @@ CPU7: cpu@103 { capacity-dmips-mhz =3D <1638>; dynamic-power-coefficient =3D <282>; enable-method =3D "psci"; - next-level-cache =3D <&L2_1>; + next-level-cache =3D <&l2_1>; qcom,freq-domain =3D <&cpufreq_hw 1>; - power-domains =3D <&CPU_PD7>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; }; =20 cluster1 { core0 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core1 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core2 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core3 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -203,7 +203,7 @@ core3 { idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + little_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "silver-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000003>; @@ -213,7 +213,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + big_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "gold-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000003>; @@ -225,7 +225,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { }; =20 domain-idle-states { - CLUSTER_0_SLEEP_0: cluster-sleep-0-0 { + cluster_0_sleep_0: cluster-sleep-0-0 { /* GDHS */ compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x40000022>; @@ -234,7 +234,7 @@ CLUSTER_0_SLEEP_0: cluster-sleep-0-0 { min-residency-us =3D <782>; }; =20 - CLUSTER_0_SLEEP_1: cluster-sleep-0-1 { + cluster_0_sleep_1: cluster-sleep-0-1 { /* Power Collapse */ compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000044>; @@ -243,7 +243,7 @@ CLUSTER_0_SLEEP_1: cluster-sleep-0-1 { min-residency-us =3D <7376>; }; =20 - CLUSTER_1_SLEEP_0: cluster-sleep-1-0 { + cluster_1_sleep_0: cluster-sleep-1-0 { /* GDHS */ compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x40000042>; @@ -252,7 +252,7 @@ CLUSTER_1_SLEEP_0: cluster-sleep-1-0 { min-residency-us =3D <660>; }; =20 - CLUSTER_1_SLEEP_1: cluster-sleep-1-1 { + cluster_1_sleep_1: cluster-sleep-1-1 { /* Power Collapse */ compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000044>; @@ -306,62 +306,62 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_0_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_0_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_0_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_0_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_0_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_0_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_0_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_0_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_1_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_1_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_1_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_1_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_1_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_1_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_1_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_1_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CLUSTER_0_PD: power-domain-cpu-cluster0 { + cluster_0_pd: power-domain-cpu-cluster0 { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_0_SLEEP_0>, <&CLUSTER_0_SLEEP_1>; + domain-idle-states =3D <&cluster_0_sleep_0>, <&cluster_0_sleep_1>; }; =20 - CLUSTER_1_PD: power-domain-cpu-cluster1 { + cluster_1_pd: power-domain-cpu-cluster1 { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_1_SLEEP_0>, <&CLUSTER_1_SLEEP_1>; + domain-idle-states =3D <&cluster_1_sleep_0>, <&cluster_1_sleep_1>; }; }; =20 @@ -2405,7 +2405,7 @@ etm@9040000 { clock-names =3D "apb_pclk"; arm,coresight-loses-context-with-cpu; =20 - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; =20 status =3D "disabled"; =20 @@ -2426,7 +2426,7 @@ etm@9140000 { clock-names =3D "apb_pclk"; arm,coresight-loses-context-with-cpu; =20 - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; =20 status =3D "disabled"; =20 @@ -2447,7 +2447,7 @@ etm@9240000 { clock-names =3D "apb_pclk"; arm,coresight-loses-context-with-cpu; =20 - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; =20 status =3D "disabled"; =20 @@ -2468,7 +2468,7 @@ etm@9340000 { clock-names =3D "apb_pclk"; arm,coresight-loses-context-with-cpu; =20 - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; =20 status =3D "disabled"; =20 @@ -2489,7 +2489,7 @@ etm@9440000 { clock-names =3D "apb_pclk"; arm,coresight-loses-context-with-cpu; =20 - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; =20 status =3D "disabled"; =20 @@ -2510,7 +2510,7 @@ etm@9540000 { clock-names =3D "apb_pclk"; arm,coresight-loses-context-with-cpu; =20 - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; =20 status =3D "disabled"; =20 @@ -2531,7 +2531,7 @@ etm@9640000 { clock-names =3D "apb_pclk"; arm,coresight-loses-context-with-cpu; =20 - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; =20 status =3D "disabled"; =20 @@ -2552,7 +2552,7 @@ etm@9740000 { clock-names =3D "apb_pclk"; arm,coresight-loses-context-with-cpu; =20 - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; =20 status =3D "disabled"; =20 --=20 2.43.0