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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240829-dts-qcom-label-v2-6-5deaada3e6b2@linaro.org> References: <20240829-dts-qcom-label-v2-0-5deaada3e6b2@linaro.org> In-Reply-To: <20240829-dts-qcom-label-v2-0-5deaada3e6b2@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=41979; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=0KzD1q17RS0u/ZJlNF97Gx1fF6UDKRoIIFxquXKcgew=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBm0GrqX6yVM/Iwxu8BD9l/vWIW7SEB4QtastXUU cDjpMcZuKOJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZtBq6gAKCRDBN2bmhouD 1+DuD/9rUUkrjYWKPTp88JjHOu1e1ICv+6DXZ4RD72bTAtTdR5s1DM1xdjZPrglZOqlp2KBvSXP btPYSrsfBThYs/TM5zSlT0xBaM8dEkPblKkBpiLp2W0bATixAjJV22IZijdIbedcdHrLhxxRL/m 9pqZYutC/3np1eC+iTxMwJM1d9nlcnCC6oHj+xA1g7ZKehwOcCkYSJnl+RKbcB3mE/7CgU6csbB 039bXktiQEswrFJfv0sdHhR7Cc19w6heuJpRGJ2HXgzPVxqtU8gpUMyODTDj/iZb8jsCcoPOW7P gWT+KmUM8uv/LOsysj9pn0Lfs+bGDGQcAOtoYzHS3vex33vGkq/L7TXRGMGrlYTD1CJ5c6C8cB6 9hbgxWPY7w4P30rYSvCVHFHHcficynBGLrr7pKZEAi8EcVLnyUi6wl9lbfOcD8uaNziFrxkXyoW PiVqxxFDIwIkkGsxdEGH/POhZWUbzKrVPDkKZGHmUKmlM2aYECXSZyWz+cQHfBenzOBSfsaTLPN RbWg+u3Y3CeioGtqu7wVTYn9Gg3OdHhLWq4UaDwIq48v4qYITGAUCJnH4HpPd3qW/AFppmbJ5BG wWlru1I6hsAAb/A8PqdcZaCDxN86TKVCArYkP1KJipOUd2KafFOaCS4SnOCgUCddvlgdoI5fJkt JmhEOSkE72EEJEw== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi | 6 +- arch/arm64/boot/dts/qcom/sc7280.dtsi | 374 ++++++++++-------= ---- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 164 ++++----- 3 files changed, 272 insertions(+), 272 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm6= 4/boot/dts/qcom/sc7280-chrome-common.dtsi index cecb3e89f7f7..6005a6cfeca3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi @@ -29,7 +29,7 @@ / { cpus { domain_idle_states: domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + cluster_sleep_0: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x40003444>; entry-latency-us =3D <2752>; @@ -52,8 +52,8 @@ venus_mem: memory@8b200000 { }; }; =20 -&CLUSTER_PD { - domain-idle-states =3D <&CLUSTER_SLEEP_0>; +&cluster_pd { + domain-idle-states =3D <&cluster_sleep_0>; }; =20 &lpass_aon { diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 3d8410683402..4de3475312c5 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -193,15 +193,15 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x0>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; operating-points-v2 =3D <&cpu0_opp_table>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; @@ -209,12 +209,12 @@ CPU0: cpu@0 { <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; - L3_0: l3-cache { + next-level-cache =3D <&l3_0>; + l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; @@ -222,15 +222,15 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x100>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD1>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_100>; + next-level-cache =3D <&l2_100>; operating-points-v2 =3D <&cpu0_opp_table>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; @@ -238,23 +238,23 @@ CPU1: cpu@100 { <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; - L2_100: l2-cache { + l2_100: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x200>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD2>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_200>; + next-level-cache =3D <&l2_200>; operating-points-v2 =3D <&cpu0_opp_table>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; @@ -262,23 +262,23 @@ CPU2: cpu@200 { <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; - L2_200: l2-cache { + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x300>; clocks =3D <&cpufreq_hw 0>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD3>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_300>; + next-level-cache =3D <&l2_300>; operating-points-v2 =3D <&cpu0_opp_table>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; @@ -286,23 +286,23 @@ CPU3: cpu@300 { <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; - L2_300: l2-cache { + l2_300: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU4: cpu@400 { + cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x400>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD4>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_400>; + next-level-cache =3D <&l2_400>; operating-points-v2 =3D <&cpu4_opp_table>; capacity-dmips-mhz =3D <1946>; dynamic-power-coefficient =3D <520>; @@ -310,23 +310,23 @@ CPU4: cpu@400 { <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; - L2_400: l2-cache { + l2_400: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU5: cpu@500 { + cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x500>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD5>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_500>; + next-level-cache =3D <&l2_500>; operating-points-v2 =3D <&cpu4_opp_table>; capacity-dmips-mhz =3D <1946>; dynamic-power-coefficient =3D <520>; @@ -334,23 +334,23 @@ CPU5: cpu@500 { <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; - L2_500: l2-cache { + l2_500: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU6: cpu@600 { + cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x600>; clocks =3D <&cpufreq_hw 1>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD6>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_600>; + next-level-cache =3D <&l2_600>; operating-points-v2 =3D <&cpu4_opp_table>; capacity-dmips-mhz =3D <1946>; dynamic-power-coefficient =3D <520>; @@ -358,23 +358,23 @@ CPU6: cpu@600 { <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; - L2_600: l2-cache { + l2_600: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU7: cpu@700 { + cpu7: cpu@700 { device_type =3D "cpu"; compatible =3D "qcom,kryo"; reg =3D <0x0 0x700>; clocks =3D <&cpufreq_hw 2>; enable-method =3D "psci"; - power-domains =3D <&CPU_PD7>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; - next-level-cache =3D <&L2_700>; + next-level-cache =3D <&l2_700>; operating-points-v2 =3D <&cpu7_opp_table>; capacity-dmips-mhz =3D <1985>; dynamic-power-coefficient =3D <552>; @@ -382,46 +382,46 @@ CPU7: cpu@700 { <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain =3D <&cpufreq_hw 2>; #cooling-cells =3D <2>; - L2_700: l2-cache { + l2_700: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 core4 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core5 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core6 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core7 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -429,7 +429,7 @@ core7 { idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + little_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "little-power-down"; arm,psci-suspend-param =3D <0x40000003>; @@ -439,7 +439,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { + little_cpu_sleep_1: cpu-sleep-0-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "little-rail-power-down"; arm,psci-suspend-param =3D <0x40000004>; @@ -449,7 +449,7 @@ LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + big_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "big-power-down"; arm,psci-suspend-param =3D <0x40000003>; @@ -459,7 +459,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_1: cpu-sleep-1-1 { + big_cpu_sleep_1: cpu-sleep-1-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "big-rail-power-down"; arm,psci-suspend-param =3D <0x40000004>; @@ -471,7 +471,7 @@ BIG_CPU_SLEEP_1: cpu-sleep-1-1 { }; =20 domain_idle_states: domain-idle-states { - CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { + cluster_sleep_apss_off: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000044>; entry-latency-us =3D <2752>; @@ -479,7 +479,7 @@ CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { min-residency-us =3D <6118>; }; =20 - CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { + cluster_sleep_cx_ret: cluster-sleep-1 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41001344>; entry-latency-us =3D <3263>; @@ -487,7 +487,7 @@ CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { min-residency-us =3D <8467>; }; =20 - CLUSTER_SLEEP_LLCC_OFF: cluster-sleep-2 { + cluster_sleep_llcc_off: cluster-sleep-2 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x4100b344>; entry-latency-us =3D <3638>; @@ -854,57 +854,57 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; =20 - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; =20 - CLUSTER_PD: power-domain-cluster { + cluster_pd: power-domain-cluster { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_CX_RET &= CLUSTER_SLEEP_LLCC_OFF>; + domain-idle-states =3D <&cluster_sleep_apss_off &cluster_sleep_cx_ret &= cluster_sleep_llcc_off>; }; }; =20 @@ -3278,7 +3278,7 @@ etm@7040000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07040000 0 0x1000>; =20 - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3298,7 +3298,7 @@ etm@7140000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07140000 0 0x1000>; =20 - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3318,7 +3318,7 @@ etm@7240000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07240000 0 0x1000>; =20 - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3338,7 +3338,7 @@ etm@7340000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07340000 0 0x1000>; =20 - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3358,7 +3358,7 @@ etm@7440000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07440000 0 0x1000>; =20 - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3378,7 +3378,7 @@ etm@7540000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07540000 0 0x1000>; =20 - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3398,7 +3398,7 @@ etm@7640000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07640000 0 0x1000>; =20 - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3418,7 +3418,7 @@ etm@7740000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07740000 0 0x1000>; =20 - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -6057,7 +6057,7 @@ apps_rsc: rsc@18200000 { , , ; - power-domains =3D <&CLUSTER_PD>; + power-domains =3D <&cluster_pd>; =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; @@ -6177,17 +6177,17 @@ cpu0_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu0_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu0_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6220,17 +6220,17 @@ cpu1_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu1_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu1_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6263,17 +6263,17 @@ cpu2_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu2_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu2_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6306,17 +6306,17 @@ cpu3_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu3_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu3_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6349,17 +6349,17 @@ cpu4_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu4_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu4_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6392,17 +6392,17 @@ cpu5_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu5_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu5_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6435,17 +6435,17 @@ cpu6_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu6_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu6_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6478,17 +6478,17 @@ cpu7_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu7_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu7_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6521,17 +6521,17 @@ cpu8_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu8_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu8_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6564,17 +6564,17 @@ cpu9_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu9_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu9_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6607,17 +6607,17 @@ cpu10_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu10_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu10_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6650,17 +6650,17 @@ cpu11_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu11_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu11_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qc= om/sc8180x.dtsi index 0e9429684dd9..0828ebd58515 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -42,28 +42,28 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x0>; enable-method =3D "psci"; capacity-dmips-mhz =3D <602>; - next-level-cache =3D <&L2_0>; + next-level-cache =3D <&l2_0>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; clocks =3D <&cpufreq_hw 0>; =20 - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; - L3_0: l3-cache { + next-level-cache =3D <&l3_0>; + l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; @@ -71,207 +71,207 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x100>; enable-method =3D "psci"; capacity-dmips-mhz =3D <602>; - next-level-cache =3D <&L2_100>; + next-level-cache =3D <&l2_100>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD1>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; clocks =3D <&cpufreq_hw 0>; =20 - L2_100: l2-cache { + l2_100: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; =20 }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x200>; enable-method =3D "psci"; capacity-dmips-mhz =3D <602>; - next-level-cache =3D <&L2_200>; + next-level-cache =3D <&l2_200>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD2>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; clocks =3D <&cpufreq_hw 0>; =20 - L2_200: l2-cache { + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x300>; enable-method =3D "psci"; capacity-dmips-mhz =3D <602>; - next-level-cache =3D <&L2_300>; + next-level-cache =3D <&l2_300>; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD3>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; clocks =3D <&cpufreq_hw 0>; =20 - L2_300: l2-cache { + l2_300: l2-cache { compatible =3D "cache"; cache-unified; cache-level =3D <2>; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU4: cpu@400 { + cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x400>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_400>; + next-level-cache =3D <&l2_400>; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD4>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; clocks =3D <&cpufreq_hw 1>; =20 - L2_400: l2-cache { + l2_400: l2-cache { compatible =3D "cache"; cache-unified; cache-level =3D <2>; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU5: cpu@500 { + cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x500>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_500>; + next-level-cache =3D <&l2_500>; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD5>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; clocks =3D <&cpufreq_hw 1>; =20 - L2_500: l2-cache { + l2_500: l2-cache { compatible =3D "cache"; cache-unified; cache-level =3D <2>; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU6: cpu@600 { + cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x600>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_600>; + next-level-cache =3D <&l2_600>; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD6>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; clocks =3D <&cpufreq_hw 1>; =20 - L2_600: l2-cache { + l2_600: l2-cache { compatible =3D "cache"; cache-unified; cache-level =3D <2>; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU7: cpu@700 { + cpu7: cpu@700 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x700>; enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; - next-level-cache =3D <&L2_700>; + next-level-cache =3D <&l2_700>; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - power-domains =3D <&CPU_PD7>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; #cooling-cells =3D <2>; clocks =3D <&cpufreq_hw 1>; =20 - L2_700: l2-cache { + l2_700: l2-cache { compatible =3D "cache"; cache-unified; cache-level =3D <2>; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 core4 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core5 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core6 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core7 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -279,7 +279,7 @@ core7 { idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + little_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; arm,psci-suspend-param =3D <0x40000004>; entry-latency-us =3D <355>; @@ -288,7 +288,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + big_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; arm,psci-suspend-param =3D <0x40000004>; entry-latency-us =3D <2411>; @@ -299,7 +299,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { }; =20 domain-idle-states { - CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { + cluster_sleep_apss_off: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x41000044>; entry-latency-us =3D <3300>; @@ -307,7 +307,7 @@ CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { min-residency-us =3D <6000>; }; =20 - CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 { + cluster_sleep_aoss_sleep: cluster-sleep-1 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x4100a344>; entry-latency-us =3D <3263>; @@ -541,57 +541,57 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CLUSTER_PD: power-domain-cpu-cluster0 { + cluster_pd: power-domain-cpu-cluster0 { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLE= EP>; + domain-idle-states =3D <&cluster_sleep_apss_off &cluster_sleep_aoss_sle= ep>; }; }; =20 @@ -3790,7 +3790,7 @@ apps_rsc: rsc@18200000 { , ; label =3D "apps_rsc"; - power-domains =3D <&CLUSTER_PD>; + power-domains =3D <&cluster_pd>; =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; @@ -3868,7 +3868,7 @@ lmh@18350800 { compatible =3D "qcom,sc8180x-lmh"; reg =3D <0 0x18350800 0 0x400>; interrupts =3D ; - cpus =3D <&CPU4>; + cpus =3D <&cpu4>; qcom,lmh-temp-arm-millicelsius =3D <65000>; qcom,lmh-temp-low-millicelsius =3D <94500>; qcom,lmh-temp-high-millicelsius =3D <95000>; @@ -3880,7 +3880,7 @@ lmh@18358800 { compatible =3D "qcom,sc8180x-lmh"; reg =3D <0 0x18358800 0 0x400>; interrupts =3D ; - cpus =3D <&CPU0>; + cpus =3D <&cpu0>; qcom,lmh-temp-arm-millicelsius =3D <65000>; qcom,lmh-temp-low-millicelsius =3D <94500>; qcom,lmh-temp-high-millicelsius =3D <95000>; --=20 2.43.0