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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240829-dts-qcom-label-v2-10-5deaada3e6b2@linaro.org> References: <20240829-dts-qcom-label-v2-0-5deaada3e6b2@linaro.org> In-Reply-To: <20240829-dts-qcom-label-v2-0-5deaada3e6b2@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=28409; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=yCGlG4b7EtQdP90ej1j49YSm1bJURc6Ztfr5uZKbLIU=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBm0Grup7Pa/yRN6P5Y3dO5Z3Dt5XymGHmHbX+MA o3Viso8f++JAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZtBq7gAKCRDBN2bmhouD 1/KBD/9q9D3nxAgI0TeoRYnG0L2BEHG4CgKSbnSYIsSQnXVOWptGykIa0WyOIV2vX8rGTTl4DiF IeZfSG7Q/JEW7JdvWR78j3I91lnilSqtiwXr7tEBI/9aOk8saL3YGes2gz3b3+EfideEUK8eOiw 3T12y2aWJQ0GLjCwiSeYHFL3AYYrV0UpPazKcngHXIaOYZb/RKCLptnEQ188s/z4N3qvrJEWErz N/zVjH8FgYofq9p9hupTW+ct7NcjjKZzlU7gqNri3fqyTgPukRRjFxffGgDcASU+y6Q4XXzR/L5 2YuaEWqqHsbUwP2GC8D02bI2frBa7WfniGEimUcN6wlWdT53PAgR4S2+Yhqs+3fBV1OQ4jgMmjV mKllWI8OWTgMPDLgdITsTE52PJNLLz5mVcp3yEN0BvOma7BWjrwQOyGoYvDOuRcXYE9zxggprA8 LebgAKT/2V3ig8AIJ4wL8Km5LlgEJv07SIe3Cs6EGU0RKjdWHgUb9r1eWRmEDavdQAnn1i2s3sL 2kY6TTQ98to/4CoJMqTm2J/ANYLspGfmIgUWFsaRoq4DWu4LoEZoCFY2t6n6eb2dQjVCc7v/REv 59wxgGE3ignFWz7GDd+MXzf4A1LOaoiKAh2LVNQog6EYBjiOAfE5L0g+BR3WGCnslzs63Bdthq8 Nf9rhhU3kuvWDYg== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 4 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 366 +++++++++++++++------------= ---- 2 files changed, 185 insertions(+), 185 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts= /qcom/qrb5165-rb5.dts index ccff6cd73fdf..52eef88e882c 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -32,7 +32,7 @@ chosen { }; =20 /* Fixed crystal oscillator dedicated to MCP2518FD */ - clk40M: can-clock { + clk40m: can-clock { compatible =3D "fixed-clock"; #clock-cells =3D <0>; clock-frequency =3D <40000000>; @@ -1118,7 +1118,7 @@ &spi0 { can@0 { compatible =3D "microchip,mcp2518fd"; reg =3D <0>; - clocks =3D <&clk40M>; + clocks =3D <&clk40m>; interrupts-extended =3D <&tlmm 15 IRQ_TYPE_LEVEL_LOW>; spi-max-frequency =3D <10000000>; vdd-supply =3D <&vdc_5v>; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index 630f4eff20bf..48318ed1ce98 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -93,7 +93,7 @@ cpus { #address-cells =3D <2>; #size-cells =3D <0>; =20 - CPU0: cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x0>; @@ -101,21 +101,21 @@ CPU0: cpu@0 { enable-method =3D "psci"; capacity-dmips-mhz =3D <448>; dynamic-power-coefficient =3D <105>; - next-level-cache =3D <&L2_0>; - power-domains =3D <&CPU_PD0>; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd0>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; - L2_0: l2-cache { + l2_0: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-size =3D <0x20000>; cache-unified; - next-level-cache =3D <&L3_0>; - L3_0: l3-cache { + next-level-cache =3D <&l3_0>; + l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-size =3D <0x400000>; @@ -124,7 +124,7 @@ L3_0: l3-cache { }; }; =20 - CPU1: cpu@100 { + cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x100>; @@ -132,24 +132,24 @@ CPU1: cpu@100 { enable-method =3D "psci"; capacity-dmips-mhz =3D <448>; dynamic-power-coefficient =3D <105>; - next-level-cache =3D <&L2_100>; - power-domains =3D <&CPU_PD1>; + next-level-cache =3D <&l2_100>; + power-domains =3D <&cpu_pd1>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; - L2_100: l2-cache { + l2_100: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-size =3D <0x20000>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU2: cpu@200 { + cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x200>; @@ -157,24 +157,24 @@ CPU2: cpu@200 { enable-method =3D "psci"; capacity-dmips-mhz =3D <448>; dynamic-power-coefficient =3D <105>; - next-level-cache =3D <&L2_200>; - power-domains =3D <&CPU_PD2>; + next-level-cache =3D <&l2_200>; + power-domains =3D <&cpu_pd2>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; - L2_200: l2-cache { + l2_200: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-size =3D <0x20000>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU3: cpu@300 { + cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x300>; @@ -182,24 +182,24 @@ CPU3: cpu@300 { enable-method =3D "psci"; capacity-dmips-mhz =3D <448>; dynamic-power-coefficient =3D <105>; - next-level-cache =3D <&L2_300>; - power-domains =3D <&CPU_PD3>; + next-level-cache =3D <&l2_300>; + power-domains =3D <&cpu_pd3>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; - L2_300: l2-cache { + l2_300: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-size =3D <0x20000>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU4: cpu@400 { + cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x400>; @@ -207,24 +207,24 @@ CPU4: cpu@400 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <379>; - next-level-cache =3D <&L2_400>; - power-domains =3D <&CPU_PD4>; + next-level-cache =3D <&l2_400>; + power-domains =3D <&cpu_pd4>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; - L2_400: l2-cache { + l2_400: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-size =3D <0x40000>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU5: cpu@500 { + cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x500>; @@ -232,24 +232,24 @@ CPU5: cpu@500 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <379>; - next-level-cache =3D <&L2_500>; - power-domains =3D <&CPU_PD5>; + next-level-cache =3D <&l2_500>; + power-domains =3D <&cpu_pd5>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; - L2_500: l2-cache { + l2_500: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-size =3D <0x40000>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU6: cpu@600 { + cpu6: cpu@600 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x600>; @@ -257,24 +257,24 @@ CPU6: cpu@600 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <379>; - next-level-cache =3D <&L2_600>; - power-domains =3D <&CPU_PD6>; + next-level-cache =3D <&l2_600>; + power-domains =3D <&cpu_pd6>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; - L2_600: l2-cache { + l2_600: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-size =3D <0x40000>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 - CPU7: cpu@700 { + cpu7: cpu@700 { device_type =3D "cpu"; compatible =3D "qcom,kryo485"; reg =3D <0x0 0x700>; @@ -282,55 +282,55 @@ CPU7: cpu@700 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <444>; - next-level-cache =3D <&L2_700>; - power-domains =3D <&CPU_PD7>; + next-level-cache =3D <&l2_700>; + power-domains =3D <&cpu_pd7>; power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 2>; operating-points-v2 =3D <&cpu7_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; #cooling-cells =3D <2>; - L2_700: l2-cache { + l2_700: l2-cache { compatible =3D "cache"; cache-level =3D <2>; cache-size =3D <0x80000>; cache-unified; - next-level-cache =3D <&L3_0>; + next-level-cache =3D <&l3_0>; }; }; =20 cpu-map { cluster0 { core0 { - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; }; =20 core1 { - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; }; =20 core2 { - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; }; =20 core3 { - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; }; =20 core4 { - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; }; =20 core5 { - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; }; =20 core6 { - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; }; =20 core7 { - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; }; }; }; @@ -338,7 +338,7 @@ core7 { idle-states { entry-method =3D "psci"; =20 - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + little_cpu_sleep_0: cpu-sleep-0-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "silver-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -348,7 +348,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { local-timer-stop; }; =20 - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + big_cpu_sleep_0: cpu-sleep-1-0 { compatible =3D "arm,idle-state"; idle-state-name =3D "gold-rail-power-collapse"; arm,psci-suspend-param =3D <0x40000004>; @@ -360,7 +360,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { }; =20 domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + cluster_sleep_0: cluster-sleep-0 { compatible =3D "domain-idle-state"; arm,psci-suspend-param =3D <0x4100c244>; entry-latency-us =3D <3264>; @@ -689,57 +689,57 @@ psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>; }; =20 - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells =3D <0>; - power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>; }; =20 - CLUSTER_PD: power-domain-cpu-cluster0 { + cluster_pd: power-domain-cpu-cluster0 { #power-domain-cells =3D <0>; - domain-idle-states =3D <&CLUSTER_SLEEP_0>; + domain-idle-states =3D <&cluster_sleep_0>; }; }; =20 @@ -3522,7 +3522,7 @@ etm@7040000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07040000 0 0x1000>; =20 - cpu =3D <&CPU0>; + cpu =3D <&cpu0>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3541,7 +3541,7 @@ etm@7140000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07140000 0 0x1000>; =20 - cpu =3D <&CPU1>; + cpu =3D <&cpu1>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3560,7 +3560,7 @@ etm@7240000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07240000 0 0x1000>; =20 - cpu =3D <&CPU2>; + cpu =3D <&cpu2>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3579,7 +3579,7 @@ etm@7340000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07340000 0 0x1000>; =20 - cpu =3D <&CPU3>; + cpu =3D <&cpu3>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3598,7 +3598,7 @@ etm@7440000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07440000 0 0x1000>; =20 - cpu =3D <&CPU4>; + cpu =3D <&cpu4>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3617,7 +3617,7 @@ etm@7540000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07540000 0 0x1000>; =20 - cpu =3D <&CPU5>; + cpu =3D <&cpu5>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3636,7 +3636,7 @@ etm@7640000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07640000 0 0x1000>; =20 - cpu =3D <&CPU6>; + cpu =3D <&cpu6>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -3655,7 +3655,7 @@ etm@7740000 { compatible =3D "arm,coresight-etm4x", "arm,primecell"; reg =3D <0 0x07740000 0 0x1000>; =20 - cpu =3D <&CPU7>; + cpu =3D <&cpu7>; =20 clocks =3D <&aoss_qmp>; clock-names =3D "apb_pclk"; @@ -6165,7 +6165,7 @@ apps_rsc: rsc@18200000 { qcom,drv-id =3D <2>; qcom,tcs-config =3D , , , ; - power-domains =3D <&CLUSTER_PD>; + power-domains =3D <&cluster_pd>; =20 rpmhcc: clock-controller { compatible =3D "qcom,sm8250-rpmh-clk"; @@ -6302,17 +6302,17 @@ cpu0_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu0_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu0_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6345,17 +6345,17 @@ cpu1_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu1_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu1_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6388,17 +6388,17 @@ cpu2_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu2_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu2_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6431,17 +6431,17 @@ cpu3_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu3_alert0>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu3_alert1>; - cooling-device =3D <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6474,17 +6474,17 @@ cpu4_top_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu4_top_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu4_top_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6517,17 +6517,17 @@ cpu5_top_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu5_top_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu5_top_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6560,17 +6560,17 @@ cpu6_top_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu6_top_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu6_top_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6603,17 +6603,17 @@ cpu7_top_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu7_top_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu7_top_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6646,17 +6646,17 @@ cpu4_bottom_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu4_bottom_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu4_bottom_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6689,17 +6689,17 @@ cpu5_bottom_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu5_bottom_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu5_bottom_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6732,17 +6732,17 @@ cpu6_bottom_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu6_bottom_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu6_bottom_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -6775,17 +6775,17 @@ cpu7_bottom_crit: cpu-crit { cooling-maps { map0 { trip =3D <&cpu7_bottom_alert0>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip =3D <&cpu7_bottom_alert1>; - cooling-device =3D <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; --=20 2.43.0